1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2016 Broadcom
4 * Author: Jayachandran C <jchandra@broadcom.com>
5 * Copyright (C) 2016 Semihalf
6 * Author: Tomasz Nowicki <tn@semihalf.com>
7 */
8
9 #define pr_fmt(fmt) "ACPI: " fmt
10
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/pci-acpi.h>
14 #include <linux/pci-ecam.h>
15
16 /* Structure to hold entries from the MCFG table */
17 struct mcfg_entry {
18 struct list_head list;
19 phys_addr_t addr;
20 u16 segment;
21 u8 bus_start;
22 u8 bus_end;
23 };
24
25 #ifdef CONFIG_PCI_QUIRKS
26 struct mcfg_fixup {
27 char oem_id[ACPI_OEM_ID_SIZE + 1];
28 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
29 u32 oem_revision;
30 u16 segment;
31 struct resource bus_range;
32 const struct pci_ecam_ops *ops;
33 struct resource cfgres;
34 };
35
36 #define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \
37 ((end) - (start) + 1), \
38 NULL, IORESOURCE_BUS)
39 #define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff)
40
41 static struct mcfg_fixup mcfg_quirks[] = {
42 /* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
43
44 #ifdef CONFIG_ARM64
45
46 #define AL_ECAM(table_id, rev, seg, ops) \
47 { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
48
49 AL_ECAM("GRAVITON", 0, 0, &al_pcie_ops),
50 AL_ECAM("GRAVITON", 0, 1, &al_pcie_ops),
51 AL_ECAM("GRAVITON", 0, 2, &al_pcie_ops),
52 AL_ECAM("GRAVITON", 0, 3, &al_pcie_ops),
53 AL_ECAM("GRAVITON", 0, 4, &al_pcie_ops),
54 AL_ECAM("GRAVITON", 0, 5, &al_pcie_ops),
55 AL_ECAM("GRAVITON", 0, 6, &al_pcie_ops),
56 AL_ECAM("GRAVITON", 0, 7, &al_pcie_ops),
57
58 #define QCOM_ECAM32(seg) \
59 { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
60
61 QCOM_ECAM32(0),
62 QCOM_ECAM32(1),
63 QCOM_ECAM32(2),
64 QCOM_ECAM32(3),
65 QCOM_ECAM32(4),
66 QCOM_ECAM32(5),
67 QCOM_ECAM32(6),
68 QCOM_ECAM32(7),
69
70 #define RKCP_ECAM(seg, table_id, ops) \
71 { "RKCP ", table_id, 0x0000, seg, MCFG_BUS_ANY, ops }
72
73 RKCP_ECAM(0, "RK3588 ", &rk_pcie_ecam_ops), /* pcie3x4: Name (_SEG, Zero) */
74
75 #define HISI_QUAD_DOM(table_id, seg, ops) \
76 { "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
77 { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
78 { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
79 { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
80
81 HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
82 HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
83 HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
84 HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops),
85 HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops),
86 HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops),
87
88 #define THUNDER_PEM_RES(addr, node) \
89 DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
90
91 #define THUNDER_PEM_QUIRK(rev, node) \
92 { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
93 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \
94 { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \
95 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \
96 { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \
97 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) }, \
98 { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \
99 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) }, \
100 { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \
101 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \
102 { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
103 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
104
105 #define THUNDER_ECAM_QUIRK(rev, seg) \
106 { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
107 &pci_thunder_ecam_ops }
108
109 /* SoC pass2.x */
110 THUNDER_PEM_QUIRK(1, 0),
111 THUNDER_PEM_QUIRK(1, 1),
112 THUNDER_ECAM_QUIRK(1, 10),
113
114 /* SoC pass1.x */
115 THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */
116 THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */
117 THUNDER_ECAM_QUIRK(2, 0),
118 THUNDER_ECAM_QUIRK(2, 1),
119 THUNDER_ECAM_QUIRK(2, 2),
120 THUNDER_ECAM_QUIRK(2, 3),
121 THUNDER_ECAM_QUIRK(2, 10),
122 THUNDER_ECAM_QUIRK(2, 11),
123 THUNDER_ECAM_QUIRK(2, 12),
124 THUNDER_ECAM_QUIRK(2, 13),
125
126 #define XGENE_V1_ECAM_MCFG(rev, seg) \
127 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
128 &xgene_v1_pcie_ecam_ops }
129
130 #define XGENE_V2_ECAM_MCFG(rev, seg) \
131 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
132 &xgene_v2_pcie_ecam_ops }
133
134 /* X-Gene SoC with v1 PCIe controller */
135 XGENE_V1_ECAM_MCFG(1, 0),
136 XGENE_V1_ECAM_MCFG(1, 1),
137 XGENE_V1_ECAM_MCFG(1, 2),
138 XGENE_V1_ECAM_MCFG(1, 3),
139 XGENE_V1_ECAM_MCFG(1, 4),
140 XGENE_V1_ECAM_MCFG(2, 0),
141 XGENE_V1_ECAM_MCFG(2, 1),
142 XGENE_V1_ECAM_MCFG(2, 2),
143 XGENE_V1_ECAM_MCFG(2, 3),
144 XGENE_V1_ECAM_MCFG(2, 4),
145 /* X-Gene SoC with v2.1 PCIe controller */
146 XGENE_V2_ECAM_MCFG(3, 0),
147 XGENE_V2_ECAM_MCFG(3, 1),
148 /* X-Gene SoC with v2.2 PCIe controller */
149 XGENE_V2_ECAM_MCFG(4, 0),
150 XGENE_V2_ECAM_MCFG(4, 1),
151 XGENE_V2_ECAM_MCFG(4, 2),
152
153 #define ALTRA_ECAM_QUIRK(rev, seg) \
154 { "Ampere", "Altra ", rev, seg, MCFG_BUS_ANY, &pci_32b_read_ops }
155
156 ALTRA_ECAM_QUIRK(1, 0),
157 ALTRA_ECAM_QUIRK(1, 1),
158 ALTRA_ECAM_QUIRK(1, 2),
159 ALTRA_ECAM_QUIRK(1, 3),
160 ALTRA_ECAM_QUIRK(1, 4),
161 ALTRA_ECAM_QUIRK(1, 5),
162 ALTRA_ECAM_QUIRK(1, 6),
163 ALTRA_ECAM_QUIRK(1, 7),
164 ALTRA_ECAM_QUIRK(1, 8),
165 ALTRA_ECAM_QUIRK(1, 9),
166 ALTRA_ECAM_QUIRK(1, 10),
167 ALTRA_ECAM_QUIRK(1, 11),
168 ALTRA_ECAM_QUIRK(1, 12),
169 ALTRA_ECAM_QUIRK(1, 13),
170 ALTRA_ECAM_QUIRK(1, 14),
171 ALTRA_ECAM_QUIRK(1, 15),
172 #endif /* ARM64 */
173 };
174
175 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
176 static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
177 static u32 mcfg_oem_revision;
178
pci_mcfg_quirk_matches(struct mcfg_fixup * f,u16 segment,struct resource * bus_range)179 static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
180 struct resource *bus_range)
181 {
182 if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
183 !memcmp(f->oem_table_id, mcfg_oem_table_id,
184 ACPI_OEM_TABLE_ID_SIZE) &&
185 f->oem_revision == mcfg_oem_revision &&
186 f->segment == segment &&
187 resource_contains(&f->bus_range, bus_range))
188 return 1;
189
190 return 0;
191 }
192 #endif
193
pci_mcfg_apply_quirks(struct acpi_pci_root * root,struct resource * cfgres,const struct pci_ecam_ops ** ecam_ops)194 static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
195 struct resource *cfgres,
196 const struct pci_ecam_ops **ecam_ops)
197 {
198 #ifdef CONFIG_PCI_QUIRKS
199 u16 segment = root->segment;
200 struct resource *bus_range = &root->secondary;
201 struct mcfg_fixup *f;
202 int i;
203
204 for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
205 if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
206 if (f->cfgres.start)
207 *cfgres = f->cfgres;
208 if (f->ops)
209 *ecam_ops = f->ops;
210 dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
211 cfgres, bus_range, *ecam_ops);
212 return;
213 }
214 }
215 #endif
216 }
217
218 /* List to save MCFG entries */
219 static LIST_HEAD(pci_mcfg_list);
220
pci_mcfg_lookup(struct acpi_pci_root * root,struct resource * cfgres,const struct pci_ecam_ops ** ecam_ops)221 int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
222 const struct pci_ecam_ops **ecam_ops)
223 {
224 const struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
225 struct resource *bus_res = &root->secondary;
226 u16 seg = root->segment;
227 struct mcfg_entry *e;
228 struct resource res;
229
230 /* Use address from _CBA if present, otherwise lookup MCFG */
231 if (root->mcfg_addr)
232 goto skip_lookup;
233
234 /*
235 * We expect the range in bus_res in the coverage of MCFG bus range.
236 */
237 list_for_each_entry(e, &pci_mcfg_list, list) {
238 if (e->segment == seg && e->bus_start <= bus_res->start &&
239 e->bus_end >= bus_res->end) {
240 root->mcfg_addr = e->addr;
241 }
242
243 }
244
245 skip_lookup:
246 memset(&res, 0, sizeof(res));
247 if (root->mcfg_addr) {
248 res.start = root->mcfg_addr + (bus_res->start << 20);
249 res.end = res.start + (resource_size(bus_res) << 20) - 1;
250 res.flags = IORESOURCE_MEM;
251 }
252
253 /*
254 * Allow quirks to override default ECAM ops and CFG resource
255 * range. This may even fabricate a CFG resource range in case
256 * MCFG does not have it. Invalid CFG start address means MCFG
257 * firmware bug or we need another quirk in array.
258 */
259 pci_mcfg_apply_quirks(root, &res, &ops);
260 if (!res.start)
261 return -ENXIO;
262
263 *cfgres = res;
264 *ecam_ops = ops;
265 return 0;
266 }
267
pci_mcfg_parse(struct acpi_table_header * header)268 static __init int pci_mcfg_parse(struct acpi_table_header *header)
269 {
270 struct acpi_table_mcfg *mcfg;
271 struct acpi_mcfg_allocation *mptr;
272 struct mcfg_entry *e, *arr;
273 int i, n;
274
275 if (header->length < sizeof(struct acpi_table_mcfg))
276 return -EINVAL;
277
278 n = (header->length - sizeof(struct acpi_table_mcfg)) /
279 sizeof(struct acpi_mcfg_allocation);
280 mcfg = (struct acpi_table_mcfg *)header;
281 mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
282
283 arr = kcalloc(n, sizeof(*arr), GFP_KERNEL);
284 if (!arr)
285 return -ENOMEM;
286
287 for (i = 0, e = arr; i < n; i++, mptr++, e++) {
288 e->segment = mptr->pci_segment;
289 e->addr = mptr->address;
290 e->bus_start = mptr->start_bus_number;
291 e->bus_end = mptr->end_bus_number;
292 list_add(&e->list, &pci_mcfg_list);
293 }
294
295 #ifdef CONFIG_PCI_QUIRKS
296 /* Save MCFG IDs and revision for quirks matching */
297 memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
298 memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
299 mcfg_oem_revision = header->oem_revision;
300 #endif
301
302 pr_info("MCFG table detected, %d entries\n", n);
303 return 0;
304 }
305
306 /* Interface called by ACPI - parse and save MCFG table */
pci_mmcfg_late_init(void)307 void __init pci_mmcfg_late_init(void)
308 {
309 int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
310 if (err)
311 pr_debug("Failed to parse MCFG (%d)\n", err);
312 }
313