1 /*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/iopoll.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/spi/spi.h>
32
33 #include <video/display_timing.h>
34 #include <video/mipi_display.h>
35 #include <video/of_display_timing.h>
36 #include <video/videomode.h>
37
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_device.h>
40 #include <drm/drm_mipi_dsi.h>
41 #include <drm/drm_panel.h>
42 #include <drm/drm_dsc.h>
43
44 #include "panel-simple.h"
45
46 enum panel_simple_cmd_type {
47 CMD_TYPE_DEFAULT,
48 CMD_TYPE_SPI
49 };
50
51 struct panel_cmd_header {
52 u8 data_type;
53 u8 delay;
54 u8 payload_length;
55 } __packed;
56
57 struct panel_cmd_desc {
58 struct panel_cmd_header header;
59 u8 *payload;
60 };
61
62 struct panel_cmd_seq {
63 struct panel_cmd_desc *cmds;
64 unsigned int cmd_cnt;
65 };
66
67 /**
68 * @modes: Pointer to array of fixed modes appropriate for this panel. If
69 * only one mode then this can just be the address of this the mode.
70 * NOTE: cannot be used with "timings" and also if this is specified
71 * then you cannot override the mode in the device tree.
72 * @num_modes: Number of elements in modes array.
73 * @timings: Pointer to array of display timings. NOTE: cannot be used with
74 * "modes" and also these will be used to validate a device tree
75 * override if one is present.
76 * @num_timings: Number of elements in timings array.
77 * @bpc: Bits per color.
78 * @size: Structure containing the physical size of this panel.
79 * @delay: Structure containing various delay values for this panel.
80 * @bus_format: See MEDIA_BUS_FMT_... defines.
81 * @bus_flags: See DRM_BUS_FLAG_... defines.
82 */
83 struct panel_desc {
84 const struct drm_display_mode *modes;
85 unsigned int num_modes;
86 const struct display_timing *timings;
87 unsigned int num_timings;
88
89 unsigned int bpc;
90
91 /**
92 * @width: width (in millimeters) of the panel's active display area
93 * @height: height (in millimeters) of the panel's active display area
94 */
95 struct {
96 unsigned int width;
97 unsigned int height;
98 } size;
99
100 /**
101 * @prepare: the time (in milliseconds) that it takes for the panel to
102 * become ready and start receiving video data
103 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
104 * Plug Detect isn't used.
105 * @enable: the time (in milliseconds) that it takes for the panel to
106 * display the first valid frame after starting to receive
107 * video data
108 * @disable: the time (in milliseconds) that it takes for the panel to
109 * turn the display off (no content is visible)
110 * @unprepare: the time (in milliseconds) that it takes for the panel
111 * to power itself down completely
112 * @reset: the time (in milliseconds) that it takes for the panel
113 * to reset itself completely
114 * @init: the time (in milliseconds) that it takes for the panel to
115 * send init command sequence after reset deassert
116 */
117 struct {
118 unsigned int prepare;
119 unsigned int hpd_absent_delay;
120 unsigned int enable;
121 unsigned int disable;
122 unsigned int unprepare;
123 unsigned int reset;
124 unsigned int init;
125 } delay;
126
127 u32 bus_format;
128 u32 bus_flags;
129 int connector_type;
130
131 struct panel_cmd_seq *init_seq;
132 struct panel_cmd_seq *exit_seq;
133
134 enum panel_simple_cmd_type cmd_type;
135
136 int (*spi_read)(struct device *dev, const u8 cmd, u8 *val);
137 int (*spi_write)(struct device *dev, const u8 *data, size_t len, u8 type);
138 };
139
140 struct panel_simple {
141 struct drm_panel base;
142 struct mipi_dsi_device *dsi;
143 bool prepared;
144 bool enabled;
145 bool power_invert;
146 bool no_hpd;
147
148 const struct panel_desc *desc;
149
150 struct regulator *supply;
151 struct i2c_adapter *ddc;
152
153 struct gpio_desc *enable_gpio;
154 struct gpio_desc *reset_gpio;
155 struct gpio_desc *hpd_gpio;
156
157 struct drm_display_mode override_mode;
158
159 struct drm_dsc_picture_parameter_set *pps;
160 enum drm_panel_orientation orientation;
161 };
162
to_panel_simple(struct drm_panel * panel)163 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
164 {
165 return container_of(panel, struct panel_simple, base);
166 }
167
panel_simple_parse_cmd_seq(struct device * dev,const u8 * data,int length,struct panel_cmd_seq * seq)168 static int panel_simple_parse_cmd_seq(struct device *dev,
169 const u8 *data, int length,
170 struct panel_cmd_seq *seq)
171 {
172 struct panel_cmd_header *header;
173 struct panel_cmd_desc *desc;
174 char *buf, *d;
175 unsigned int i, cnt, len;
176
177 if (!seq)
178 return -EINVAL;
179
180 buf = devm_kmemdup(dev, data, length, GFP_KERNEL);
181 if (!buf)
182 return -ENOMEM;
183
184 d = buf;
185 len = length;
186 cnt = 0;
187 while (len > sizeof(*header)) {
188 header = (struct panel_cmd_header *)d;
189
190 d += sizeof(*header);
191 len -= sizeof(*header);
192
193 if (header->payload_length > len)
194 return -EINVAL;
195
196 d += header->payload_length;
197 len -= header->payload_length;
198 cnt++;
199 }
200
201 if (len)
202 return -EINVAL;
203
204 seq->cmd_cnt = cnt;
205 seq->cmds = devm_kcalloc(dev, cnt, sizeof(*desc), GFP_KERNEL);
206 if (!seq->cmds)
207 return -ENOMEM;
208
209 d = buf;
210 len = length;
211 for (i = 0; i < cnt; i++) {
212 header = (struct panel_cmd_header *)d;
213 len -= sizeof(*header);
214 d += sizeof(*header);
215
216 desc = &seq->cmds[i];
217 desc->header = *header;
218 desc->payload = d;
219
220 d += header->payload_length;
221 len -= header->payload_length;
222 }
223
224 return 0;
225 }
226
panel_simple_xfer_dsi_cmd_seq(struct panel_simple * panel,struct panel_cmd_seq * seq)227 static int panel_simple_xfer_dsi_cmd_seq(struct panel_simple *panel,
228 struct panel_cmd_seq *seq)
229 {
230 struct device *dev = panel->base.dev;
231 struct mipi_dsi_device *dsi = panel->dsi;
232 unsigned int i;
233 int err;
234
235 if (!IS_ENABLED(CONFIG_DRM_MIPI_DSI))
236 return -EINVAL;
237 if (!seq)
238 return -EINVAL;
239
240 for (i = 0; i < seq->cmd_cnt; i++) {
241 struct panel_cmd_desc *cmd = &seq->cmds[i];
242
243 switch (cmd->header.data_type) {
244 case MIPI_DSI_COMPRESSION_MODE:
245 err = mipi_dsi_compression_mode(dsi, cmd->payload[0]);
246 break;
247 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
248 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
249 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
250 case MIPI_DSI_GENERIC_LONG_WRITE:
251 err = mipi_dsi_generic_write(dsi, cmd->payload,
252 cmd->header.payload_length);
253 break;
254 case MIPI_DSI_DCS_SHORT_WRITE:
255 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
256 case MIPI_DSI_DCS_LONG_WRITE:
257 err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload,
258 cmd->header.payload_length);
259 break;
260 case MIPI_DSI_PICTURE_PARAMETER_SET:
261 if (!panel->pps) {
262 panel->pps = devm_kzalloc(dev, sizeof(*panel->pps),
263 GFP_KERNEL);
264 if (!panel->pps)
265 return -ENOMEM;
266
267 memcpy(panel->pps, cmd->payload, cmd->header.payload_length);
268 }
269
270 err = mipi_dsi_picture_parameter_set(dsi, panel->pps);
271 break;
272 default:
273 return -EINVAL;
274 }
275
276 if (err < 0)
277 dev_err(dev, "failed to write dcs cmd: %d\n", err);
278
279 if (cmd->header.delay)
280 msleep(cmd->header.delay);
281 }
282
283 return 0;
284 }
285
panel_simple_xfer_spi_cmd_seq(struct panel_simple * panel,struct panel_cmd_seq * cmds)286 static int panel_simple_xfer_spi_cmd_seq(struct panel_simple *panel, struct panel_cmd_seq *cmds)
287 {
288 int i;
289 int ret;
290
291 if (!cmds)
292 return -EINVAL;
293
294 for (i = 0; i < cmds->cmd_cnt; i++) {
295 struct panel_cmd_desc *cmd = &cmds->cmds[i];
296
297 ret = panel->desc->spi_write(panel->base.dev, cmd->payload,
298 cmd->header.payload_length, cmd->header.data_type);
299 if (ret)
300 return ret;
301
302 if (cmd->header.delay)
303 usleep_range(cmd->header.delay * 1000, (cmd->header.delay + 1) * 1000);
304 }
305
306 return 0;
307 }
308
panel_simple_get_timings_modes(struct panel_simple * panel,struct drm_connector * connector)309 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
310 struct drm_connector *connector)
311 {
312 struct drm_display_mode *mode;
313 unsigned int i, num = 0;
314
315 for (i = 0; i < panel->desc->num_timings; i++) {
316 const struct display_timing *dt = &panel->desc->timings[i];
317 struct videomode vm;
318
319 videomode_from_timing(dt, &vm);
320 mode = drm_mode_create(connector->dev);
321 if (!mode) {
322 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
323 dt->hactive.typ, dt->vactive.typ);
324 continue;
325 }
326
327 drm_display_mode_from_videomode(&vm, mode);
328
329 mode->type |= DRM_MODE_TYPE_DRIVER;
330
331 if (panel->desc->num_timings == 1)
332 mode->type |= DRM_MODE_TYPE_PREFERRED;
333
334 drm_mode_probed_add(connector, mode);
335 num++;
336 }
337
338 return num;
339 }
340
panel_simple_get_display_modes(struct panel_simple * panel,struct drm_connector * connector)341 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
342 struct drm_connector *connector)
343 {
344 struct drm_display_mode *mode;
345 unsigned int i, num = 0;
346
347 for (i = 0; i < panel->desc->num_modes; i++) {
348 const struct drm_display_mode *m = &panel->desc->modes[i];
349
350 mode = drm_mode_duplicate(connector->dev, m);
351 if (!mode) {
352 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
353 m->hdisplay, m->vdisplay,
354 drm_mode_vrefresh(m));
355 continue;
356 }
357
358 mode->type |= DRM_MODE_TYPE_DRIVER;
359
360 if (panel->desc->num_modes == 1)
361 mode->type |= DRM_MODE_TYPE_PREFERRED;
362
363 drm_mode_set_name(mode);
364
365 drm_mode_probed_add(connector, mode);
366 num++;
367 }
368
369 return num;
370 }
371
panel_simple_get_non_edid_modes(struct panel_simple * panel,struct drm_connector * connector)372 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
373 struct drm_connector *connector)
374 {
375 struct drm_display_mode *mode;
376 bool has_override = panel->override_mode.type;
377 unsigned int num = 0;
378
379 if (!panel->desc)
380 return 0;
381
382 if (has_override) {
383 mode = drm_mode_duplicate(connector->dev,
384 &panel->override_mode);
385 if (mode) {
386 drm_mode_probed_add(connector, mode);
387 num = 1;
388 } else {
389 dev_err(panel->base.dev, "failed to add override mode\n");
390 }
391 }
392
393 /* Only add timings if override was not there or failed to validate */
394 if (num == 0 && panel->desc->num_timings)
395 num = panel_simple_get_timings_modes(panel, connector);
396
397 /*
398 * Only add fixed modes if timings/override added no mode.
399 *
400 * We should only ever have either the display timings specified
401 * or a fixed mode. Anything else is rather bogus.
402 */
403 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
404 if (num == 0)
405 num = panel_simple_get_display_modes(panel, connector);
406
407 if (panel->desc->bpc)
408 connector->display_info.bpc = panel->desc->bpc;
409 if (panel->desc->size.width)
410 connector->display_info.width_mm = panel->desc->size.width;
411 if (panel->desc->size.height)
412 connector->display_info.height_mm = panel->desc->size.height;
413 if (panel->desc->bus_format)
414 drm_display_info_set_bus_formats(&connector->display_info,
415 &panel->desc->bus_format, 1);
416 if (panel->desc->bus_flags)
417 connector->display_info.bus_flags = panel->desc->bus_flags;
418
419 return num;
420 }
421
panel_simple_regulator_enable(struct panel_simple * p)422 static int panel_simple_regulator_enable(struct panel_simple *p)
423 {
424 int err;
425
426 if (p->power_invert) {
427 if (regulator_is_enabled(p->supply) > 0)
428 regulator_disable(p->supply);
429 } else {
430 err = regulator_enable(p->supply);
431 if (err < 0)
432 return err;
433 }
434
435 return 0;
436 }
437
panel_simple_regulator_disable(struct panel_simple * p)438 static int panel_simple_regulator_disable(struct panel_simple *p)
439 {
440 int err;
441
442 if (p->power_invert) {
443 if (!regulator_is_enabled(p->supply)) {
444 err = regulator_enable(p->supply);
445 if (err < 0)
446 return err;
447 }
448 } else {
449 regulator_disable(p->supply);
450 }
451
452 return 0;
453 }
454
panel_simple_loader_protect(struct drm_panel * panel)455 int panel_simple_loader_protect(struct drm_panel *panel)
456 {
457 struct panel_simple *p = to_panel_simple(panel);
458 int err;
459
460 err = panel_simple_regulator_enable(p);
461 if (err < 0) {
462 dev_err(panel->dev, "failed to enable supply: %d\n", err);
463 return err;
464 }
465
466 p->prepared = true;
467 p->enabled = true;
468
469 return 0;
470 }
471 EXPORT_SYMBOL(panel_simple_loader_protect);
472
panel_simple_disable(struct drm_panel * panel)473 static int panel_simple_disable(struct drm_panel *panel)
474 {
475 struct panel_simple *p = to_panel_simple(panel);
476
477 if (!p->enabled)
478 return 0;
479
480 if (p->desc->delay.disable)
481 msleep(p->desc->delay.disable);
482
483 p->enabled = false;
484
485 return 0;
486 }
487
panel_simple_unprepare(struct drm_panel * panel)488 static int panel_simple_unprepare(struct drm_panel *panel)
489 {
490 struct panel_simple *p = to_panel_simple(panel);
491
492 if (!p->prepared)
493 return 0;
494
495 if (p->desc->exit_seq) {
496 if (p->desc->cmd_type == CMD_TYPE_SPI) {
497 if (panel_simple_xfer_spi_cmd_seq(p, p->desc->exit_seq)) {
498 dev_err(panel->dev, "failed to send exit spi cmds seq\n");
499 return -EINVAL;
500 }
501 } else {
502 if (p->dsi)
503 panel_simple_xfer_dsi_cmd_seq(p, p->desc->exit_seq);
504 }
505 }
506
507 gpiod_direction_output(p->reset_gpio, 1);
508 gpiod_direction_output(p->enable_gpio, 0);
509
510 panel_simple_regulator_disable(p);
511
512 if (p->desc->delay.unprepare)
513 msleep(p->desc->delay.unprepare);
514
515 p->prepared = false;
516
517 return 0;
518 }
519
panel_simple_get_hpd_gpio(struct device * dev,struct panel_simple * p,bool from_probe)520 static int panel_simple_get_hpd_gpio(struct device *dev,
521 struct panel_simple *p, bool from_probe)
522 {
523 int err;
524
525 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
526 if (IS_ERR(p->hpd_gpio)) {
527 err = PTR_ERR(p->hpd_gpio);
528
529 /*
530 * If we're called from probe we won't consider '-EPROBE_DEFER'
531 * to be an error--we'll leave the error code in "hpd_gpio".
532 * When we try to use it we'll try again. This allows for
533 * circular dependencies where the component providing the
534 * hpd gpio needs the panel to init before probing.
535 */
536 if (err != -EPROBE_DEFER || !from_probe) {
537 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
538 return err;
539 }
540 }
541
542 return 0;
543 }
544
panel_simple_prepare(struct drm_panel * panel)545 static int panel_simple_prepare(struct drm_panel *panel)
546 {
547 struct panel_simple *p = to_panel_simple(panel);
548 unsigned int delay;
549 int err;
550 int hpd_asserted;
551
552 if (p->prepared)
553 return 0;
554
555 err = panel_simple_regulator_enable(p);
556 if (err < 0) {
557 dev_err(panel->dev, "failed to enable supply: %d\n", err);
558 return err;
559 }
560
561 gpiod_direction_output(p->enable_gpio, 1);
562
563 delay = p->desc->delay.prepare;
564 if (p->no_hpd)
565 delay += p->desc->delay.hpd_absent_delay;
566 if (delay)
567 msleep(delay);
568
569 if (p->hpd_gpio) {
570 if (IS_ERR(p->hpd_gpio)) {
571 err = panel_simple_get_hpd_gpio(panel->dev, p, false);
572 if (err)
573 return err;
574 }
575
576 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
577 hpd_asserted, hpd_asserted,
578 1000, 2000000);
579 if (hpd_asserted < 0)
580 err = hpd_asserted;
581
582 if (err) {
583 dev_err(panel->dev,
584 "error waiting for hpd GPIO: %d\n", err);
585 return err;
586 }
587 }
588
589 gpiod_direction_output(p->reset_gpio, 1);
590
591 if (p->desc->delay.reset)
592 msleep(p->desc->delay.reset);
593
594 gpiod_direction_output(p->reset_gpio, 0);
595
596 if (p->desc->delay.init)
597 msleep(p->desc->delay.init);
598
599 if (p->desc->init_seq) {
600 if (p->desc->cmd_type == CMD_TYPE_SPI) {
601 if (panel_simple_xfer_spi_cmd_seq(p, p->desc->init_seq)) {
602 dev_err(panel->dev, "failed to send init spi cmds seq\n");
603 return -EINVAL;
604 }
605 } else {
606 if (p->dsi)
607 panel_simple_xfer_dsi_cmd_seq(p, p->desc->init_seq);
608 }
609 }
610
611 p->prepared = true;
612
613 return 0;
614 }
615
panel_simple_enable(struct drm_panel * panel)616 static int panel_simple_enable(struct drm_panel *panel)
617 {
618 struct panel_simple *p = to_panel_simple(panel);
619
620 if (p->enabled)
621 return 0;
622
623 if (p->desc->delay.enable)
624 msleep(p->desc->delay.enable);
625
626 p->enabled = true;
627
628 return 0;
629 }
630
panel_simple_get_modes(struct drm_panel * panel,struct drm_connector * connector)631 static int panel_simple_get_modes(struct drm_panel *panel,
632 struct drm_connector *connector)
633 {
634 struct panel_simple *p = to_panel_simple(panel);
635 int num = 0;
636
637 /* probe EDID if a DDC bus is available */
638 if (p->ddc) {
639 struct edid *edid = drm_get_edid(connector, p->ddc);
640
641 drm_connector_update_edid_property(connector, edid);
642 if (edid) {
643 num += drm_add_edid_modes(connector, edid);
644 kfree(edid);
645 }
646 }
647
648 /* add hard-coded panel modes */
649 num += panel_simple_get_non_edid_modes(p, connector);
650
651 /* set up connector's "panel orientation" property */
652 drm_connector_set_panel_orientation(connector, p->orientation);
653
654 return num;
655 }
656
panel_simple_get_timings(struct drm_panel * panel,unsigned int num_timings,struct display_timing * timings)657 static int panel_simple_get_timings(struct drm_panel *panel,
658 unsigned int num_timings,
659 struct display_timing *timings)
660 {
661 struct panel_simple *p = to_panel_simple(panel);
662 unsigned int i;
663
664 if (p->desc->num_timings < num_timings)
665 num_timings = p->desc->num_timings;
666
667 if (timings)
668 for (i = 0; i < num_timings; i++)
669 timings[i] = p->desc->timings[i];
670
671 return p->desc->num_timings;
672 }
673
674 static const struct drm_panel_funcs panel_simple_funcs = {
675 .disable = panel_simple_disable,
676 .unprepare = panel_simple_unprepare,
677 .prepare = panel_simple_prepare,
678 .enable = panel_simple_enable,
679 .get_modes = panel_simple_get_modes,
680 .get_timings = panel_simple_get_timings,
681 };
682
683 static struct panel_desc panel_dpi;
684
panel_dpi_probe(struct device * dev,struct panel_simple * panel)685 static int panel_dpi_probe(struct device *dev,
686 struct panel_simple *panel)
687 {
688 struct display_timing *timing;
689 const struct device_node *np;
690 struct panel_desc *desc;
691 unsigned int bus_flags;
692 struct videomode vm;
693 int ret;
694
695 np = dev->of_node;
696 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
697 if (!desc)
698 return -ENOMEM;
699
700 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
701 if (!timing)
702 return -ENOMEM;
703
704 ret = of_get_display_timing(np, "panel-timing", timing);
705 if (ret < 0) {
706 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
707 np);
708 return ret;
709 }
710
711 desc->timings = timing;
712 desc->num_timings = 1;
713
714 of_property_read_u32(np, "width-mm", &desc->size.width);
715 of_property_read_u32(np, "height-mm", &desc->size.height);
716
717 /* Extract bus_flags from display_timing */
718 bus_flags = 0;
719 vm.flags = timing->flags;
720 drm_bus_flags_from_videomode(&vm, &bus_flags);
721 desc->bus_flags = bus_flags;
722
723 /* We do not know the connector for the DT node, so guess it */
724 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
725
726 panel->desc = desc;
727
728 return 0;
729 }
730
731 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
732 (to_check->field.typ >= bounds->field.min && \
733 to_check->field.typ <= bounds->field.max)
panel_simple_parse_panel_timing_node(struct device * dev,struct panel_simple * panel,const struct display_timing * ot)734 static void panel_simple_parse_panel_timing_node(struct device *dev,
735 struct panel_simple *panel,
736 const struct display_timing *ot)
737 {
738 const struct panel_desc *desc = panel->desc;
739 struct videomode vm;
740 unsigned int i;
741
742 if (WARN_ON(desc->num_modes)) {
743 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
744 return;
745 }
746 if (WARN_ON(!desc->num_timings)) {
747 dev_err(dev, "Reject override mode: no timings specified\n");
748 return;
749 }
750
751 for (i = 0; i < panel->desc->num_timings; i++) {
752 const struct display_timing *dt = &panel->desc->timings[i];
753
754 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
755 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
756 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
757 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
758 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
759 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
760 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
761 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
762 continue;
763
764 if (ot->flags != dt->flags)
765 continue;
766
767 videomode_from_timing(ot, &vm);
768 drm_display_mode_from_videomode(&vm, &panel->override_mode);
769 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
770 DRM_MODE_TYPE_PREFERRED;
771 break;
772 }
773
774 if (WARN_ON(!panel->override_mode.type))
775 dev_err(dev, "Reject override mode: No display_timing found\n");
776 }
777
dcs_bl_update_status(struct backlight_device * bl)778 static int dcs_bl_update_status(struct backlight_device *bl)
779 {
780 struct panel_simple *p = bl_get_data(bl);
781 struct mipi_dsi_device *dsi = p->dsi;
782 int ret;
783
784 if (!p->prepared)
785 return 0;
786
787 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
788
789 ret = mipi_dsi_dcs_set_display_brightness(dsi, bl->props.brightness);
790 if (ret < 0)
791 return ret;
792
793 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
794
795 return 0;
796 }
797
dcs_bl_get_brightness(struct backlight_device * bl)798 static int dcs_bl_get_brightness(struct backlight_device *bl)
799 {
800 struct panel_simple *p = bl_get_data(bl);
801 struct mipi_dsi_device *dsi = p->dsi;
802 u16 brightness = bl->props.brightness;
803 int ret;
804
805 if (!p->prepared)
806 return 0;
807
808 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
809
810 ret = mipi_dsi_dcs_get_display_brightness(dsi, &brightness);
811 if (ret < 0)
812 return ret;
813
814 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
815
816 return brightness & 0xff;
817 }
818
819 static const struct backlight_ops dcs_bl_ops = {
820 .update_status = dcs_bl_update_status,
821 .get_brightness = dcs_bl_get_brightness,
822 };
823
panel_simple_probe(struct device * dev,const struct panel_desc * desc)824 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
825 {
826 struct panel_simple *panel;
827 struct display_timing dt;
828 struct device_node *ddc;
829 int connector_type;
830 u32 bus_flags;
831 int err;
832
833 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
834 if (!panel)
835 return -ENOMEM;
836
837 panel->enabled = false;
838 panel->prepared = false;
839 panel->desc = desc;
840
841 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
842 if (!panel->no_hpd) {
843 err = panel_simple_get_hpd_gpio(dev, panel, true);
844 if (err)
845 return err;
846 }
847
848 panel->supply = devm_regulator_get(dev, "power");
849 if (IS_ERR(panel->supply)) {
850 err = PTR_ERR(panel->supply);
851 dev_err(dev, "failed to get power regulator: %d\n", err);
852 return err;
853 }
854
855 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_ASIS);
856 if (IS_ERR(panel->enable_gpio)) {
857 err = PTR_ERR(panel->enable_gpio);
858 if (err != -EPROBE_DEFER)
859 dev_err(dev, "failed to get enable GPIO: %d\n", err);
860 return err;
861 }
862
863 panel->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
864 if (IS_ERR(panel->reset_gpio)) {
865 err = PTR_ERR(panel->reset_gpio);
866 if (err != -EPROBE_DEFER)
867 dev_err(dev, "failed to get reset GPIO: %d\n", err);
868 return err;
869 }
870
871 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
872 if (err) {
873 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
874 return err;
875 }
876
877 panel->power_invert = of_property_read_bool(dev->of_node, "power-invert");
878
879 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
880 if (ddc) {
881 panel->ddc = of_find_i2c_adapter_by_node(ddc);
882 of_node_put(ddc);
883
884 if (!panel->ddc) {
885 err = -EPROBE_DEFER;
886 dev_err(dev, "failed to find ddc-i2c-bus: %d\n", err);
887 return err;
888 }
889 }
890
891 if (desc == &panel_dpi) {
892 /* Handle the generic panel-dpi binding */
893 err = panel_dpi_probe(dev, panel);
894 if (err)
895 goto free_ddc;
896 desc = panel->desc;
897 } else {
898 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
899 panel_simple_parse_panel_timing_node(dev, panel, &dt);
900 }
901
902 connector_type = desc->connector_type;
903 /* Catch common mistakes for panels. */
904 switch (connector_type) {
905 case 0:
906 dev_dbg(dev, "Specify missing connector_type\n");
907 connector_type = DRM_MODE_CONNECTOR_DPI;
908 break;
909 case DRM_MODE_CONNECTOR_LVDS:
910 WARN_ON(desc->bus_flags &
911 ~(DRM_BUS_FLAG_DE_LOW |
912 DRM_BUS_FLAG_DE_HIGH |
913 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
914 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
915 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
916 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
917 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
918 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
919 desc->bpc != 6);
920 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
921 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
922 desc->bpc != 8);
923 break;
924 case DRM_MODE_CONNECTOR_eDP:
925 if (desc->bus_format == 0)
926 dev_warn(dev, "Specify missing bus_format\n");
927 if (desc->bpc != 6 && desc->bpc != 8)
928 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
929 break;
930 case DRM_MODE_CONNECTOR_DSI:
931 if (desc->bpc != 6 && desc->bpc != 8)
932 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
933 break;
934 case DRM_MODE_CONNECTOR_DPI:
935 bus_flags = DRM_BUS_FLAG_DE_LOW |
936 DRM_BUS_FLAG_DE_HIGH |
937 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
938 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
939 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
940 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
941 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
942 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
943 if (desc->bus_flags & ~bus_flags)
944 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
945 if (!(desc->bus_flags & bus_flags))
946 dev_warn(dev, "Specify missing bus_flags\n");
947 if (desc->bus_format == 0)
948 dev_warn(dev, "Specify missing bus_format\n");
949 if (desc->bpc != 6 && desc->bpc != 8)
950 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
951 break;
952 default:
953 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
954 connector_type = DRM_MODE_CONNECTOR_DPI;
955 break;
956 }
957
958 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
959
960 err = drm_panel_of_backlight(&panel->base);
961 if (err) {
962 dev_err(dev, "failed to find backlight: %d\n", err);
963 goto free_ddc;
964 }
965
966 drm_panel_add(&panel->base);
967
968 dev_set_drvdata(dev, panel);
969
970 return 0;
971
972 free_ddc:
973 if (panel->ddc)
974 put_device(&panel->ddc->dev);
975
976 return err;
977 }
978
panel_simple_remove(struct device * dev)979 static int panel_simple_remove(struct device *dev)
980 {
981 struct panel_simple *panel = dev_get_drvdata(dev);
982
983 drm_panel_remove(&panel->base);
984 drm_panel_disable(&panel->base);
985 drm_panel_unprepare(&panel->base);
986
987 if (panel->ddc)
988 put_device(&panel->ddc->dev);
989
990 return 0;
991 }
992
panel_simple_shutdown(struct device * dev)993 static void panel_simple_shutdown(struct device *dev)
994 {
995 struct panel_simple *panel = dev_get_drvdata(dev);
996
997 drm_panel_disable(&panel->base);
998 drm_panel_unprepare(&panel->base);
999 }
1000
1001 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
1002 .clock = 71100,
1003 .hdisplay = 1280,
1004 .hsync_start = 1280 + 40,
1005 .hsync_end = 1280 + 40 + 80,
1006 .htotal = 1280 + 40 + 80 + 40,
1007 .vdisplay = 800,
1008 .vsync_start = 800 + 3,
1009 .vsync_end = 800 + 3 + 10,
1010 .vtotal = 800 + 3 + 10 + 10,
1011 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1012 };
1013
1014 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
1015 .modes = &ire_am_1280800n3tzqw_t00h_mode,
1016 .num_modes = 1,
1017 .bpc = 8,
1018 .size = {
1019 .width = 217,
1020 .height = 136,
1021 },
1022 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1023 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1024 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1025 };
1026
1027 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
1028 .clock = 9000,
1029 .hdisplay = 480,
1030 .hsync_start = 480 + 2,
1031 .hsync_end = 480 + 2 + 41,
1032 .htotal = 480 + 2 + 41 + 2,
1033 .vdisplay = 272,
1034 .vsync_start = 272 + 2,
1035 .vsync_end = 272 + 2 + 10,
1036 .vtotal = 272 + 2 + 10 + 2,
1037 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1038 };
1039
1040 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
1041 .modes = &ire_am_480272h3tmqw_t01h_mode,
1042 .num_modes = 1,
1043 .bpc = 8,
1044 .size = {
1045 .width = 105,
1046 .height = 67,
1047 },
1048 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1049 };
1050
1051 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
1052 .clock = 33333,
1053 .hdisplay = 800,
1054 .hsync_start = 800 + 0,
1055 .hsync_end = 800 + 0 + 255,
1056 .htotal = 800 + 0 + 255 + 0,
1057 .vdisplay = 480,
1058 .vsync_start = 480 + 2,
1059 .vsync_end = 480 + 2 + 45,
1060 .vtotal = 480 + 2 + 45 + 0,
1061 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1062 };
1063
1064 static const struct panel_desc ampire_am800480r3tmqwa1h = {
1065 .modes = &ire_am800480r3tmqwa1h_mode,
1066 .num_modes = 1,
1067 .bpc = 6,
1068 .size = {
1069 .width = 152,
1070 .height = 91,
1071 },
1072 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1073 };
1074
1075 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
1076 .pixelclock = { 26400000, 33300000, 46800000 },
1077 .hactive = { 800, 800, 800 },
1078 .hfront_porch = { 16, 210, 354 },
1079 .hback_porch = { 45, 36, 6 },
1080 .hsync_len = { 1, 10, 40 },
1081 .vactive = { 480, 480, 480 },
1082 .vfront_porch = { 7, 22, 147 },
1083 .vback_porch = { 22, 13, 3 },
1084 .vsync_len = { 1, 10, 20 },
1085 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1086 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
1087 };
1088
1089 static const struct panel_desc armadeus_st0700_adapt = {
1090 .timings = &santek_st0700i5y_rbslw_f_timing,
1091 .num_timings = 1,
1092 .bpc = 6,
1093 .size = {
1094 .width = 154,
1095 .height = 86,
1096 },
1097 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1098 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1099 };
1100
1101 static const struct drm_display_mode auo_b101aw03_mode = {
1102 .clock = 51450,
1103 .hdisplay = 1024,
1104 .hsync_start = 1024 + 156,
1105 .hsync_end = 1024 + 156 + 8,
1106 .htotal = 1024 + 156 + 8 + 156,
1107 .vdisplay = 600,
1108 .vsync_start = 600 + 16,
1109 .vsync_end = 600 + 16 + 6,
1110 .vtotal = 600 + 16 + 6 + 16,
1111 };
1112
1113 static const struct panel_desc auo_b101aw03 = {
1114 .modes = &auo_b101aw03_mode,
1115 .num_modes = 1,
1116 .bpc = 6,
1117 .size = {
1118 .width = 223,
1119 .height = 125,
1120 },
1121 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1122 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1123 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1124 };
1125
1126 static const struct display_timing auo_b101ean01_timing = {
1127 .pixelclock = { 65300000, 72500000, 75000000 },
1128 .hactive = { 1280, 1280, 1280 },
1129 .hfront_porch = { 18, 119, 119 },
1130 .hback_porch = { 21, 21, 21 },
1131 .hsync_len = { 32, 32, 32 },
1132 .vactive = { 800, 800, 800 },
1133 .vfront_porch = { 4, 4, 4 },
1134 .vback_porch = { 8, 8, 8 },
1135 .vsync_len = { 18, 20, 20 },
1136 };
1137
1138 static const struct panel_desc auo_b101ean01 = {
1139 .timings = &auo_b101ean01_timing,
1140 .num_timings = 1,
1141 .bpc = 6,
1142 .size = {
1143 .width = 217,
1144 .height = 136,
1145 },
1146 };
1147
1148 static const struct drm_display_mode auo_b101xtn01_mode = {
1149 .clock = 72000,
1150 .hdisplay = 1366,
1151 .hsync_start = 1366 + 20,
1152 .hsync_end = 1366 + 20 + 70,
1153 .htotal = 1366 + 20 + 70,
1154 .vdisplay = 768,
1155 .vsync_start = 768 + 14,
1156 .vsync_end = 768 + 14 + 42,
1157 .vtotal = 768 + 14 + 42,
1158 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1159 };
1160
1161 static const struct panel_desc auo_b101xtn01 = {
1162 .modes = &auo_b101xtn01_mode,
1163 .num_modes = 1,
1164 .bpc = 6,
1165 .size = {
1166 .width = 223,
1167 .height = 125,
1168 },
1169 };
1170
1171 static const struct drm_display_mode auo_b116xak01_mode = {
1172 .clock = 69300,
1173 .hdisplay = 1366,
1174 .hsync_start = 1366 + 48,
1175 .hsync_end = 1366 + 48 + 32,
1176 .htotal = 1366 + 48 + 32 + 10,
1177 .vdisplay = 768,
1178 .vsync_start = 768 + 4,
1179 .vsync_end = 768 + 4 + 6,
1180 .vtotal = 768 + 4 + 6 + 15,
1181 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1182 };
1183
1184 static const struct panel_desc auo_b116xak01 = {
1185 .modes = &auo_b116xak01_mode,
1186 .num_modes = 1,
1187 .bpc = 6,
1188 .size = {
1189 .width = 256,
1190 .height = 144,
1191 },
1192 .delay = {
1193 .hpd_absent_delay = 200,
1194 },
1195 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1196 .connector_type = DRM_MODE_CONNECTOR_eDP,
1197 };
1198
1199 static const struct drm_display_mode auo_b116xw03_mode = {
1200 .clock = 70589,
1201 .hdisplay = 1366,
1202 .hsync_start = 1366 + 40,
1203 .hsync_end = 1366 + 40 + 40,
1204 .htotal = 1366 + 40 + 40 + 32,
1205 .vdisplay = 768,
1206 .vsync_start = 768 + 10,
1207 .vsync_end = 768 + 10 + 12,
1208 .vtotal = 768 + 10 + 12 + 6,
1209 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1210 };
1211
1212 static const struct panel_desc auo_b116xw03 = {
1213 .modes = &auo_b116xw03_mode,
1214 .num_modes = 1,
1215 .bpc = 6,
1216 .size = {
1217 .width = 256,
1218 .height = 144,
1219 },
1220 .delay = {
1221 .enable = 400,
1222 },
1223 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
1224 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1225 .connector_type = DRM_MODE_CONNECTOR_eDP,
1226 };
1227
1228 static const struct drm_display_mode auo_b133xtn01_mode = {
1229 .clock = 69500,
1230 .hdisplay = 1366,
1231 .hsync_start = 1366 + 48,
1232 .hsync_end = 1366 + 48 + 32,
1233 .htotal = 1366 + 48 + 32 + 20,
1234 .vdisplay = 768,
1235 .vsync_start = 768 + 3,
1236 .vsync_end = 768 + 3 + 6,
1237 .vtotal = 768 + 3 + 6 + 13,
1238 };
1239
1240 static const struct panel_desc auo_b133xtn01 = {
1241 .modes = &auo_b133xtn01_mode,
1242 .num_modes = 1,
1243 .bpc = 6,
1244 .size = {
1245 .width = 293,
1246 .height = 165,
1247 },
1248 };
1249
1250 static const struct drm_display_mode auo_b133htn01_mode = {
1251 .clock = 150660,
1252 .hdisplay = 1920,
1253 .hsync_start = 1920 + 172,
1254 .hsync_end = 1920 + 172 + 80,
1255 .htotal = 1920 + 172 + 80 + 60,
1256 .vdisplay = 1080,
1257 .vsync_start = 1080 + 25,
1258 .vsync_end = 1080 + 25 + 10,
1259 .vtotal = 1080 + 25 + 10 + 10,
1260 };
1261
1262 static const struct panel_desc auo_b133htn01 = {
1263 .modes = &auo_b133htn01_mode,
1264 .num_modes = 1,
1265 .bpc = 6,
1266 .size = {
1267 .width = 293,
1268 .height = 165,
1269 },
1270 .delay = {
1271 .prepare = 105,
1272 .enable = 20,
1273 .unprepare = 50,
1274 },
1275 };
1276
1277 static const struct display_timing auo_g070vvn01_timings = {
1278 .pixelclock = { 33300000, 34209000, 45000000 },
1279 .hactive = { 800, 800, 800 },
1280 .hfront_porch = { 20, 40, 200 },
1281 .hback_porch = { 87, 40, 1 },
1282 .hsync_len = { 1, 48, 87 },
1283 .vactive = { 480, 480, 480 },
1284 .vfront_porch = { 5, 13, 200 },
1285 .vback_porch = { 31, 31, 29 },
1286 .vsync_len = { 1, 1, 3 },
1287 };
1288
1289 static const struct panel_desc auo_g070vvn01 = {
1290 .timings = &auo_g070vvn01_timings,
1291 .num_timings = 1,
1292 .bpc = 8,
1293 .size = {
1294 .width = 152,
1295 .height = 91,
1296 },
1297 .delay = {
1298 .prepare = 200,
1299 .enable = 50,
1300 .disable = 50,
1301 .unprepare = 1000,
1302 },
1303 };
1304
1305 static const struct drm_display_mode auo_g101evn010_mode = {
1306 .clock = 68930,
1307 .hdisplay = 1280,
1308 .hsync_start = 1280 + 82,
1309 .hsync_end = 1280 + 82 + 2,
1310 .htotal = 1280 + 82 + 2 + 84,
1311 .vdisplay = 800,
1312 .vsync_start = 800 + 8,
1313 .vsync_end = 800 + 8 + 2,
1314 .vtotal = 800 + 8 + 2 + 6,
1315 };
1316
1317 static const struct panel_desc auo_g101evn010 = {
1318 .modes = &auo_g101evn010_mode,
1319 .num_modes = 1,
1320 .bpc = 6,
1321 .size = {
1322 .width = 216,
1323 .height = 135,
1324 },
1325 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1326 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1327 };
1328
1329 static const struct drm_display_mode auo_g104sn02_mode = {
1330 .clock = 40000,
1331 .hdisplay = 800,
1332 .hsync_start = 800 + 40,
1333 .hsync_end = 800 + 40 + 216,
1334 .htotal = 800 + 40 + 216 + 128,
1335 .vdisplay = 600,
1336 .vsync_start = 600 + 10,
1337 .vsync_end = 600 + 10 + 35,
1338 .vtotal = 600 + 10 + 35 + 2,
1339 };
1340
1341 static const struct panel_desc auo_g104sn02 = {
1342 .modes = &auo_g104sn02_mode,
1343 .num_modes = 1,
1344 .bpc = 8,
1345 .size = {
1346 .width = 211,
1347 .height = 158,
1348 },
1349 };
1350
1351 static const struct drm_display_mode auo_g121ean01_mode = {
1352 .clock = 66700,
1353 .hdisplay = 1280,
1354 .hsync_start = 1280 + 58,
1355 .hsync_end = 1280 + 58 + 8,
1356 .htotal = 1280 + 58 + 8 + 70,
1357 .vdisplay = 800,
1358 .vsync_start = 800 + 6,
1359 .vsync_end = 800 + 6 + 4,
1360 .vtotal = 800 + 6 + 4 + 10,
1361 };
1362
1363 static const struct panel_desc auo_g121ean01 = {
1364 .modes = &auo_g121ean01_mode,
1365 .num_modes = 1,
1366 .bpc = 8,
1367 .size = {
1368 .width = 261,
1369 .height = 163,
1370 },
1371 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1372 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1373 };
1374
1375 static const struct display_timing auo_g133han01_timings = {
1376 .pixelclock = { 134000000, 141200000, 149000000 },
1377 .hactive = { 1920, 1920, 1920 },
1378 .hfront_porch = { 39, 58, 77 },
1379 .hback_porch = { 59, 88, 117 },
1380 .hsync_len = { 28, 42, 56 },
1381 .vactive = { 1080, 1080, 1080 },
1382 .vfront_porch = { 3, 8, 11 },
1383 .vback_porch = { 5, 14, 19 },
1384 .vsync_len = { 4, 14, 19 },
1385 };
1386
1387 static const struct panel_desc auo_g133han01 = {
1388 .timings = &auo_g133han01_timings,
1389 .num_timings = 1,
1390 .bpc = 8,
1391 .size = {
1392 .width = 293,
1393 .height = 165,
1394 },
1395 .delay = {
1396 .prepare = 200,
1397 .enable = 50,
1398 .disable = 50,
1399 .unprepare = 1000,
1400 },
1401 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1402 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1403 };
1404
1405 static const struct drm_display_mode auo_g156xtn01_mode = {
1406 .clock = 76000,
1407 .hdisplay = 1366,
1408 .hsync_start = 1366 + 33,
1409 .hsync_end = 1366 + 33 + 67,
1410 .htotal = 1560,
1411 .vdisplay = 768,
1412 .vsync_start = 768 + 4,
1413 .vsync_end = 768 + 4 + 4,
1414 .vtotal = 806,
1415 };
1416
1417 static const struct panel_desc auo_g156xtn01 = {
1418 .modes = &auo_g156xtn01_mode,
1419 .num_modes = 1,
1420 .bpc = 8,
1421 .size = {
1422 .width = 344,
1423 .height = 194,
1424 },
1425 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1426 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1427 };
1428
1429 static const struct display_timing auo_g185han01_timings = {
1430 .pixelclock = { 120000000, 144000000, 175000000 },
1431 .hactive = { 1920, 1920, 1920 },
1432 .hfront_porch = { 36, 120, 148 },
1433 .hback_porch = { 24, 88, 108 },
1434 .hsync_len = { 20, 48, 64 },
1435 .vactive = { 1080, 1080, 1080 },
1436 .vfront_porch = { 6, 10, 40 },
1437 .vback_porch = { 2, 5, 20 },
1438 .vsync_len = { 2, 5, 20 },
1439 };
1440
1441 static const struct panel_desc auo_g185han01 = {
1442 .timings = &auo_g185han01_timings,
1443 .num_timings = 1,
1444 .bpc = 8,
1445 .size = {
1446 .width = 409,
1447 .height = 230,
1448 },
1449 .delay = {
1450 .prepare = 50,
1451 .enable = 200,
1452 .disable = 110,
1453 .unprepare = 1000,
1454 },
1455 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1456 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1457 };
1458
1459 static const struct display_timing auo_g190ean01_timings = {
1460 .pixelclock = { 90000000, 108000000, 135000000 },
1461 .hactive = { 1280, 1280, 1280 },
1462 .hfront_porch = { 126, 184, 1266 },
1463 .hback_porch = { 84, 122, 844 },
1464 .hsync_len = { 70, 102, 704 },
1465 .vactive = { 1024, 1024, 1024 },
1466 .vfront_porch = { 4, 26, 76 },
1467 .vback_porch = { 2, 8, 25 },
1468 .vsync_len = { 2, 8, 25 },
1469 };
1470
1471 static const struct panel_desc auo_g190ean01 = {
1472 .timings = &auo_g190ean01_timings,
1473 .num_timings = 1,
1474 .bpc = 8,
1475 .size = {
1476 .width = 376,
1477 .height = 301,
1478 },
1479 .delay = {
1480 .prepare = 50,
1481 .enable = 200,
1482 .disable = 110,
1483 .unprepare = 1000,
1484 },
1485 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1486 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1487 };
1488
1489 static const struct display_timing auo_p320hvn03_timings = {
1490 .pixelclock = { 106000000, 148500000, 164000000 },
1491 .hactive = { 1920, 1920, 1920 },
1492 .hfront_porch = { 25, 50, 130 },
1493 .hback_porch = { 25, 50, 130 },
1494 .hsync_len = { 20, 40, 105 },
1495 .vactive = { 1080, 1080, 1080 },
1496 .vfront_porch = { 8, 17, 150 },
1497 .vback_porch = { 8, 17, 150 },
1498 .vsync_len = { 4, 11, 100 },
1499 };
1500
1501 static const struct panel_desc auo_p320hvn03 = {
1502 .timings = &auo_p320hvn03_timings,
1503 .num_timings = 1,
1504 .bpc = 8,
1505 .size = {
1506 .width = 698,
1507 .height = 393,
1508 },
1509 .delay = {
1510 .prepare = 1,
1511 .enable = 450,
1512 .unprepare = 500,
1513 },
1514 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1515 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1516 };
1517
1518 static const struct drm_display_mode auo_t215hvn01_mode = {
1519 .clock = 148800,
1520 .hdisplay = 1920,
1521 .hsync_start = 1920 + 88,
1522 .hsync_end = 1920 + 88 + 44,
1523 .htotal = 1920 + 88 + 44 + 148,
1524 .vdisplay = 1080,
1525 .vsync_start = 1080 + 4,
1526 .vsync_end = 1080 + 4 + 5,
1527 .vtotal = 1080 + 4 + 5 + 36,
1528 };
1529
1530 static const struct panel_desc auo_t215hvn01 = {
1531 .modes = &auo_t215hvn01_mode,
1532 .num_modes = 1,
1533 .bpc = 8,
1534 .size = {
1535 .width = 430,
1536 .height = 270,
1537 },
1538 .delay = {
1539 .disable = 5,
1540 .unprepare = 1000,
1541 }
1542 };
1543
1544 static const struct drm_display_mode avic_tm070ddh03_mode = {
1545 .clock = 51200,
1546 .hdisplay = 1024,
1547 .hsync_start = 1024 + 160,
1548 .hsync_end = 1024 + 160 + 4,
1549 .htotal = 1024 + 160 + 4 + 156,
1550 .vdisplay = 600,
1551 .vsync_start = 600 + 17,
1552 .vsync_end = 600 + 17 + 1,
1553 .vtotal = 600 + 17 + 1 + 17,
1554 };
1555
1556 static const struct panel_desc avic_tm070ddh03 = {
1557 .modes = &avic_tm070ddh03_mode,
1558 .num_modes = 1,
1559 .bpc = 8,
1560 .size = {
1561 .width = 154,
1562 .height = 90,
1563 },
1564 .delay = {
1565 .prepare = 20,
1566 .enable = 200,
1567 .disable = 200,
1568 },
1569 };
1570
1571 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1572 .clock = 30000,
1573 .hdisplay = 800,
1574 .hsync_start = 800 + 40,
1575 .hsync_end = 800 + 40 + 48,
1576 .htotal = 800 + 40 + 48 + 40,
1577 .vdisplay = 480,
1578 .vsync_start = 480 + 13,
1579 .vsync_end = 480 + 13 + 3,
1580 .vtotal = 480 + 13 + 3 + 29,
1581 };
1582
1583 static const struct panel_desc bananapi_s070wv20_ct16 = {
1584 .modes = &bananapi_s070wv20_ct16_mode,
1585 .num_modes = 1,
1586 .bpc = 6,
1587 .size = {
1588 .width = 154,
1589 .height = 86,
1590 },
1591 };
1592
1593 static const struct drm_display_mode boe_hv070wsa_mode = {
1594 .clock = 42105,
1595 .hdisplay = 1024,
1596 .hsync_start = 1024 + 30,
1597 .hsync_end = 1024 + 30 + 30,
1598 .htotal = 1024 + 30 + 30 + 30,
1599 .vdisplay = 600,
1600 .vsync_start = 600 + 10,
1601 .vsync_end = 600 + 10 + 10,
1602 .vtotal = 600 + 10 + 10 + 10,
1603 };
1604
1605 static const struct panel_desc boe_hv070wsa = {
1606 .modes = &boe_hv070wsa_mode,
1607 .num_modes = 1,
1608 .bpc = 8,
1609 .size = {
1610 .width = 154,
1611 .height = 90,
1612 },
1613 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1614 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1615 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1616 };
1617
1618 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1619 {
1620 .clock = 71900,
1621 .hdisplay = 1280,
1622 .hsync_start = 1280 + 48,
1623 .hsync_end = 1280 + 48 + 32,
1624 .htotal = 1280 + 48 + 32 + 80,
1625 .vdisplay = 800,
1626 .vsync_start = 800 + 3,
1627 .vsync_end = 800 + 3 + 5,
1628 .vtotal = 800 + 3 + 5 + 24,
1629 },
1630 {
1631 .clock = 57500,
1632 .hdisplay = 1280,
1633 .hsync_start = 1280 + 48,
1634 .hsync_end = 1280 + 48 + 32,
1635 .htotal = 1280 + 48 + 32 + 80,
1636 .vdisplay = 800,
1637 .vsync_start = 800 + 3,
1638 .vsync_end = 800 + 3 + 5,
1639 .vtotal = 800 + 3 + 5 + 24,
1640 },
1641 };
1642
1643 static const struct panel_desc boe_nv101wxmn51 = {
1644 .modes = boe_nv101wxmn51_modes,
1645 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1646 .bpc = 8,
1647 .size = {
1648 .width = 217,
1649 .height = 136,
1650 },
1651 .delay = {
1652 .prepare = 210,
1653 .enable = 50,
1654 .unprepare = 160,
1655 },
1656 };
1657
1658 /* Also used for boe_nv133fhm_n62 */
1659 static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1660 .clock = 147840,
1661 .hdisplay = 1920,
1662 .hsync_start = 1920 + 48,
1663 .hsync_end = 1920 + 48 + 32,
1664 .htotal = 1920 + 48 + 32 + 200,
1665 .vdisplay = 1080,
1666 .vsync_start = 1080 + 3,
1667 .vsync_end = 1080 + 3 + 6,
1668 .vtotal = 1080 + 3 + 6 + 31,
1669 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1670 };
1671
1672 /* Also used for boe_nv133fhm_n62 */
1673 static const struct panel_desc boe_nv133fhm_n61 = {
1674 .modes = &boe_nv133fhm_n61_modes,
1675 .num_modes = 1,
1676 .bpc = 6,
1677 .size = {
1678 .width = 294,
1679 .height = 165,
1680 },
1681 .delay = {
1682 /*
1683 * When power is first given to the panel there's a short
1684 * spike on the HPD line. It was explained that this spike
1685 * was until the TCON data download was complete. On
1686 * one system this was measured at 8 ms. We'll put 15 ms
1687 * in the prepare delay just to be safe and take it away
1688 * from the hpd_absent_delay (which would otherwise be 200 ms)
1689 * to handle this. That means:
1690 * - If HPD isn't hooked up you still have 200 ms delay.
1691 * - If HPD is hooked up we won't try to look at it for the
1692 * first 15 ms.
1693 */
1694 .prepare = 15,
1695 .hpd_absent_delay = 185,
1696
1697 .unprepare = 500,
1698 },
1699 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1700 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1701 .connector_type = DRM_MODE_CONNECTOR_eDP,
1702 };
1703
1704 static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1705 {
1706 .clock = 148500,
1707 .hdisplay = 1920,
1708 .hsync_start = 1920 + 48,
1709 .hsync_end = 1920 + 48 + 32,
1710 .htotal = 2200,
1711 .vdisplay = 1080,
1712 .vsync_start = 1080 + 3,
1713 .vsync_end = 1080 + 3 + 5,
1714 .vtotal = 1125,
1715 },
1716 };
1717
1718 static const struct panel_desc boe_nv140fhmn49 = {
1719 .modes = boe_nv140fhmn49_modes,
1720 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1721 .bpc = 6,
1722 .size = {
1723 .width = 309,
1724 .height = 174,
1725 },
1726 .delay = {
1727 .prepare = 210,
1728 .enable = 50,
1729 .unprepare = 160,
1730 },
1731 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1732 .connector_type = DRM_MODE_CONNECTOR_eDP,
1733 };
1734
1735 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1736 .clock = 9000,
1737 .hdisplay = 480,
1738 .hsync_start = 480 + 5,
1739 .hsync_end = 480 + 5 + 5,
1740 .htotal = 480 + 5 + 5 + 40,
1741 .vdisplay = 272,
1742 .vsync_start = 272 + 8,
1743 .vsync_end = 272 + 8 + 8,
1744 .vtotal = 272 + 8 + 8 + 8,
1745 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1746 };
1747
1748 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1749 .modes = &cdtech_s043wq26h_ct7_mode,
1750 .num_modes = 1,
1751 .bpc = 8,
1752 .size = {
1753 .width = 95,
1754 .height = 54,
1755 },
1756 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1757 };
1758
1759 /* S070PWS19HP-FC21 2017/04/22 */
1760 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1761 .clock = 51200,
1762 .hdisplay = 1024,
1763 .hsync_start = 1024 + 160,
1764 .hsync_end = 1024 + 160 + 20,
1765 .htotal = 1024 + 160 + 20 + 140,
1766 .vdisplay = 600,
1767 .vsync_start = 600 + 12,
1768 .vsync_end = 600 + 12 + 3,
1769 .vtotal = 600 + 12 + 3 + 20,
1770 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1771 };
1772
1773 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1774 .modes = &cdtech_s070pws19hp_fc21_mode,
1775 .num_modes = 1,
1776 .bpc = 6,
1777 .size = {
1778 .width = 154,
1779 .height = 86,
1780 },
1781 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1782 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1783 .connector_type = DRM_MODE_CONNECTOR_DPI,
1784 };
1785
1786 /* S070SWV29HG-DC44 2017/09/21 */
1787 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1788 .clock = 33300,
1789 .hdisplay = 800,
1790 .hsync_start = 800 + 210,
1791 .hsync_end = 800 + 210 + 2,
1792 .htotal = 800 + 210 + 2 + 44,
1793 .vdisplay = 480,
1794 .vsync_start = 480 + 22,
1795 .vsync_end = 480 + 22 + 2,
1796 .vtotal = 480 + 22 + 2 + 21,
1797 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1798 };
1799
1800 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1801 .modes = &cdtech_s070swv29hg_dc44_mode,
1802 .num_modes = 1,
1803 .bpc = 6,
1804 .size = {
1805 .width = 154,
1806 .height = 86,
1807 },
1808 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1809 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1810 .connector_type = DRM_MODE_CONNECTOR_DPI,
1811 };
1812
1813 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1814 .clock = 35000,
1815 .hdisplay = 800,
1816 .hsync_start = 800 + 40,
1817 .hsync_end = 800 + 40 + 40,
1818 .htotal = 800 + 40 + 40 + 48,
1819 .vdisplay = 480,
1820 .vsync_start = 480 + 29,
1821 .vsync_end = 480 + 29 + 13,
1822 .vtotal = 480 + 29 + 13 + 3,
1823 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1824 };
1825
1826 static const struct panel_desc cdtech_s070wv95_ct16 = {
1827 .modes = &cdtech_s070wv95_ct16_mode,
1828 .num_modes = 1,
1829 .bpc = 8,
1830 .size = {
1831 .width = 154,
1832 .height = 85,
1833 },
1834 };
1835
1836 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1837 .pixelclock = { 68900000, 71100000, 73400000 },
1838 .hactive = { 1280, 1280, 1280 },
1839 .hfront_porch = { 65, 80, 95 },
1840 .hback_porch = { 64, 79, 94 },
1841 .hsync_len = { 1, 1, 1 },
1842 .vactive = { 800, 800, 800 },
1843 .vfront_porch = { 7, 11, 14 },
1844 .vback_porch = { 7, 11, 14 },
1845 .vsync_len = { 1, 1, 1 },
1846 .flags = DISPLAY_FLAGS_DE_HIGH,
1847 };
1848
1849 static const struct panel_desc chefree_ch101olhlwh_002 = {
1850 .timings = &chefree_ch101olhlwh_002_timing,
1851 .num_timings = 1,
1852 .bpc = 8,
1853 .size = {
1854 .width = 217,
1855 .height = 135,
1856 },
1857 .delay = {
1858 .enable = 200,
1859 .disable = 200,
1860 },
1861 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1862 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1863 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1864 };
1865
1866 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1867 .clock = 66770,
1868 .hdisplay = 800,
1869 .hsync_start = 800 + 49,
1870 .hsync_end = 800 + 49 + 33,
1871 .htotal = 800 + 49 + 33 + 17,
1872 .vdisplay = 1280,
1873 .vsync_start = 1280 + 1,
1874 .vsync_end = 1280 + 1 + 7,
1875 .vtotal = 1280 + 1 + 7 + 15,
1876 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1877 };
1878
1879 static const struct panel_desc chunghwa_claa070wp03xg = {
1880 .modes = &chunghwa_claa070wp03xg_mode,
1881 .num_modes = 1,
1882 .bpc = 6,
1883 .size = {
1884 .width = 94,
1885 .height = 150,
1886 },
1887 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1888 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1889 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1890 };
1891
1892 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1893 .clock = 72070,
1894 .hdisplay = 1366,
1895 .hsync_start = 1366 + 58,
1896 .hsync_end = 1366 + 58 + 58,
1897 .htotal = 1366 + 58 + 58 + 58,
1898 .vdisplay = 768,
1899 .vsync_start = 768 + 4,
1900 .vsync_end = 768 + 4 + 4,
1901 .vtotal = 768 + 4 + 4 + 4,
1902 };
1903
1904 static const struct panel_desc chunghwa_claa101wa01a = {
1905 .modes = &chunghwa_claa101wa01a_mode,
1906 .num_modes = 1,
1907 .bpc = 6,
1908 .size = {
1909 .width = 220,
1910 .height = 120,
1911 },
1912 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1913 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1914 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1915 };
1916
1917 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1918 .clock = 69300,
1919 .hdisplay = 1366,
1920 .hsync_start = 1366 + 48,
1921 .hsync_end = 1366 + 48 + 32,
1922 .htotal = 1366 + 48 + 32 + 20,
1923 .vdisplay = 768,
1924 .vsync_start = 768 + 16,
1925 .vsync_end = 768 + 16 + 8,
1926 .vtotal = 768 + 16 + 8 + 16,
1927 };
1928
1929 static const struct panel_desc chunghwa_claa101wb01 = {
1930 .modes = &chunghwa_claa101wb01_mode,
1931 .num_modes = 1,
1932 .bpc = 6,
1933 .size = {
1934 .width = 223,
1935 .height = 125,
1936 },
1937 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1938 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1939 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1940 };
1941
1942 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1943 .clock = 33260,
1944 .hdisplay = 800,
1945 .hsync_start = 800 + 40,
1946 .hsync_end = 800 + 40 + 128,
1947 .htotal = 800 + 40 + 128 + 88,
1948 .vdisplay = 480,
1949 .vsync_start = 480 + 10,
1950 .vsync_end = 480 + 10 + 2,
1951 .vtotal = 480 + 10 + 2 + 33,
1952 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1953 };
1954
1955 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1956 .modes = &dataimage_scf0700c48ggu18_mode,
1957 .num_modes = 1,
1958 .bpc = 8,
1959 .size = {
1960 .width = 152,
1961 .height = 91,
1962 },
1963 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1964 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1965 };
1966
1967 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1968 .pixelclock = { 45000000, 51200000, 57000000 },
1969 .hactive = { 1024, 1024, 1024 },
1970 .hfront_porch = { 100, 106, 113 },
1971 .hback_porch = { 100, 106, 113 },
1972 .hsync_len = { 100, 108, 114 },
1973 .vactive = { 600, 600, 600 },
1974 .vfront_porch = { 8, 11, 15 },
1975 .vback_porch = { 8, 11, 15 },
1976 .vsync_len = { 9, 13, 15 },
1977 .flags = DISPLAY_FLAGS_DE_HIGH,
1978 };
1979
1980 static const struct panel_desc dlc_dlc0700yzg_1 = {
1981 .timings = &dlc_dlc0700yzg_1_timing,
1982 .num_timings = 1,
1983 .bpc = 6,
1984 .size = {
1985 .width = 154,
1986 .height = 86,
1987 },
1988 .delay = {
1989 .prepare = 30,
1990 .enable = 200,
1991 .disable = 200,
1992 },
1993 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1994 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1995 };
1996
1997 static const struct display_timing dlc_dlc1010gig_timing = {
1998 .pixelclock = { 68900000, 71100000, 73400000 },
1999 .hactive = { 1280, 1280, 1280 },
2000 .hfront_porch = { 43, 53, 63 },
2001 .hback_porch = { 43, 53, 63 },
2002 .hsync_len = { 44, 54, 64 },
2003 .vactive = { 800, 800, 800 },
2004 .vfront_porch = { 5, 8, 11 },
2005 .vback_porch = { 5, 8, 11 },
2006 .vsync_len = { 5, 7, 11 },
2007 .flags = DISPLAY_FLAGS_DE_HIGH,
2008 };
2009
2010 static const struct panel_desc dlc_dlc1010gig = {
2011 .timings = &dlc_dlc1010gig_timing,
2012 .num_timings = 1,
2013 .bpc = 8,
2014 .size = {
2015 .width = 216,
2016 .height = 135,
2017 },
2018 .delay = {
2019 .prepare = 60,
2020 .enable = 150,
2021 .disable = 100,
2022 .unprepare = 60,
2023 },
2024 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2025 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2026 };
2027
2028 static const struct drm_display_mode edt_et035012dm6_mode = {
2029 .clock = 6500,
2030 .hdisplay = 320,
2031 .hsync_start = 320 + 20,
2032 .hsync_end = 320 + 20 + 30,
2033 .htotal = 320 + 20 + 68,
2034 .vdisplay = 240,
2035 .vsync_start = 240 + 4,
2036 .vsync_end = 240 + 4 + 4,
2037 .vtotal = 240 + 4 + 4 + 14,
2038 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2039 };
2040
2041 static const struct panel_desc edt_et035012dm6 = {
2042 .modes = &edt_et035012dm6_mode,
2043 .num_modes = 1,
2044 .bpc = 8,
2045 .size = {
2046 .width = 70,
2047 .height = 52,
2048 },
2049 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2050 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2051 };
2052
2053 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
2054 .clock = 10870,
2055 .hdisplay = 480,
2056 .hsync_start = 480 + 8,
2057 .hsync_end = 480 + 8 + 4,
2058 .htotal = 480 + 8 + 4 + 41,
2059
2060 /*
2061 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
2062 * fb_align
2063 */
2064
2065 .vdisplay = 288,
2066 .vsync_start = 288 + 2,
2067 .vsync_end = 288 + 2 + 4,
2068 .vtotal = 288 + 2 + 4 + 10,
2069 };
2070
2071 static const struct panel_desc edt_etm043080dh6gp = {
2072 .modes = &edt_etm043080dh6gp_mode,
2073 .num_modes = 1,
2074 .bpc = 8,
2075 .size = {
2076 .width = 100,
2077 .height = 65,
2078 },
2079 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2080 .connector_type = DRM_MODE_CONNECTOR_DPI,
2081 };
2082
2083 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
2084 .clock = 9000,
2085 .hdisplay = 480,
2086 .hsync_start = 480 + 2,
2087 .hsync_end = 480 + 2 + 41,
2088 .htotal = 480 + 2 + 41 + 2,
2089 .vdisplay = 272,
2090 .vsync_start = 272 + 2,
2091 .vsync_end = 272 + 2 + 10,
2092 .vtotal = 272 + 2 + 10 + 2,
2093 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2094 };
2095
2096 static const struct panel_desc edt_etm0430g0dh6 = {
2097 .modes = &edt_etm0430g0dh6_mode,
2098 .num_modes = 1,
2099 .bpc = 6,
2100 .size = {
2101 .width = 95,
2102 .height = 54,
2103 },
2104 };
2105
2106 static const struct drm_display_mode edt_et057090dhu_mode = {
2107 .clock = 25175,
2108 .hdisplay = 640,
2109 .hsync_start = 640 + 16,
2110 .hsync_end = 640 + 16 + 30,
2111 .htotal = 640 + 16 + 30 + 114,
2112 .vdisplay = 480,
2113 .vsync_start = 480 + 10,
2114 .vsync_end = 480 + 10 + 3,
2115 .vtotal = 480 + 10 + 3 + 32,
2116 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2117 };
2118
2119 static const struct panel_desc edt_et057090dhu = {
2120 .modes = &edt_et057090dhu_mode,
2121 .num_modes = 1,
2122 .bpc = 6,
2123 .size = {
2124 .width = 115,
2125 .height = 86,
2126 },
2127 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2128 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2129 .connector_type = DRM_MODE_CONNECTOR_DPI,
2130 };
2131
2132 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
2133 .clock = 33260,
2134 .hdisplay = 800,
2135 .hsync_start = 800 + 40,
2136 .hsync_end = 800 + 40 + 128,
2137 .htotal = 800 + 40 + 128 + 88,
2138 .vdisplay = 480,
2139 .vsync_start = 480 + 10,
2140 .vsync_end = 480 + 10 + 2,
2141 .vtotal = 480 + 10 + 2 + 33,
2142 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2143 };
2144
2145 static const struct panel_desc edt_etm0700g0dh6 = {
2146 .modes = &edt_etm0700g0dh6_mode,
2147 .num_modes = 1,
2148 .bpc = 6,
2149 .size = {
2150 .width = 152,
2151 .height = 91,
2152 },
2153 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2154 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2155 };
2156
2157 static const struct panel_desc edt_etm0700g0bdh6 = {
2158 .modes = &edt_etm0700g0dh6_mode,
2159 .num_modes = 1,
2160 .bpc = 6,
2161 .size = {
2162 .width = 152,
2163 .height = 91,
2164 },
2165 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2166 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2167 };
2168
2169 static const struct display_timing evervision_vgg804821_timing = {
2170 .pixelclock = { 27600000, 33300000, 50000000 },
2171 .hactive = { 800, 800, 800 },
2172 .hfront_porch = { 40, 66, 70 },
2173 .hback_porch = { 40, 67, 70 },
2174 .hsync_len = { 40, 67, 70 },
2175 .vactive = { 480, 480, 480 },
2176 .vfront_porch = { 6, 10, 10 },
2177 .vback_porch = { 7, 11, 11 },
2178 .vsync_len = { 7, 11, 11 },
2179 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
2180 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2181 DISPLAY_FLAGS_SYNC_NEGEDGE,
2182 };
2183
2184 static const struct panel_desc evervision_vgg804821 = {
2185 .timings = &evervision_vgg804821_timing,
2186 .num_timings = 1,
2187 .bpc = 8,
2188 .size = {
2189 .width = 108,
2190 .height = 64,
2191 },
2192 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2193 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2194 };
2195
2196 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
2197 .clock = 32260,
2198 .hdisplay = 800,
2199 .hsync_start = 800 + 168,
2200 .hsync_end = 800 + 168 + 64,
2201 .htotal = 800 + 168 + 64 + 88,
2202 .vdisplay = 480,
2203 .vsync_start = 480 + 37,
2204 .vsync_end = 480 + 37 + 2,
2205 .vtotal = 480 + 37 + 2 + 8,
2206 };
2207
2208 static const struct panel_desc foxlink_fl500wvr00_a0t = {
2209 .modes = &foxlink_fl500wvr00_a0t_mode,
2210 .num_modes = 1,
2211 .bpc = 8,
2212 .size = {
2213 .width = 108,
2214 .height = 65,
2215 },
2216 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2217 };
2218
2219 static const struct drm_display_mode frida_frd350h54004_modes[] = {
2220 { /* 60 Hz */
2221 .clock = 6000,
2222 .hdisplay = 320,
2223 .hsync_start = 320 + 44,
2224 .hsync_end = 320 + 44 + 16,
2225 .htotal = 320 + 44 + 16 + 20,
2226 .vdisplay = 240,
2227 .vsync_start = 240 + 2,
2228 .vsync_end = 240 + 2 + 6,
2229 .vtotal = 240 + 2 + 6 + 2,
2230 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2231 },
2232 { /* 50 Hz */
2233 .clock = 5400,
2234 .hdisplay = 320,
2235 .hsync_start = 320 + 56,
2236 .hsync_end = 320 + 56 + 16,
2237 .htotal = 320 + 56 + 16 + 40,
2238 .vdisplay = 240,
2239 .vsync_start = 240 + 2,
2240 .vsync_end = 240 + 2 + 6,
2241 .vtotal = 240 + 2 + 6 + 2,
2242 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2243 },
2244 };
2245
2246 static const struct panel_desc frida_frd350h54004 = {
2247 .modes = frida_frd350h54004_modes,
2248 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
2249 .bpc = 8,
2250 .size = {
2251 .width = 77,
2252 .height = 64,
2253 },
2254 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2255 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2256 .connector_type = DRM_MODE_CONNECTOR_DPI,
2257 };
2258
2259 static const struct drm_display_mode friendlyarm_hd702e_mode = {
2260 .clock = 67185,
2261 .hdisplay = 800,
2262 .hsync_start = 800 + 20,
2263 .hsync_end = 800 + 20 + 24,
2264 .htotal = 800 + 20 + 24 + 20,
2265 .vdisplay = 1280,
2266 .vsync_start = 1280 + 4,
2267 .vsync_end = 1280 + 4 + 8,
2268 .vtotal = 1280 + 4 + 8 + 4,
2269 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2270 };
2271
2272 static const struct panel_desc friendlyarm_hd702e = {
2273 .modes = &friendlyarm_hd702e_mode,
2274 .num_modes = 1,
2275 .size = {
2276 .width = 94,
2277 .height = 151,
2278 },
2279 };
2280
2281 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2282 .clock = 9000,
2283 .hdisplay = 480,
2284 .hsync_start = 480 + 5,
2285 .hsync_end = 480 + 5 + 1,
2286 .htotal = 480 + 5 + 1 + 40,
2287 .vdisplay = 272,
2288 .vsync_start = 272 + 8,
2289 .vsync_end = 272 + 8 + 1,
2290 .vtotal = 272 + 8 + 1 + 8,
2291 };
2292
2293 static const struct panel_desc giantplus_gpg482739qs5 = {
2294 .modes = &giantplus_gpg482739qs5_mode,
2295 .num_modes = 1,
2296 .bpc = 8,
2297 .size = {
2298 .width = 95,
2299 .height = 54,
2300 },
2301 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2302 };
2303
2304 static const struct display_timing giantplus_gpm940b0_timing = {
2305 .pixelclock = { 13500000, 27000000, 27500000 },
2306 .hactive = { 320, 320, 320 },
2307 .hfront_porch = { 14, 686, 718 },
2308 .hback_porch = { 50, 70, 255 },
2309 .hsync_len = { 1, 1, 1 },
2310 .vactive = { 240, 240, 240 },
2311 .vfront_porch = { 1, 1, 179 },
2312 .vback_porch = { 1, 21, 31 },
2313 .vsync_len = { 1, 1, 6 },
2314 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2315 };
2316
2317 static const struct panel_desc giantplus_gpm940b0 = {
2318 .timings = &giantplus_gpm940b0_timing,
2319 .num_timings = 1,
2320 .bpc = 8,
2321 .size = {
2322 .width = 60,
2323 .height = 45,
2324 },
2325 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2326 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2327 };
2328
2329 static const struct display_timing hannstar_hsd070pww1_timing = {
2330 .pixelclock = { 64300000, 71100000, 82000000 },
2331 .hactive = { 1280, 1280, 1280 },
2332 .hfront_porch = { 1, 1, 10 },
2333 .hback_porch = { 1, 1, 10 },
2334 /*
2335 * According to the data sheet, the minimum horizontal blanking interval
2336 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2337 * minimum working horizontal blanking interval to be 60 clocks.
2338 */
2339 .hsync_len = { 58, 158, 661 },
2340 .vactive = { 800, 800, 800 },
2341 .vfront_porch = { 1, 1, 10 },
2342 .vback_porch = { 1, 1, 10 },
2343 .vsync_len = { 1, 21, 203 },
2344 .flags = DISPLAY_FLAGS_DE_HIGH,
2345 };
2346
2347 static const struct panel_desc hannstar_hsd070pww1 = {
2348 .timings = &hannstar_hsd070pww1_timing,
2349 .num_timings = 1,
2350 .bpc = 6,
2351 .size = {
2352 .width = 151,
2353 .height = 94,
2354 },
2355 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2356 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2357 };
2358
2359 static const struct display_timing hannstar_hsd100pxn1_timing = {
2360 .pixelclock = { 55000000, 65000000, 75000000 },
2361 .hactive = { 1024, 1024, 1024 },
2362 .hfront_porch = { 40, 40, 40 },
2363 .hback_porch = { 220, 220, 220 },
2364 .hsync_len = { 20, 60, 100 },
2365 .vactive = { 768, 768, 768 },
2366 .vfront_porch = { 7, 7, 7 },
2367 .vback_porch = { 21, 21, 21 },
2368 .vsync_len = { 10, 10, 10 },
2369 .flags = DISPLAY_FLAGS_DE_HIGH,
2370 };
2371
2372 static const struct panel_desc hannstar_hsd100pxn1 = {
2373 .timings = &hannstar_hsd100pxn1_timing,
2374 .num_timings = 1,
2375 .bpc = 6,
2376 .size = {
2377 .width = 203,
2378 .height = 152,
2379 },
2380 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2381 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2382 };
2383
2384 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2385 .clock = 33333,
2386 .hdisplay = 800,
2387 .hsync_start = 800 + 85,
2388 .hsync_end = 800 + 85 + 86,
2389 .htotal = 800 + 85 + 86 + 85,
2390 .vdisplay = 480,
2391 .vsync_start = 480 + 16,
2392 .vsync_end = 480 + 16 + 13,
2393 .vtotal = 480 + 16 + 13 + 16,
2394 };
2395
2396 static const struct panel_desc hitachi_tx23d38vm0caa = {
2397 .modes = &hitachi_tx23d38vm0caa_mode,
2398 .num_modes = 1,
2399 .bpc = 6,
2400 .size = {
2401 .width = 195,
2402 .height = 117,
2403 },
2404 .delay = {
2405 .enable = 160,
2406 .disable = 160,
2407 },
2408 };
2409
2410 static const struct drm_display_mode innolux_at043tn24_mode = {
2411 .clock = 9000,
2412 .hdisplay = 480,
2413 .hsync_start = 480 + 2,
2414 .hsync_end = 480 + 2 + 41,
2415 .htotal = 480 + 2 + 41 + 2,
2416 .vdisplay = 272,
2417 .vsync_start = 272 + 2,
2418 .vsync_end = 272 + 2 + 10,
2419 .vtotal = 272 + 2 + 10 + 2,
2420 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2421 };
2422
2423 static const struct panel_desc innolux_at043tn24 = {
2424 .modes = &innolux_at043tn24_mode,
2425 .num_modes = 1,
2426 .bpc = 8,
2427 .size = {
2428 .width = 95,
2429 .height = 54,
2430 },
2431 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2432 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2433 };
2434
2435 static const struct drm_display_mode innolux_at070tn92_mode = {
2436 .clock = 33333,
2437 .hdisplay = 800,
2438 .hsync_start = 800 + 210,
2439 .hsync_end = 800 + 210 + 20,
2440 .htotal = 800 + 210 + 20 + 46,
2441 .vdisplay = 480,
2442 .vsync_start = 480 + 22,
2443 .vsync_end = 480 + 22 + 10,
2444 .vtotal = 480 + 22 + 23 + 10,
2445 };
2446
2447 static const struct panel_desc innolux_at070tn92 = {
2448 .modes = &innolux_at070tn92_mode,
2449 .num_modes = 1,
2450 .size = {
2451 .width = 154,
2452 .height = 86,
2453 },
2454 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2455 };
2456
2457 static const struct display_timing innolux_g070y2_l01_timing = {
2458 .pixelclock = { 28000000, 29500000, 32000000 },
2459 .hactive = { 800, 800, 800 },
2460 .hfront_porch = { 61, 91, 141 },
2461 .hback_porch = { 60, 90, 140 },
2462 .hsync_len = { 12, 12, 12 },
2463 .vactive = { 480, 480, 480 },
2464 .vfront_porch = { 4, 9, 30 },
2465 .vback_porch = { 4, 8, 28 },
2466 .vsync_len = { 2, 2, 2 },
2467 .flags = DISPLAY_FLAGS_DE_HIGH,
2468 };
2469
2470 static const struct panel_desc innolux_g070y2_l01 = {
2471 .timings = &innolux_g070y2_l01_timing,
2472 .num_timings = 1,
2473 .bpc = 8,
2474 .size = {
2475 .width = 152,
2476 .height = 91,
2477 },
2478 .delay = {
2479 .prepare = 10,
2480 .enable = 100,
2481 .disable = 100,
2482 .unprepare = 800,
2483 },
2484 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2485 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2486 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2487 };
2488
2489 static const struct display_timing innolux_g101ice_l01_timing = {
2490 .pixelclock = { 60400000, 71100000, 74700000 },
2491 .hactive = { 1280, 1280, 1280 },
2492 .hfront_porch = { 41, 80, 100 },
2493 .hback_porch = { 40, 79, 99 },
2494 .hsync_len = { 1, 1, 1 },
2495 .vactive = { 800, 800, 800 },
2496 .vfront_porch = { 5, 11, 14 },
2497 .vback_porch = { 4, 11, 14 },
2498 .vsync_len = { 1, 1, 1 },
2499 .flags = DISPLAY_FLAGS_DE_HIGH,
2500 };
2501
2502 static const struct panel_desc innolux_g101ice_l01 = {
2503 .timings = &innolux_g101ice_l01_timing,
2504 .num_timings = 1,
2505 .bpc = 8,
2506 .size = {
2507 .width = 217,
2508 .height = 135,
2509 },
2510 .delay = {
2511 .enable = 200,
2512 .disable = 200,
2513 },
2514 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2515 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2516 };
2517
2518 static const struct display_timing innolux_g121i1_l01_timing = {
2519 .pixelclock = { 67450000, 71000000, 74550000 },
2520 .hactive = { 1280, 1280, 1280 },
2521 .hfront_porch = { 40, 80, 160 },
2522 .hback_porch = { 39, 79, 159 },
2523 .hsync_len = { 1, 1, 1 },
2524 .vactive = { 800, 800, 800 },
2525 .vfront_porch = { 5, 11, 100 },
2526 .vback_porch = { 4, 11, 99 },
2527 .vsync_len = { 1, 1, 1 },
2528 };
2529
2530 static const struct panel_desc innolux_g121i1_l01 = {
2531 .timings = &innolux_g121i1_l01_timing,
2532 .num_timings = 1,
2533 .bpc = 6,
2534 .size = {
2535 .width = 261,
2536 .height = 163,
2537 },
2538 .delay = {
2539 .enable = 200,
2540 .disable = 20,
2541 },
2542 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2543 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2544 };
2545
2546 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2547 .clock = 65000,
2548 .hdisplay = 1024,
2549 .hsync_start = 1024 + 0,
2550 .hsync_end = 1024 + 1,
2551 .htotal = 1024 + 0 + 1 + 320,
2552 .vdisplay = 768,
2553 .vsync_start = 768 + 38,
2554 .vsync_end = 768 + 38 + 1,
2555 .vtotal = 768 + 38 + 1 + 0,
2556 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2557 };
2558
2559 static const struct panel_desc innolux_g121x1_l03 = {
2560 .modes = &innolux_g121x1_l03_mode,
2561 .num_modes = 1,
2562 .bpc = 6,
2563 .size = {
2564 .width = 246,
2565 .height = 185,
2566 },
2567 .delay = {
2568 .enable = 200,
2569 .unprepare = 200,
2570 .disable = 400,
2571 },
2572 };
2573
2574 /*
2575 * Datasheet specifies that at 60 Hz refresh rate:
2576 * - total horizontal time: { 1506, 1592, 1716 }
2577 * - total vertical time: { 788, 800, 868 }
2578 *
2579 * ...but doesn't go into exactly how that should be split into a front
2580 * porch, back porch, or sync length. For now we'll leave a single setting
2581 * here which allows a bit of tweaking of the pixel clock at the expense of
2582 * refresh rate.
2583 */
2584 static const struct display_timing innolux_n116bge_timing = {
2585 .pixelclock = { 72600000, 76420000, 80240000 },
2586 .hactive = { 1366, 1366, 1366 },
2587 .hfront_porch = { 136, 136, 136 },
2588 .hback_porch = { 60, 60, 60 },
2589 .hsync_len = { 30, 30, 30 },
2590 .vactive = { 768, 768, 768 },
2591 .vfront_porch = { 8, 8, 8 },
2592 .vback_porch = { 12, 12, 12 },
2593 .vsync_len = { 12, 12, 12 },
2594 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2595 };
2596
2597 static const struct panel_desc innolux_n116bge = {
2598 .timings = &innolux_n116bge_timing,
2599 .num_timings = 1,
2600 .bpc = 6,
2601 .size = {
2602 .width = 256,
2603 .height = 144,
2604 },
2605 };
2606
2607 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2608 .clock = 69300,
2609 .hdisplay = 1366,
2610 .hsync_start = 1366 + 16,
2611 .hsync_end = 1366 + 16 + 34,
2612 .htotal = 1366 + 16 + 34 + 50,
2613 .vdisplay = 768,
2614 .vsync_start = 768 + 2,
2615 .vsync_end = 768 + 2 + 6,
2616 .vtotal = 768 + 2 + 6 + 12,
2617 };
2618
2619 static const struct panel_desc innolux_n156bge_l21 = {
2620 .modes = &innolux_n156bge_l21_mode,
2621 .num_modes = 1,
2622 .bpc = 6,
2623 .size = {
2624 .width = 344,
2625 .height = 193,
2626 },
2627 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2628 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2629 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2630 };
2631
2632 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
2633 .clock = 206016,
2634 .hdisplay = 2160,
2635 .hsync_start = 2160 + 48,
2636 .hsync_end = 2160 + 48 + 32,
2637 .htotal = 2160 + 48 + 32 + 80,
2638 .vdisplay = 1440,
2639 .vsync_start = 1440 + 3,
2640 .vsync_end = 1440 + 3 + 10,
2641 .vtotal = 1440 + 3 + 10 + 27,
2642 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2643 };
2644
2645 static const struct panel_desc innolux_p120zdg_bf1 = {
2646 .modes = &innolux_p120zdg_bf1_mode,
2647 .num_modes = 1,
2648 .bpc = 8,
2649 .size = {
2650 .width = 254,
2651 .height = 169,
2652 },
2653 .delay = {
2654 .hpd_absent_delay = 200,
2655 .unprepare = 500,
2656 },
2657 };
2658
2659 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2660 .clock = 51501,
2661 .hdisplay = 1024,
2662 .hsync_start = 1024 + 128,
2663 .hsync_end = 1024 + 128 + 64,
2664 .htotal = 1024 + 128 + 64 + 128,
2665 .vdisplay = 600,
2666 .vsync_start = 600 + 16,
2667 .vsync_end = 600 + 16 + 4,
2668 .vtotal = 600 + 16 + 4 + 16,
2669 };
2670
2671 static const struct panel_desc innolux_zj070na_01p = {
2672 .modes = &innolux_zj070na_01p_mode,
2673 .num_modes = 1,
2674 .bpc = 6,
2675 .size = {
2676 .width = 154,
2677 .height = 90,
2678 },
2679 };
2680
2681 static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2682 .clock = 138778,
2683 .hdisplay = 1920,
2684 .hsync_start = 1920 + 24,
2685 .hsync_end = 1920 + 24 + 48,
2686 .htotal = 1920 + 24 + 48 + 88,
2687 .vdisplay = 1080,
2688 .vsync_start = 1080 + 3,
2689 .vsync_end = 1080 + 3 + 12,
2690 .vtotal = 1080 + 3 + 12 + 17,
2691 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2692 };
2693
2694 static const struct panel_desc ivo_m133nwf4_r0 = {
2695 .modes = &ivo_m133nwf4_r0_mode,
2696 .num_modes = 1,
2697 .bpc = 8,
2698 .size = {
2699 .width = 294,
2700 .height = 165,
2701 },
2702 .delay = {
2703 .hpd_absent_delay = 200,
2704 .unprepare = 500,
2705 },
2706 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2707 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2708 .connector_type = DRM_MODE_CONNECTOR_eDP,
2709 };
2710
2711 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
2712 .clock = 81000,
2713 .hdisplay = 1366,
2714 .hsync_start = 1366 + 40,
2715 .hsync_end = 1366 + 40 + 32,
2716 .htotal = 1366 + 40 + 32 + 62,
2717 .vdisplay = 768,
2718 .vsync_start = 768 + 5,
2719 .vsync_end = 768 + 5 + 5,
2720 .vtotal = 768 + 5 + 5 + 122,
2721 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2722 };
2723
2724 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
2725 .modes = &kingdisplay_kd116n21_30nv_a010_mode,
2726 .num_modes = 1,
2727 .bpc = 6,
2728 .size = {
2729 .width = 256,
2730 .height = 144,
2731 },
2732 .delay = {
2733 .hpd_absent_delay = 200,
2734 },
2735 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2736 .connector_type = DRM_MODE_CONNECTOR_eDP,
2737 };
2738
2739 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2740 .pixelclock = { 5580000, 5850000, 6200000 },
2741 .hactive = { 320, 320, 320 },
2742 .hfront_porch = { 30, 30, 30 },
2743 .hback_porch = { 30, 30, 30 },
2744 .hsync_len = { 1, 5, 17 },
2745 .vactive = { 240, 240, 240 },
2746 .vfront_porch = { 6, 6, 6 },
2747 .vback_porch = { 5, 5, 5 },
2748 .vsync_len = { 1, 2, 11 },
2749 .flags = DISPLAY_FLAGS_DE_HIGH,
2750 };
2751
2752 static const struct panel_desc koe_tx14d24vm1bpa = {
2753 .timings = &koe_tx14d24vm1bpa_timing,
2754 .num_timings = 1,
2755 .bpc = 6,
2756 .size = {
2757 .width = 115,
2758 .height = 86,
2759 },
2760 };
2761
2762 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2763 .pixelclock = { 151820000, 156720000, 159780000 },
2764 .hactive = { 1920, 1920, 1920 },
2765 .hfront_porch = { 105, 130, 142 },
2766 .hback_porch = { 45, 70, 82 },
2767 .hsync_len = { 30, 30, 30 },
2768 .vactive = { 1200, 1200, 1200},
2769 .vfront_porch = { 3, 5, 10 },
2770 .vback_porch = { 2, 5, 10 },
2771 .vsync_len = { 5, 5, 5 },
2772 };
2773
2774 static const struct panel_desc koe_tx26d202vm0bwa = {
2775 .timings = &koe_tx26d202vm0bwa_timing,
2776 .num_timings = 1,
2777 .bpc = 8,
2778 .size = {
2779 .width = 217,
2780 .height = 136,
2781 },
2782 .delay = {
2783 .prepare = 1000,
2784 .enable = 1000,
2785 .unprepare = 1000,
2786 .disable = 1000,
2787 },
2788 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2789 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2790 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2791 };
2792
2793 static const struct display_timing koe_tx31d200vm0baa_timing = {
2794 .pixelclock = { 39600000, 43200000, 48000000 },
2795 .hactive = { 1280, 1280, 1280 },
2796 .hfront_porch = { 16, 36, 56 },
2797 .hback_porch = { 16, 36, 56 },
2798 .hsync_len = { 8, 8, 8 },
2799 .vactive = { 480, 480, 480 },
2800 .vfront_porch = { 6, 21, 33 },
2801 .vback_porch = { 6, 21, 33 },
2802 .vsync_len = { 8, 8, 8 },
2803 .flags = DISPLAY_FLAGS_DE_HIGH,
2804 };
2805
2806 static const struct panel_desc koe_tx31d200vm0baa = {
2807 .timings = &koe_tx31d200vm0baa_timing,
2808 .num_timings = 1,
2809 .bpc = 6,
2810 .size = {
2811 .width = 292,
2812 .height = 109,
2813 },
2814 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2815 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2816 };
2817
2818 static const struct display_timing kyo_tcg121xglp_timing = {
2819 .pixelclock = { 52000000, 65000000, 71000000 },
2820 .hactive = { 1024, 1024, 1024 },
2821 .hfront_porch = { 2, 2, 2 },
2822 .hback_porch = { 2, 2, 2 },
2823 .hsync_len = { 86, 124, 244 },
2824 .vactive = { 768, 768, 768 },
2825 .vfront_porch = { 2, 2, 2 },
2826 .vback_porch = { 2, 2, 2 },
2827 .vsync_len = { 6, 34, 73 },
2828 .flags = DISPLAY_FLAGS_DE_HIGH,
2829 };
2830
2831 static const struct panel_desc kyo_tcg121xglp = {
2832 .timings = &kyo_tcg121xglp_timing,
2833 .num_timings = 1,
2834 .bpc = 8,
2835 .size = {
2836 .width = 246,
2837 .height = 184,
2838 },
2839 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2840 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2841 };
2842
2843 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2844 .clock = 7000,
2845 .hdisplay = 320,
2846 .hsync_start = 320 + 20,
2847 .hsync_end = 320 + 20 + 30,
2848 .htotal = 320 + 20 + 30 + 38,
2849 .vdisplay = 240,
2850 .vsync_start = 240 + 4,
2851 .vsync_end = 240 + 4 + 3,
2852 .vtotal = 240 + 4 + 3 + 15,
2853 };
2854
2855 static const struct panel_desc lemaker_bl035_rgb_002 = {
2856 .modes = &lemaker_bl035_rgb_002_mode,
2857 .num_modes = 1,
2858 .size = {
2859 .width = 70,
2860 .height = 52,
2861 },
2862 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2863 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2864 };
2865
2866 static const struct drm_display_mode lg_lb070wv8_mode = {
2867 .clock = 33246,
2868 .hdisplay = 800,
2869 .hsync_start = 800 + 88,
2870 .hsync_end = 800 + 88 + 80,
2871 .htotal = 800 + 88 + 80 + 88,
2872 .vdisplay = 480,
2873 .vsync_start = 480 + 10,
2874 .vsync_end = 480 + 10 + 25,
2875 .vtotal = 480 + 10 + 25 + 10,
2876 };
2877
2878 static const struct panel_desc lg_lb070wv8 = {
2879 .modes = &lg_lb070wv8_mode,
2880 .num_modes = 1,
2881 .bpc = 8,
2882 .size = {
2883 .width = 151,
2884 .height = 91,
2885 },
2886 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2887 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2888 };
2889
2890 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2891 .clock = 200000,
2892 .hdisplay = 1536,
2893 .hsync_start = 1536 + 12,
2894 .hsync_end = 1536 + 12 + 16,
2895 .htotal = 1536 + 12 + 16 + 48,
2896 .vdisplay = 2048,
2897 .vsync_start = 2048 + 8,
2898 .vsync_end = 2048 + 8 + 4,
2899 .vtotal = 2048 + 8 + 4 + 8,
2900 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2901 };
2902
2903 static const struct panel_desc lg_lp079qx1_sp0v = {
2904 .modes = &lg_lp079qx1_sp0v_mode,
2905 .num_modes = 1,
2906 .size = {
2907 .width = 129,
2908 .height = 171,
2909 },
2910 };
2911
2912 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2913 .clock = 205210,
2914 .hdisplay = 2048,
2915 .hsync_start = 2048 + 150,
2916 .hsync_end = 2048 + 150 + 5,
2917 .htotal = 2048 + 150 + 5 + 5,
2918 .vdisplay = 1536,
2919 .vsync_start = 1536 + 3,
2920 .vsync_end = 1536 + 3 + 1,
2921 .vtotal = 1536 + 3 + 1 + 9,
2922 };
2923
2924 static const struct panel_desc lg_lp097qx1_spa1 = {
2925 .modes = &lg_lp097qx1_spa1_mode,
2926 .num_modes = 1,
2927 .size = {
2928 .width = 208,
2929 .height = 147,
2930 },
2931 };
2932
2933 static const struct drm_display_mode lg_lp120up1_mode = {
2934 .clock = 162300,
2935 .hdisplay = 1920,
2936 .hsync_start = 1920 + 40,
2937 .hsync_end = 1920 + 40 + 40,
2938 .htotal = 1920 + 40 + 40+ 80,
2939 .vdisplay = 1280,
2940 .vsync_start = 1280 + 4,
2941 .vsync_end = 1280 + 4 + 4,
2942 .vtotal = 1280 + 4 + 4 + 12,
2943 };
2944
2945 static const struct panel_desc lg_lp120up1 = {
2946 .modes = &lg_lp120up1_mode,
2947 .num_modes = 1,
2948 .bpc = 8,
2949 .size = {
2950 .width = 267,
2951 .height = 183,
2952 },
2953 .connector_type = DRM_MODE_CONNECTOR_eDP,
2954 };
2955
2956 static const struct drm_display_mode lg_lp129qe_mode = {
2957 .clock = 285250,
2958 .hdisplay = 2560,
2959 .hsync_start = 2560 + 48,
2960 .hsync_end = 2560 + 48 + 32,
2961 .htotal = 2560 + 48 + 32 + 80,
2962 .vdisplay = 1700,
2963 .vsync_start = 1700 + 3,
2964 .vsync_end = 1700 + 3 + 10,
2965 .vtotal = 1700 + 3 + 10 + 36,
2966 };
2967
2968 static const struct panel_desc lg_lp129qe = {
2969 .modes = &lg_lp129qe_mode,
2970 .num_modes = 1,
2971 .bpc = 8,
2972 .size = {
2973 .width = 272,
2974 .height = 181,
2975 },
2976 };
2977
2978 static const struct display_timing logictechno_lt161010_2nh_timing = {
2979 .pixelclock = { 26400000, 33300000, 46800000 },
2980 .hactive = { 800, 800, 800 },
2981 .hfront_porch = { 16, 210, 354 },
2982 .hback_porch = { 46, 46, 46 },
2983 .hsync_len = { 1, 20, 40 },
2984 .vactive = { 480, 480, 480 },
2985 .vfront_porch = { 7, 22, 147 },
2986 .vback_porch = { 23, 23, 23 },
2987 .vsync_len = { 1, 10, 20 },
2988 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2989 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2990 DISPLAY_FLAGS_SYNC_POSEDGE,
2991 };
2992
2993 static const struct panel_desc logictechno_lt161010_2nh = {
2994 .timings = &logictechno_lt161010_2nh_timing,
2995 .num_timings = 1,
2996 .bpc = 6,
2997 .size = {
2998 .width = 154,
2999 .height = 86,
3000 },
3001 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3002 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3003 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3004 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3005 .connector_type = DRM_MODE_CONNECTOR_DPI,
3006 };
3007
3008 static const struct display_timing logictechno_lt170410_2whc_timing = {
3009 .pixelclock = { 68900000, 71100000, 73400000 },
3010 .hactive = { 1280, 1280, 1280 },
3011 .hfront_porch = { 23, 60, 71 },
3012 .hback_porch = { 23, 60, 71 },
3013 .hsync_len = { 15, 40, 47 },
3014 .vactive = { 800, 800, 800 },
3015 .vfront_porch = { 5, 7, 10 },
3016 .vback_porch = { 5, 7, 10 },
3017 .vsync_len = { 6, 9, 12 },
3018 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3019 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3020 DISPLAY_FLAGS_SYNC_POSEDGE,
3021 };
3022
3023 static const struct panel_desc logictechno_lt170410_2whc = {
3024 .timings = &logictechno_lt170410_2whc_timing,
3025 .num_timings = 1,
3026 .bpc = 8,
3027 .size = {
3028 .width = 217,
3029 .height = 136,
3030 },
3031 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3032 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3033 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3034 };
3035
3036 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
3037 .clock = 30400,
3038 .hdisplay = 800,
3039 .hsync_start = 800 + 0,
3040 .hsync_end = 800 + 1,
3041 .htotal = 800 + 0 + 1 + 160,
3042 .vdisplay = 480,
3043 .vsync_start = 480 + 0,
3044 .vsync_end = 480 + 48 + 1,
3045 .vtotal = 480 + 48 + 1 + 0,
3046 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3047 };
3048
3049 static const struct drm_display_mode logicpd_type_28_mode = {
3050 .clock = 9107,
3051 .hdisplay = 480,
3052 .hsync_start = 480 + 3,
3053 .hsync_end = 480 + 3 + 42,
3054 .htotal = 480 + 3 + 42 + 2,
3055
3056 .vdisplay = 272,
3057 .vsync_start = 272 + 2,
3058 .vsync_end = 272 + 2 + 11,
3059 .vtotal = 272 + 2 + 11 + 3,
3060 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3061 };
3062
3063 static const struct panel_desc logicpd_type_28 = {
3064 .modes = &logicpd_type_28_mode,
3065 .num_modes = 1,
3066 .bpc = 8,
3067 .size = {
3068 .width = 105,
3069 .height = 67,
3070 },
3071 .delay = {
3072 .prepare = 200,
3073 .enable = 200,
3074 .unprepare = 200,
3075 .disable = 200,
3076 },
3077 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3078 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3079 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
3080 .connector_type = DRM_MODE_CONNECTOR_DPI,
3081 };
3082
3083 static const struct panel_desc mitsubishi_aa070mc01 = {
3084 .modes = &mitsubishi_aa070mc01_mode,
3085 .num_modes = 1,
3086 .bpc = 8,
3087 .size = {
3088 .width = 152,
3089 .height = 91,
3090 },
3091
3092 .delay = {
3093 .enable = 200,
3094 .unprepare = 200,
3095 .disable = 400,
3096 },
3097 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3098 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3099 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3100 };
3101
3102 static const struct display_timing nec_nl12880bc20_05_timing = {
3103 .pixelclock = { 67000000, 71000000, 75000000 },
3104 .hactive = { 1280, 1280, 1280 },
3105 .hfront_porch = { 2, 30, 30 },
3106 .hback_porch = { 6, 100, 100 },
3107 .hsync_len = { 2, 30, 30 },
3108 .vactive = { 800, 800, 800 },
3109 .vfront_porch = { 5, 5, 5 },
3110 .vback_porch = { 11, 11, 11 },
3111 .vsync_len = { 7, 7, 7 },
3112 };
3113
3114 static const struct panel_desc nec_nl12880bc20_05 = {
3115 .timings = &nec_nl12880bc20_05_timing,
3116 .num_timings = 1,
3117 .bpc = 8,
3118 .size = {
3119 .width = 261,
3120 .height = 163,
3121 },
3122 .delay = {
3123 .enable = 50,
3124 .disable = 50,
3125 },
3126 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3127 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3128 };
3129
3130 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
3131 .clock = 10870,
3132 .hdisplay = 480,
3133 .hsync_start = 480 + 2,
3134 .hsync_end = 480 + 2 + 41,
3135 .htotal = 480 + 2 + 41 + 2,
3136 .vdisplay = 272,
3137 .vsync_start = 272 + 2,
3138 .vsync_end = 272 + 2 + 4,
3139 .vtotal = 272 + 2 + 4 + 2,
3140 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3141 };
3142
3143 static const struct panel_desc nec_nl4827hc19_05b = {
3144 .modes = &nec_nl4827hc19_05b_mode,
3145 .num_modes = 1,
3146 .bpc = 8,
3147 .size = {
3148 .width = 95,
3149 .height = 54,
3150 },
3151 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3152 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3153 };
3154
3155 static const struct drm_display_mode netron_dy_e231732_mode = {
3156 .clock = 66000,
3157 .hdisplay = 1024,
3158 .hsync_start = 1024 + 160,
3159 .hsync_end = 1024 + 160 + 70,
3160 .htotal = 1024 + 160 + 70 + 90,
3161 .vdisplay = 600,
3162 .vsync_start = 600 + 127,
3163 .vsync_end = 600 + 127 + 20,
3164 .vtotal = 600 + 127 + 20 + 3,
3165 };
3166
3167 static const struct panel_desc netron_dy_e231732 = {
3168 .modes = &netron_dy_e231732_mode,
3169 .num_modes = 1,
3170 .size = {
3171 .width = 154,
3172 .height = 87,
3173 },
3174 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3175 };
3176
3177 static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
3178 {
3179 .clock = 138500,
3180 .hdisplay = 1920,
3181 .hsync_start = 1920 + 48,
3182 .hsync_end = 1920 + 48 + 32,
3183 .htotal = 1920 + 48 + 32 + 80,
3184 .vdisplay = 1080,
3185 .vsync_start = 1080 + 3,
3186 .vsync_end = 1080 + 3 + 5,
3187 .vtotal = 1080 + 3 + 5 + 23,
3188 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3189 }, {
3190 .clock = 110920,
3191 .hdisplay = 1920,
3192 .hsync_start = 1920 + 48,
3193 .hsync_end = 1920 + 48 + 32,
3194 .htotal = 1920 + 48 + 32 + 80,
3195 .vdisplay = 1080,
3196 .vsync_start = 1080 + 3,
3197 .vsync_end = 1080 + 3 + 5,
3198 .vtotal = 1080 + 3 + 5 + 23,
3199 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3200 }
3201 };
3202
3203 static const struct panel_desc neweast_wjfh116008a = {
3204 .modes = neweast_wjfh116008a_modes,
3205 .num_modes = 2,
3206 .bpc = 6,
3207 .size = {
3208 .width = 260,
3209 .height = 150,
3210 },
3211 .delay = {
3212 .prepare = 110,
3213 .enable = 20,
3214 .unprepare = 500,
3215 },
3216 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3217 .connector_type = DRM_MODE_CONNECTOR_eDP,
3218 };
3219
3220 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3221 .clock = 9000,
3222 .hdisplay = 480,
3223 .hsync_start = 480 + 2,
3224 .hsync_end = 480 + 2 + 41,
3225 .htotal = 480 + 2 + 41 + 2,
3226 .vdisplay = 272,
3227 .vsync_start = 272 + 2,
3228 .vsync_end = 272 + 2 + 10,
3229 .vtotal = 272 + 2 + 10 + 2,
3230 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3231 };
3232
3233 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3234 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3235 .num_modes = 1,
3236 .bpc = 8,
3237 .size = {
3238 .width = 95,
3239 .height = 54,
3240 },
3241 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3242 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3243 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3244 .connector_type = DRM_MODE_CONNECTOR_DPI,
3245 };
3246
3247 static const struct display_timing nlt_nl192108ac18_02d_timing = {
3248 .pixelclock = { 130000000, 148350000, 163000000 },
3249 .hactive = { 1920, 1920, 1920 },
3250 .hfront_porch = { 80, 100, 100 },
3251 .hback_porch = { 100, 120, 120 },
3252 .hsync_len = { 50, 60, 60 },
3253 .vactive = { 1080, 1080, 1080 },
3254 .vfront_porch = { 12, 30, 30 },
3255 .vback_porch = { 4, 10, 10 },
3256 .vsync_len = { 4, 5, 5 },
3257 };
3258
3259 static const struct panel_desc nlt_nl192108ac18_02d = {
3260 .timings = &nlt_nl192108ac18_02d_timing,
3261 .num_timings = 1,
3262 .bpc = 8,
3263 .size = {
3264 .width = 344,
3265 .height = 194,
3266 },
3267 .delay = {
3268 .unprepare = 500,
3269 },
3270 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3271 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3272 };
3273
3274 static const struct drm_display_mode nvd_9128_mode = {
3275 .clock = 29500,
3276 .hdisplay = 800,
3277 .hsync_start = 800 + 130,
3278 .hsync_end = 800 + 130 + 98,
3279 .htotal = 800 + 0 + 130 + 98,
3280 .vdisplay = 480,
3281 .vsync_start = 480 + 10,
3282 .vsync_end = 480 + 10 + 50,
3283 .vtotal = 480 + 0 + 10 + 50,
3284 };
3285
3286 static const struct panel_desc nvd_9128 = {
3287 .modes = &nvd_9128_mode,
3288 .num_modes = 1,
3289 .bpc = 8,
3290 .size = {
3291 .width = 156,
3292 .height = 88,
3293 },
3294 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3295 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3296 };
3297
3298 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3299 .pixelclock = { 30000000, 30000000, 40000000 },
3300 .hactive = { 800, 800, 800 },
3301 .hfront_porch = { 40, 40, 40 },
3302 .hback_porch = { 40, 40, 40 },
3303 .hsync_len = { 1, 48, 48 },
3304 .vactive = { 480, 480, 480 },
3305 .vfront_porch = { 13, 13, 13 },
3306 .vback_porch = { 29, 29, 29 },
3307 .vsync_len = { 3, 3, 3 },
3308 .flags = DISPLAY_FLAGS_DE_HIGH,
3309 };
3310
3311 static const struct panel_desc okaya_rs800480t_7x0gp = {
3312 .timings = &okaya_rs800480t_7x0gp_timing,
3313 .num_timings = 1,
3314 .bpc = 6,
3315 .size = {
3316 .width = 154,
3317 .height = 87,
3318 },
3319 .delay = {
3320 .prepare = 41,
3321 .enable = 50,
3322 .unprepare = 41,
3323 .disable = 50,
3324 },
3325 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3326 };
3327
3328 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3329 .clock = 9000,
3330 .hdisplay = 480,
3331 .hsync_start = 480 + 5,
3332 .hsync_end = 480 + 5 + 30,
3333 .htotal = 480 + 5 + 30 + 10,
3334 .vdisplay = 272,
3335 .vsync_start = 272 + 8,
3336 .vsync_end = 272 + 8 + 5,
3337 .vtotal = 272 + 8 + 5 + 3,
3338 };
3339
3340 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3341 .modes = &olimex_lcd_olinuxino_43ts_mode,
3342 .num_modes = 1,
3343 .size = {
3344 .width = 95,
3345 .height = 54,
3346 },
3347 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3348 };
3349
3350 /*
3351 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3352 * pixel clocks, but this is the timing that was being used in the Adafruit
3353 * installation instructions.
3354 */
3355 static const struct drm_display_mode ontat_yx700wv03_mode = {
3356 .clock = 29500,
3357 .hdisplay = 800,
3358 .hsync_start = 824,
3359 .hsync_end = 896,
3360 .htotal = 992,
3361 .vdisplay = 480,
3362 .vsync_start = 483,
3363 .vsync_end = 493,
3364 .vtotal = 500,
3365 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3366 };
3367
3368 /*
3369 * Specification at:
3370 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3371 */
3372 static const struct panel_desc ontat_yx700wv03 = {
3373 .modes = &ontat_yx700wv03_mode,
3374 .num_modes = 1,
3375 .bpc = 8,
3376 .size = {
3377 .width = 154,
3378 .height = 83,
3379 },
3380 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3381 };
3382
3383 static const struct drm_display_mode ortustech_com37h3m_mode = {
3384 .clock = 22230,
3385 .hdisplay = 480,
3386 .hsync_start = 480 + 40,
3387 .hsync_end = 480 + 40 + 10,
3388 .htotal = 480 + 40 + 10 + 40,
3389 .vdisplay = 640,
3390 .vsync_start = 640 + 4,
3391 .vsync_end = 640 + 4 + 2,
3392 .vtotal = 640 + 4 + 2 + 4,
3393 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3394 };
3395
3396 static const struct panel_desc ortustech_com37h3m = {
3397 .modes = &ortustech_com37h3m_mode,
3398 .num_modes = 1,
3399 .bpc = 8,
3400 .size = {
3401 .width = 56, /* 56.16mm */
3402 .height = 75, /* 74.88mm */
3403 },
3404 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3405 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3406 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3407 };
3408
3409 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3410 .clock = 25000,
3411 .hdisplay = 480,
3412 .hsync_start = 480 + 10,
3413 .hsync_end = 480 + 10 + 10,
3414 .htotal = 480 + 10 + 10 + 15,
3415 .vdisplay = 800,
3416 .vsync_start = 800 + 3,
3417 .vsync_end = 800 + 3 + 3,
3418 .vtotal = 800 + 3 + 3 + 3,
3419 };
3420
3421 static const struct panel_desc ortustech_com43h4m85ulc = {
3422 .modes = &ortustech_com43h4m85ulc_mode,
3423 .num_modes = 1,
3424 .bpc = 6,
3425 .size = {
3426 .width = 56,
3427 .height = 93,
3428 },
3429 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3430 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3431 .connector_type = DRM_MODE_CONNECTOR_DPI,
3432 };
3433
3434 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3435 .clock = 33000,
3436 .hdisplay = 800,
3437 .hsync_start = 800 + 210,
3438 .hsync_end = 800 + 210 + 30,
3439 .htotal = 800 + 210 + 30 + 16,
3440 .vdisplay = 480,
3441 .vsync_start = 480 + 22,
3442 .vsync_end = 480 + 22 + 13,
3443 .vtotal = 480 + 22 + 13 + 10,
3444 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3445 };
3446
3447 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3448 .modes = &osddisplays_osd070t1718_19ts_mode,
3449 .num_modes = 1,
3450 .bpc = 8,
3451 .size = {
3452 .width = 152,
3453 .height = 91,
3454 },
3455 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3456 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3457 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3458 .connector_type = DRM_MODE_CONNECTOR_DPI,
3459 };
3460
3461 static const struct drm_display_mode pda_91_00156_a0_mode = {
3462 .clock = 33300,
3463 .hdisplay = 800,
3464 .hsync_start = 800 + 1,
3465 .hsync_end = 800 + 1 + 64,
3466 .htotal = 800 + 1 + 64 + 64,
3467 .vdisplay = 480,
3468 .vsync_start = 480 + 1,
3469 .vsync_end = 480 + 1 + 23,
3470 .vtotal = 480 + 1 + 23 + 22,
3471 };
3472
3473 static const struct panel_desc pda_91_00156_a0 = {
3474 .modes = &pda_91_00156_a0_mode,
3475 .num_modes = 1,
3476 .size = {
3477 .width = 152,
3478 .height = 91,
3479 },
3480 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3481 };
3482
3483 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3484 .clock = 24750,
3485 .hdisplay = 800,
3486 .hsync_start = 800 + 54,
3487 .hsync_end = 800 + 54 + 2,
3488 .htotal = 800 + 54 + 2 + 44,
3489 .vdisplay = 480,
3490 .vsync_start = 480 + 49,
3491 .vsync_end = 480 + 49 + 2,
3492 .vtotal = 480 + 49 + 2 + 22,
3493 };
3494
3495 static const struct panel_desc powertip_ph800480t013_idf02 = {
3496 .modes = &powertip_ph800480t013_idf02_mode,
3497 .num_modes = 1,
3498 .size = {
3499 .width = 152,
3500 .height = 91,
3501 },
3502 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3503 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3504 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3505 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3506 .connector_type = DRM_MODE_CONNECTOR_DPI,
3507 };
3508
3509 static const struct drm_display_mode qd43003c0_40_mode = {
3510 .clock = 9000,
3511 .hdisplay = 480,
3512 .hsync_start = 480 + 8,
3513 .hsync_end = 480 + 8 + 4,
3514 .htotal = 480 + 8 + 4 + 39,
3515 .vdisplay = 272,
3516 .vsync_start = 272 + 4,
3517 .vsync_end = 272 + 4 + 10,
3518 .vtotal = 272 + 4 + 10 + 2,
3519 };
3520
3521 static const struct panel_desc qd43003c0_40 = {
3522 .modes = &qd43003c0_40_mode,
3523 .num_modes = 1,
3524 .bpc = 8,
3525 .size = {
3526 .width = 95,
3527 .height = 53,
3528 },
3529 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3530 };
3531
3532 static const struct display_timing rocktech_rk070er9427_timing = {
3533 .pixelclock = { 26400000, 33300000, 46800000 },
3534 .hactive = { 800, 800, 800 },
3535 .hfront_porch = { 16, 210, 354 },
3536 .hback_porch = { 46, 46, 46 },
3537 .hsync_len = { 1, 1, 1 },
3538 .vactive = { 480, 480, 480 },
3539 .vfront_porch = { 7, 22, 147 },
3540 .vback_porch = { 23, 23, 23 },
3541 .vsync_len = { 1, 1, 1 },
3542 .flags = DISPLAY_FLAGS_DE_HIGH,
3543 };
3544
3545 static const struct panel_desc rocktech_rk070er9427 = {
3546 .timings = &rocktech_rk070er9427_timing,
3547 .num_timings = 1,
3548 .bpc = 6,
3549 .size = {
3550 .width = 154,
3551 .height = 86,
3552 },
3553 .delay = {
3554 .prepare = 41,
3555 .enable = 50,
3556 .unprepare = 41,
3557 .disable = 50,
3558 },
3559 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3560 };
3561
3562 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3563 .clock = 71100,
3564 .hdisplay = 1280,
3565 .hsync_start = 1280 + 48,
3566 .hsync_end = 1280 + 48 + 32,
3567 .htotal = 1280 + 48 + 32 + 80,
3568 .vdisplay = 800,
3569 .vsync_start = 800 + 2,
3570 .vsync_end = 800 + 2 + 5,
3571 .vtotal = 800 + 2 + 5 + 16,
3572 };
3573
3574 static const struct panel_desc rocktech_rk101ii01d_ct = {
3575 .modes = &rocktech_rk101ii01d_ct_mode,
3576 .num_modes = 1,
3577 .size = {
3578 .width = 217,
3579 .height = 136,
3580 },
3581 .delay = {
3582 .prepare = 50,
3583 .disable = 50,
3584 },
3585 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3586 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3587 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3588 };
3589
3590 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3591 .clock = 271560,
3592 .hdisplay = 2560,
3593 .hsync_start = 2560 + 48,
3594 .hsync_end = 2560 + 48 + 32,
3595 .htotal = 2560 + 48 + 32 + 80,
3596 .vdisplay = 1600,
3597 .vsync_start = 1600 + 2,
3598 .vsync_end = 1600 + 2 + 5,
3599 .vtotal = 1600 + 2 + 5 + 57,
3600 };
3601
3602 static const struct panel_desc samsung_lsn122dl01_c01 = {
3603 .modes = &samsung_lsn122dl01_c01_mode,
3604 .num_modes = 1,
3605 .size = {
3606 .width = 263,
3607 .height = 164,
3608 },
3609 };
3610
3611 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3612 .clock = 54030,
3613 .hdisplay = 1024,
3614 .hsync_start = 1024 + 24,
3615 .hsync_end = 1024 + 24 + 136,
3616 .htotal = 1024 + 24 + 136 + 160,
3617 .vdisplay = 600,
3618 .vsync_start = 600 + 3,
3619 .vsync_end = 600 + 3 + 6,
3620 .vtotal = 600 + 3 + 6 + 61,
3621 };
3622
3623 static const struct panel_desc samsung_ltn101nt05 = {
3624 .modes = &samsung_ltn101nt05_mode,
3625 .num_modes = 1,
3626 .bpc = 6,
3627 .size = {
3628 .width = 223,
3629 .height = 125,
3630 },
3631 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3632 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3633 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3634 };
3635
3636 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3637 .clock = 76300,
3638 .hdisplay = 1366,
3639 .hsync_start = 1366 + 64,
3640 .hsync_end = 1366 + 64 + 48,
3641 .htotal = 1366 + 64 + 48 + 128,
3642 .vdisplay = 768,
3643 .vsync_start = 768 + 2,
3644 .vsync_end = 768 + 2 + 5,
3645 .vtotal = 768 + 2 + 5 + 17,
3646 };
3647
3648 static const struct panel_desc samsung_ltn140at29_301 = {
3649 .modes = &samsung_ltn140at29_301_mode,
3650 .num_modes = 1,
3651 .bpc = 6,
3652 .size = {
3653 .width = 320,
3654 .height = 187,
3655 },
3656 };
3657
3658 static const struct display_timing satoz_sat050at40h12r2_timing = {
3659 .pixelclock = {33300000, 33300000, 50000000},
3660 .hactive = {800, 800, 800},
3661 .hfront_porch = {16, 210, 354},
3662 .hback_porch = {46, 46, 46},
3663 .hsync_len = {1, 1, 40},
3664 .vactive = {480, 480, 480},
3665 .vfront_porch = {7, 22, 147},
3666 .vback_porch = {23, 23, 23},
3667 .vsync_len = {1, 1, 20},
3668 };
3669
3670 static const struct panel_desc satoz_sat050at40h12r2 = {
3671 .timings = &satoz_sat050at40h12r2_timing,
3672 .num_timings = 1,
3673 .bpc = 8,
3674 .size = {
3675 .width = 108,
3676 .height = 65,
3677 },
3678 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3679 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3680 };
3681
3682 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3683 .clock = 168480,
3684 .hdisplay = 1920,
3685 .hsync_start = 1920 + 48,
3686 .hsync_end = 1920 + 48 + 32,
3687 .htotal = 1920 + 48 + 32 + 80,
3688 .vdisplay = 1280,
3689 .vsync_start = 1280 + 3,
3690 .vsync_end = 1280 + 3 + 10,
3691 .vtotal = 1280 + 3 + 10 + 57,
3692 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3693 };
3694
3695 static const struct panel_desc sharp_ld_d5116z01b = {
3696 .modes = &sharp_ld_d5116z01b_mode,
3697 .num_modes = 1,
3698 .bpc = 8,
3699 .size = {
3700 .width = 260,
3701 .height = 120,
3702 },
3703 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3704 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3705 };
3706
3707 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3708 .clock = 33260,
3709 .hdisplay = 800,
3710 .hsync_start = 800 + 64,
3711 .hsync_end = 800 + 64 + 128,
3712 .htotal = 800 + 64 + 128 + 64,
3713 .vdisplay = 480,
3714 .vsync_start = 480 + 8,
3715 .vsync_end = 480 + 8 + 2,
3716 .vtotal = 480 + 8 + 2 + 35,
3717 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3718 };
3719
3720 static const struct panel_desc sharp_lq070y3dg3b = {
3721 .modes = &sharp_lq070y3dg3b_mode,
3722 .num_modes = 1,
3723 .bpc = 8,
3724 .size = {
3725 .width = 152, /* 152.4mm */
3726 .height = 91, /* 91.4mm */
3727 },
3728 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3729 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3730 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3731 };
3732
3733 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3734 .clock = 5500,
3735 .hdisplay = 240,
3736 .hsync_start = 240 + 16,
3737 .hsync_end = 240 + 16 + 7,
3738 .htotal = 240 + 16 + 7 + 5,
3739 .vdisplay = 320,
3740 .vsync_start = 320 + 9,
3741 .vsync_end = 320 + 9 + 1,
3742 .vtotal = 320 + 9 + 1 + 7,
3743 };
3744
3745 static const struct panel_desc sharp_lq035q7db03 = {
3746 .modes = &sharp_lq035q7db03_mode,
3747 .num_modes = 1,
3748 .bpc = 6,
3749 .size = {
3750 .width = 54,
3751 .height = 72,
3752 },
3753 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3754 };
3755
3756 static const struct display_timing sharp_lq101k1ly04_timing = {
3757 .pixelclock = { 60000000, 65000000, 80000000 },
3758 .hactive = { 1280, 1280, 1280 },
3759 .hfront_porch = { 20, 20, 20 },
3760 .hback_porch = { 20, 20, 20 },
3761 .hsync_len = { 10, 10, 10 },
3762 .vactive = { 800, 800, 800 },
3763 .vfront_porch = { 4, 4, 4 },
3764 .vback_porch = { 4, 4, 4 },
3765 .vsync_len = { 4, 4, 4 },
3766 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3767 };
3768
3769 static const struct panel_desc sharp_lq101k1ly04 = {
3770 .timings = &sharp_lq101k1ly04_timing,
3771 .num_timings = 1,
3772 .bpc = 8,
3773 .size = {
3774 .width = 217,
3775 .height = 136,
3776 },
3777 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3778 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3779 };
3780
3781 static const struct display_timing sharp_lq123p1jx31_timing = {
3782 .pixelclock = { 252750000, 252750000, 266604720 },
3783 .hactive = { 2400, 2400, 2400 },
3784 .hfront_porch = { 48, 48, 48 },
3785 .hback_porch = { 80, 80, 84 },
3786 .hsync_len = { 32, 32, 32 },
3787 .vactive = { 1600, 1600, 1600 },
3788 .vfront_porch = { 3, 3, 3 },
3789 .vback_porch = { 33, 33, 120 },
3790 .vsync_len = { 10, 10, 10 },
3791 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
3792 };
3793
3794 static const struct panel_desc sharp_lq123p1jx31 = {
3795 .timings = &sharp_lq123p1jx31_timing,
3796 .num_timings = 1,
3797 .bpc = 8,
3798 .size = {
3799 .width = 259,
3800 .height = 173,
3801 },
3802 .delay = {
3803 .prepare = 110,
3804 .enable = 50,
3805 .unprepare = 550,
3806 },
3807 };
3808
3809 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3810 { /* 50 Hz */
3811 .clock = 3000,
3812 .hdisplay = 240,
3813 .hsync_start = 240 + 58,
3814 .hsync_end = 240 + 58 + 1,
3815 .htotal = 240 + 58 + 1 + 1,
3816 .vdisplay = 160,
3817 .vsync_start = 160 + 24,
3818 .vsync_end = 160 + 24 + 10,
3819 .vtotal = 160 + 24 + 10 + 6,
3820 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3821 },
3822 { /* 60 Hz */
3823 .clock = 3000,
3824 .hdisplay = 240,
3825 .hsync_start = 240 + 8,
3826 .hsync_end = 240 + 8 + 1,
3827 .htotal = 240 + 8 + 1 + 1,
3828 .vdisplay = 160,
3829 .vsync_start = 160 + 24,
3830 .vsync_end = 160 + 24 + 10,
3831 .vtotal = 160 + 24 + 10 + 6,
3832 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3833 },
3834 };
3835
3836 static const struct panel_desc sharp_ls020b1dd01d = {
3837 .modes = sharp_ls020b1dd01d_modes,
3838 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3839 .bpc = 6,
3840 .size = {
3841 .width = 42,
3842 .height = 28,
3843 },
3844 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3845 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3846 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3847 | DRM_BUS_FLAG_SHARP_SIGNALS,
3848 };
3849
3850 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3851 .clock = 33300,
3852 .hdisplay = 800,
3853 .hsync_start = 800 + 1,
3854 .hsync_end = 800 + 1 + 64,
3855 .htotal = 800 + 1 + 64 + 64,
3856 .vdisplay = 480,
3857 .vsync_start = 480 + 1,
3858 .vsync_end = 480 + 1 + 23,
3859 .vtotal = 480 + 1 + 23 + 22,
3860 };
3861
3862 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3863 .modes = &shelly_sca07010_bfn_lnn_mode,
3864 .num_modes = 1,
3865 .size = {
3866 .width = 152,
3867 .height = 91,
3868 },
3869 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3870 };
3871
3872 static const struct drm_display_mode starry_kr070pe2t_mode = {
3873 .clock = 33000,
3874 .hdisplay = 800,
3875 .hsync_start = 800 + 209,
3876 .hsync_end = 800 + 209 + 1,
3877 .htotal = 800 + 209 + 1 + 45,
3878 .vdisplay = 480,
3879 .vsync_start = 480 + 22,
3880 .vsync_end = 480 + 22 + 1,
3881 .vtotal = 480 + 22 + 1 + 22,
3882 };
3883
3884 static const struct panel_desc starry_kr070pe2t = {
3885 .modes = &starry_kr070pe2t_mode,
3886 .num_modes = 1,
3887 .bpc = 8,
3888 .size = {
3889 .width = 152,
3890 .height = 86,
3891 },
3892 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3893 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3894 .connector_type = DRM_MODE_CONNECTOR_DPI,
3895 };
3896
3897 static const struct drm_display_mode starry_kr122ea0sra_mode = {
3898 .clock = 147000,
3899 .hdisplay = 1920,
3900 .hsync_start = 1920 + 16,
3901 .hsync_end = 1920 + 16 + 16,
3902 .htotal = 1920 + 16 + 16 + 32,
3903 .vdisplay = 1200,
3904 .vsync_start = 1200 + 15,
3905 .vsync_end = 1200 + 15 + 2,
3906 .vtotal = 1200 + 15 + 2 + 18,
3907 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3908 };
3909
3910 static const struct panel_desc starry_kr122ea0sra = {
3911 .modes = &starry_kr122ea0sra_mode,
3912 .num_modes = 1,
3913 .size = {
3914 .width = 263,
3915 .height = 164,
3916 },
3917 .delay = {
3918 .prepare = 10 + 200,
3919 .enable = 50,
3920 .unprepare = 10 + 500,
3921 },
3922 };
3923
3924 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3925 .clock = 30000,
3926 .hdisplay = 800,
3927 .hsync_start = 800 + 39,
3928 .hsync_end = 800 + 39 + 47,
3929 .htotal = 800 + 39 + 47 + 39,
3930 .vdisplay = 480,
3931 .vsync_start = 480 + 13,
3932 .vsync_end = 480 + 13 + 2,
3933 .vtotal = 480 + 13 + 2 + 29,
3934 };
3935
3936 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3937 .modes = &tfc_s9700rtwv43tr_01b_mode,
3938 .num_modes = 1,
3939 .bpc = 8,
3940 .size = {
3941 .width = 155,
3942 .height = 90,
3943 },
3944 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3945 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3946 };
3947
3948 static const struct display_timing tianma_tm070jdhg30_timing = {
3949 .pixelclock = { 62600000, 68200000, 78100000 },
3950 .hactive = { 1280, 1280, 1280 },
3951 .hfront_porch = { 15, 64, 159 },
3952 .hback_porch = { 5, 5, 5 },
3953 .hsync_len = { 1, 1, 256 },
3954 .vactive = { 800, 800, 800 },
3955 .vfront_porch = { 3, 40, 99 },
3956 .vback_porch = { 2, 2, 2 },
3957 .vsync_len = { 1, 1, 128 },
3958 .flags = DISPLAY_FLAGS_DE_HIGH,
3959 };
3960
3961 static const struct panel_desc tianma_tm070jdhg30 = {
3962 .timings = &tianma_tm070jdhg30_timing,
3963 .num_timings = 1,
3964 .bpc = 8,
3965 .size = {
3966 .width = 151,
3967 .height = 95,
3968 },
3969 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3970 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3971 };
3972
3973 static const struct panel_desc tianma_tm070jvhg33 = {
3974 .timings = &tianma_tm070jdhg30_timing,
3975 .num_timings = 1,
3976 .bpc = 8,
3977 .size = {
3978 .width = 150,
3979 .height = 94,
3980 },
3981 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3982 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3983 };
3984
3985 static const struct display_timing tianma_tm070rvhg71_timing = {
3986 .pixelclock = { 27700000, 29200000, 39600000 },
3987 .hactive = { 800, 800, 800 },
3988 .hfront_porch = { 12, 40, 212 },
3989 .hback_porch = { 88, 88, 88 },
3990 .hsync_len = { 1, 1, 40 },
3991 .vactive = { 480, 480, 480 },
3992 .vfront_porch = { 1, 13, 88 },
3993 .vback_porch = { 32, 32, 32 },
3994 .vsync_len = { 1, 1, 3 },
3995 .flags = DISPLAY_FLAGS_DE_HIGH,
3996 };
3997
3998 static const struct panel_desc tianma_tm070rvhg71 = {
3999 .timings = &tianma_tm070rvhg71_timing,
4000 .num_timings = 1,
4001 .bpc = 8,
4002 .size = {
4003 .width = 154,
4004 .height = 86,
4005 },
4006 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4007 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4008 };
4009
4010 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
4011 {
4012 .clock = 10000,
4013 .hdisplay = 320,
4014 .hsync_start = 320 + 50,
4015 .hsync_end = 320 + 50 + 6,
4016 .htotal = 320 + 50 + 6 + 38,
4017 .vdisplay = 240,
4018 .vsync_start = 240 + 3,
4019 .vsync_end = 240 + 3 + 1,
4020 .vtotal = 240 + 3 + 1 + 17,
4021 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4022 },
4023 };
4024
4025 static const struct panel_desc ti_nspire_cx_lcd_panel = {
4026 .modes = ti_nspire_cx_lcd_mode,
4027 .num_modes = 1,
4028 .bpc = 8,
4029 .size = {
4030 .width = 65,
4031 .height = 49,
4032 },
4033 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4034 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
4035 };
4036
4037 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
4038 {
4039 .clock = 10000,
4040 .hdisplay = 320,
4041 .hsync_start = 320 + 6,
4042 .hsync_end = 320 + 6 + 6,
4043 .htotal = 320 + 6 + 6 + 6,
4044 .vdisplay = 240,
4045 .vsync_start = 240 + 0,
4046 .vsync_end = 240 + 0 + 1,
4047 .vtotal = 240 + 0 + 1 + 0,
4048 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4049 },
4050 };
4051
4052 static const struct panel_desc ti_nspire_classic_lcd_panel = {
4053 .modes = ti_nspire_classic_lcd_mode,
4054 .num_modes = 1,
4055 /* The grayscale panel has 8 bit for the color .. Y (black) */
4056 .bpc = 8,
4057 .size = {
4058 .width = 71,
4059 .height = 53,
4060 },
4061 /* This is the grayscale bus format */
4062 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
4063 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4064 };
4065
4066 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
4067 .clock = 79500,
4068 .hdisplay = 1280,
4069 .hsync_start = 1280 + 192,
4070 .hsync_end = 1280 + 192 + 128,
4071 .htotal = 1280 + 192 + 128 + 64,
4072 .vdisplay = 768,
4073 .vsync_start = 768 + 20,
4074 .vsync_end = 768 + 20 + 7,
4075 .vtotal = 768 + 20 + 7 + 3,
4076 };
4077
4078 static const struct panel_desc toshiba_lt089ac29000 = {
4079 .modes = &toshiba_lt089ac29000_mode,
4080 .num_modes = 1,
4081 .size = {
4082 .width = 194,
4083 .height = 116,
4084 },
4085 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4086 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4087 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4088 };
4089
4090 static const struct drm_display_mode tpk_f07a_0102_mode = {
4091 .clock = 33260,
4092 .hdisplay = 800,
4093 .hsync_start = 800 + 40,
4094 .hsync_end = 800 + 40 + 128,
4095 .htotal = 800 + 40 + 128 + 88,
4096 .vdisplay = 480,
4097 .vsync_start = 480 + 10,
4098 .vsync_end = 480 + 10 + 2,
4099 .vtotal = 480 + 10 + 2 + 33,
4100 };
4101
4102 static const struct panel_desc tpk_f07a_0102 = {
4103 .modes = &tpk_f07a_0102_mode,
4104 .num_modes = 1,
4105 .size = {
4106 .width = 152,
4107 .height = 91,
4108 },
4109 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
4110 };
4111
4112 static const struct drm_display_mode tpk_f10a_0102_mode = {
4113 .clock = 45000,
4114 .hdisplay = 1024,
4115 .hsync_start = 1024 + 176,
4116 .hsync_end = 1024 + 176 + 5,
4117 .htotal = 1024 + 176 + 5 + 88,
4118 .vdisplay = 600,
4119 .vsync_start = 600 + 20,
4120 .vsync_end = 600 + 20 + 5,
4121 .vtotal = 600 + 20 + 5 + 25,
4122 };
4123
4124 static const struct panel_desc tpk_f10a_0102 = {
4125 .modes = &tpk_f10a_0102_mode,
4126 .num_modes = 1,
4127 .size = {
4128 .width = 223,
4129 .height = 125,
4130 },
4131 };
4132
4133 static const struct display_timing urt_umsh_8596md_timing = {
4134 .pixelclock = { 33260000, 33260000, 33260000 },
4135 .hactive = { 800, 800, 800 },
4136 .hfront_porch = { 41, 41, 41 },
4137 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
4138 .hsync_len = { 71, 128, 128 },
4139 .vactive = { 480, 480, 480 },
4140 .vfront_porch = { 10, 10, 10 },
4141 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
4142 .vsync_len = { 2, 2, 2 },
4143 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
4144 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4145 };
4146
4147 static const struct panel_desc urt_umsh_8596md_lvds = {
4148 .timings = &urt_umsh_8596md_timing,
4149 .num_timings = 1,
4150 .bpc = 6,
4151 .size = {
4152 .width = 152,
4153 .height = 91,
4154 },
4155 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4156 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4157 };
4158
4159 static const struct panel_desc urt_umsh_8596md_parallel = {
4160 .timings = &urt_umsh_8596md_timing,
4161 .num_timings = 1,
4162 .bpc = 6,
4163 .size = {
4164 .width = 152,
4165 .height = 91,
4166 },
4167 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4168 };
4169
4170 static const struct drm_display_mode vl050_8048nt_c01_mode = {
4171 .clock = 33333,
4172 .hdisplay = 800,
4173 .hsync_start = 800 + 210,
4174 .hsync_end = 800 + 210 + 20,
4175 .htotal = 800 + 210 + 20 + 46,
4176 .vdisplay = 480,
4177 .vsync_start = 480 + 22,
4178 .vsync_end = 480 + 22 + 10,
4179 .vtotal = 480 + 22 + 10 + 23,
4180 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4181 };
4182
4183 static const struct panel_desc vl050_8048nt_c01 = {
4184 .modes = &vl050_8048nt_c01_mode,
4185 .num_modes = 1,
4186 .bpc = 8,
4187 .size = {
4188 .width = 120,
4189 .height = 76,
4190 },
4191 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4192 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4193 };
4194
4195 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4196 .clock = 6410,
4197 .hdisplay = 320,
4198 .hsync_start = 320 + 20,
4199 .hsync_end = 320 + 20 + 30,
4200 .htotal = 320 + 20 + 30 + 38,
4201 .vdisplay = 240,
4202 .vsync_start = 240 + 4,
4203 .vsync_end = 240 + 4 + 3,
4204 .vtotal = 240 + 4 + 3 + 15,
4205 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4206 };
4207
4208 static const struct panel_desc winstar_wf35ltiacd = {
4209 .modes = &winstar_wf35ltiacd_mode,
4210 .num_modes = 1,
4211 .bpc = 8,
4212 .size = {
4213 .width = 70,
4214 .height = 53,
4215 },
4216 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4217 };
4218
4219 static const struct drm_display_mode arm_rtsm_mode[] = {
4220 {
4221 .clock = 65000,
4222 .hdisplay = 1024,
4223 .hsync_start = 1024 + 24,
4224 .hsync_end = 1024 + 24 + 136,
4225 .htotal = 1024 + 24 + 136 + 160,
4226 .vdisplay = 768,
4227 .vsync_start = 768 + 3,
4228 .vsync_end = 768 + 3 + 6,
4229 .vtotal = 768 + 3 + 6 + 29,
4230 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4231 },
4232 };
4233
4234 static const struct panel_desc arm_rtsm = {
4235 .modes = arm_rtsm_mode,
4236 .num_modes = 1,
4237 .bpc = 8,
4238 .size = {
4239 .width = 400,
4240 .height = 300,
4241 },
4242 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4243 };
4244
4245 static const struct of_device_id platform_of_match[] = {
4246 {
4247 .compatible = "simple-panel",
4248 .data = NULL,
4249 }, {
4250 .compatible = "ampire,am-1280800n3tzqw-t00h",
4251 .data = &ire_am_1280800n3tzqw_t00h,
4252 }, {
4253 .compatible = "ampire,am-480272h3tmqw-t01h",
4254 .data = &ire_am_480272h3tmqw_t01h,
4255 }, {
4256 .compatible = "ampire,am800480r3tmqwa1h",
4257 .data = &ire_am800480r3tmqwa1h,
4258 }, {
4259 .compatible = "arm,rtsm-display",
4260 .data = &arm_rtsm,
4261 }, {
4262 .compatible = "armadeus,st0700-adapt",
4263 .data = &armadeus_st0700_adapt,
4264 }, {
4265 .compatible = "auo,b101aw03",
4266 .data = &auo_b101aw03,
4267 }, {
4268 .compatible = "auo,b101ean01",
4269 .data = &auo_b101ean01,
4270 }, {
4271 .compatible = "auo,b101xtn01",
4272 .data = &auo_b101xtn01,
4273 }, {
4274 .compatible = "auo,b116xa01",
4275 .data = &auo_b116xak01,
4276 }, {
4277 .compatible = "auo,b116xw03",
4278 .data = &auo_b116xw03,
4279 }, {
4280 .compatible = "auo,b133htn01",
4281 .data = &auo_b133htn01,
4282 }, {
4283 .compatible = "auo,b133xtn01",
4284 .data = &auo_b133xtn01,
4285 }, {
4286 .compatible = "auo,g070vvn01",
4287 .data = &auo_g070vvn01,
4288 }, {
4289 .compatible = "auo,g101evn010",
4290 .data = &auo_g101evn010,
4291 }, {
4292 .compatible = "auo,g104sn02",
4293 .data = &auo_g104sn02,
4294 }, {
4295 .compatible = "auo,g121ean01",
4296 .data = &auo_g121ean01,
4297 }, {
4298 .compatible = "auo,g133han01",
4299 .data = &auo_g133han01,
4300 }, {
4301 .compatible = "auo,g156xtn01",
4302 .data = &auo_g156xtn01,
4303 }, {
4304 .compatible = "auo,g185han01",
4305 .data = &auo_g185han01,
4306 }, {
4307 .compatible = "auo,g190ean01",
4308 .data = &auo_g190ean01,
4309 }, {
4310 .compatible = "auo,p320hvn03",
4311 .data = &auo_p320hvn03,
4312 }, {
4313 .compatible = "auo,t215hvn01",
4314 .data = &auo_t215hvn01,
4315 }, {
4316 .compatible = "avic,tm070ddh03",
4317 .data = &avic_tm070ddh03,
4318 }, {
4319 .compatible = "bananapi,s070wv20-ct16",
4320 .data = &bananapi_s070wv20_ct16,
4321 }, {
4322 .compatible = "boe,hv070wsa-100",
4323 .data = &boe_hv070wsa
4324 }, {
4325 .compatible = "boe,nv101wxmn51",
4326 .data = &boe_nv101wxmn51,
4327 }, {
4328 .compatible = "boe,nv133fhm-n61",
4329 .data = &boe_nv133fhm_n61,
4330 }, {
4331 .compatible = "boe,nv133fhm-n62",
4332 .data = &boe_nv133fhm_n61,
4333 }, {
4334 .compatible = "boe,nv140fhmn49",
4335 .data = &boe_nv140fhmn49,
4336 }, {
4337 .compatible = "cdtech,s043wq26h-ct7",
4338 .data = &cdtech_s043wq26h_ct7,
4339 }, {
4340 .compatible = "cdtech,s070pws19hp-fc21",
4341 .data = &cdtech_s070pws19hp_fc21,
4342 }, {
4343 .compatible = "cdtech,s070swv29hg-dc44",
4344 .data = &cdtech_s070swv29hg_dc44,
4345 }, {
4346 .compatible = "cdtech,s070wv95-ct16",
4347 .data = &cdtech_s070wv95_ct16,
4348 }, {
4349 .compatible = "chefree,ch101olhlwh-002",
4350 .data = &chefree_ch101olhlwh_002,
4351 }, {
4352 .compatible = "chunghwa,claa070wp03xg",
4353 .data = &chunghwa_claa070wp03xg,
4354 }, {
4355 .compatible = "chunghwa,claa101wa01a",
4356 .data = &chunghwa_claa101wa01a
4357 }, {
4358 .compatible = "chunghwa,claa101wb01",
4359 .data = &chunghwa_claa101wb01
4360 }, {
4361 .compatible = "dataimage,scf0700c48ggu18",
4362 .data = &dataimage_scf0700c48ggu18,
4363 }, {
4364 .compatible = "dlc,dlc0700yzg-1",
4365 .data = &dlc_dlc0700yzg_1,
4366 }, {
4367 .compatible = "dlc,dlc1010gig",
4368 .data = &dlc_dlc1010gig,
4369 }, {
4370 .compatible = "edt,et035012dm6",
4371 .data = &edt_et035012dm6,
4372 }, {
4373 .compatible = "edt,etm043080dh6gp",
4374 .data = &edt_etm043080dh6gp,
4375 }, {
4376 .compatible = "edt,etm0430g0dh6",
4377 .data = &edt_etm0430g0dh6,
4378 }, {
4379 .compatible = "edt,et057090dhu",
4380 .data = &edt_et057090dhu,
4381 }, {
4382 .compatible = "edt,et070080dh6",
4383 .data = &edt_etm0700g0dh6,
4384 }, {
4385 .compatible = "edt,etm0700g0dh6",
4386 .data = &edt_etm0700g0dh6,
4387 }, {
4388 .compatible = "edt,etm0700g0bdh6",
4389 .data = &edt_etm0700g0bdh6,
4390 }, {
4391 .compatible = "edt,etm0700g0edh6",
4392 .data = &edt_etm0700g0bdh6,
4393 }, {
4394 .compatible = "evervision,vgg804821",
4395 .data = &evervision_vgg804821,
4396 }, {
4397 .compatible = "foxlink,fl500wvr00-a0t",
4398 .data = &foxlink_fl500wvr00_a0t,
4399 }, {
4400 .compatible = "frida,frd350h54004",
4401 .data = &frida_frd350h54004,
4402 }, {
4403 .compatible = "friendlyarm,hd702e",
4404 .data = &friendlyarm_hd702e,
4405 }, {
4406 .compatible = "giantplus,gpg482739qs5",
4407 .data = &giantplus_gpg482739qs5
4408 }, {
4409 .compatible = "giantplus,gpm940b0",
4410 .data = &giantplus_gpm940b0,
4411 }, {
4412 .compatible = "hannstar,hsd070pww1",
4413 .data = &hannstar_hsd070pww1,
4414 }, {
4415 .compatible = "hannstar,hsd100pxn1",
4416 .data = &hannstar_hsd100pxn1,
4417 }, {
4418 .compatible = "hit,tx23d38vm0caa",
4419 .data = &hitachi_tx23d38vm0caa
4420 }, {
4421 .compatible = "innolux,at043tn24",
4422 .data = &innolux_at043tn24,
4423 }, {
4424 .compatible = "innolux,at070tn92",
4425 .data = &innolux_at070tn92,
4426 }, {
4427 .compatible = "innolux,g070y2-l01",
4428 .data = &innolux_g070y2_l01,
4429 }, {
4430 .compatible = "innolux,g101ice-l01",
4431 .data = &innolux_g101ice_l01
4432 }, {
4433 .compatible = "innolux,g121i1-l01",
4434 .data = &innolux_g121i1_l01
4435 }, {
4436 .compatible = "innolux,g121x1-l03",
4437 .data = &innolux_g121x1_l03,
4438 }, {
4439 .compatible = "innolux,n116bge",
4440 .data = &innolux_n116bge,
4441 }, {
4442 .compatible = "innolux,n156bge-l21",
4443 .data = &innolux_n156bge_l21,
4444 }, {
4445 .compatible = "innolux,p120zdg-bf1",
4446 .data = &innolux_p120zdg_bf1,
4447 }, {
4448 .compatible = "innolux,zj070na-01p",
4449 .data = &innolux_zj070na_01p,
4450 }, {
4451 .compatible = "ivo,m133nwf4-r0",
4452 .data = &ivo_m133nwf4_r0,
4453 }, {
4454 .compatible = "kingdisplay,kd116n21-30nv-a010",
4455 .data = &kingdisplay_kd116n21_30nv_a010,
4456 }, {
4457 .compatible = "koe,tx14d24vm1bpa",
4458 .data = &koe_tx14d24vm1bpa,
4459 }, {
4460 .compatible = "koe,tx26d202vm0bwa",
4461 .data = &koe_tx26d202vm0bwa,
4462 }, {
4463 .compatible = "koe,tx31d200vm0baa",
4464 .data = &koe_tx31d200vm0baa,
4465 }, {
4466 .compatible = "kyo,tcg121xglp",
4467 .data = &kyo_tcg121xglp,
4468 }, {
4469 .compatible = "lemaker,bl035-rgb-002",
4470 .data = &lemaker_bl035_rgb_002,
4471 }, {
4472 .compatible = "lg,lb070wv8",
4473 .data = &lg_lb070wv8,
4474 }, {
4475 .compatible = "lg,lp079qx1-sp0v",
4476 .data = &lg_lp079qx1_sp0v,
4477 }, {
4478 .compatible = "lg,lp097qx1-spa1",
4479 .data = &lg_lp097qx1_spa1,
4480 }, {
4481 .compatible = "lg,lp120up1",
4482 .data = &lg_lp120up1,
4483 }, {
4484 .compatible = "lg,lp129qe",
4485 .data = &lg_lp129qe,
4486 }, {
4487 .compatible = "logicpd,type28",
4488 .data = &logicpd_type_28,
4489 }, {
4490 .compatible = "logictechno,lt161010-2nhc",
4491 .data = &logictechno_lt161010_2nh,
4492 }, {
4493 .compatible = "logictechno,lt161010-2nhr",
4494 .data = &logictechno_lt161010_2nh,
4495 }, {
4496 .compatible = "logictechno,lt170410-2whc",
4497 .data = &logictechno_lt170410_2whc,
4498 }, {
4499 .compatible = "mitsubishi,aa070mc01-ca1",
4500 .data = &mitsubishi_aa070mc01,
4501 }, {
4502 .compatible = "nec,nl12880bc20-05",
4503 .data = &nec_nl12880bc20_05,
4504 }, {
4505 .compatible = "nec,nl4827hc19-05b",
4506 .data = &nec_nl4827hc19_05b,
4507 }, {
4508 .compatible = "netron-dy,e231732",
4509 .data = &netron_dy_e231732,
4510 }, {
4511 .compatible = "neweast,wjfh116008a",
4512 .data = &neweast_wjfh116008a,
4513 }, {
4514 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4515 .data = &newhaven_nhd_43_480272ef_atxl,
4516 }, {
4517 .compatible = "nlt,nl192108ac18-02d",
4518 .data = &nlt_nl192108ac18_02d,
4519 }, {
4520 .compatible = "nvd,9128",
4521 .data = &nvd_9128,
4522 }, {
4523 .compatible = "okaya,rs800480t-7x0gp",
4524 .data = &okaya_rs800480t_7x0gp,
4525 }, {
4526 .compatible = "olimex,lcd-olinuxino-43-ts",
4527 .data = &olimex_lcd_olinuxino_43ts,
4528 }, {
4529 .compatible = "ontat,yx700wv03",
4530 .data = &ontat_yx700wv03,
4531 }, {
4532 .compatible = "ortustech,com37h3m05dtc",
4533 .data = &ortustech_com37h3m,
4534 }, {
4535 .compatible = "ortustech,com37h3m99dtc",
4536 .data = &ortustech_com37h3m,
4537 }, {
4538 .compatible = "ortustech,com43h4m85ulc",
4539 .data = &ortustech_com43h4m85ulc,
4540 }, {
4541 .compatible = "osddisplays,osd070t1718-19ts",
4542 .data = &osddisplays_osd070t1718_19ts,
4543 }, {
4544 .compatible = "pda,91-00156-a0",
4545 .data = &pda_91_00156_a0,
4546 }, {
4547 .compatible = "powertip,ph800480t013-idf02",
4548 .data = &powertip_ph800480t013_idf02,
4549 }, {
4550 .compatible = "qiaodian,qd43003c0-40",
4551 .data = &qd43003c0_40,
4552 }, {
4553 .compatible = "rocktech,rk070er9427",
4554 .data = &rocktech_rk070er9427,
4555 }, {
4556 .compatible = "rocktech,rk101ii01d-ct",
4557 .data = &rocktech_rk101ii01d_ct,
4558 }, {
4559 .compatible = "samsung,lsn122dl01-c01",
4560 .data = &samsung_lsn122dl01_c01,
4561 }, {
4562 .compatible = "samsung,ltn101nt05",
4563 .data = &samsung_ltn101nt05,
4564 }, {
4565 .compatible = "samsung,ltn140at29-301",
4566 .data = &samsung_ltn140at29_301,
4567 }, {
4568 .compatible = "satoz,sat050at40h12r2",
4569 .data = &satoz_sat050at40h12r2,
4570 }, {
4571 .compatible = "sharp,ld-d5116z01b",
4572 .data = &sharp_ld_d5116z01b,
4573 }, {
4574 .compatible = "sharp,lq035q7db03",
4575 .data = &sharp_lq035q7db03,
4576 }, {
4577 .compatible = "sharp,lq070y3dg3b",
4578 .data = &sharp_lq070y3dg3b,
4579 }, {
4580 .compatible = "sharp,lq101k1ly04",
4581 .data = &sharp_lq101k1ly04,
4582 }, {
4583 .compatible = "sharp,lq123p1jx31",
4584 .data = &sharp_lq123p1jx31,
4585 }, {
4586 .compatible = "sharp,ls020b1dd01d",
4587 .data = &sharp_ls020b1dd01d,
4588 }, {
4589 .compatible = "shelly,sca07010-bfn-lnn",
4590 .data = &shelly_sca07010_bfn_lnn,
4591 }, {
4592 .compatible = "starry,kr070pe2t",
4593 .data = &starry_kr070pe2t,
4594 }, {
4595 .compatible = "starry,kr122ea0sra",
4596 .data = &starry_kr122ea0sra,
4597 }, {
4598 .compatible = "tfc,s9700rtwv43tr-01b",
4599 .data = &tfc_s9700rtwv43tr_01b,
4600 }, {
4601 .compatible = "tianma,tm070jdhg30",
4602 .data = &tianma_tm070jdhg30,
4603 }, {
4604 .compatible = "tianma,tm070jvhg33",
4605 .data = &tianma_tm070jvhg33,
4606 }, {
4607 .compatible = "tianma,tm070rvhg71",
4608 .data = &tianma_tm070rvhg71,
4609 }, {
4610 .compatible = "ti,nspire-cx-lcd-panel",
4611 .data = &ti_nspire_cx_lcd_panel,
4612 }, {
4613 .compatible = "ti,nspire-classic-lcd-panel",
4614 .data = &ti_nspire_classic_lcd_panel,
4615 }, {
4616 .compatible = "toshiba,lt089ac29000",
4617 .data = &toshiba_lt089ac29000,
4618 }, {
4619 .compatible = "tpk,f07a-0102",
4620 .data = &tpk_f07a_0102,
4621 }, {
4622 .compatible = "tpk,f10a-0102",
4623 .data = &tpk_f10a_0102,
4624 }, {
4625 .compatible = "urt,umsh-8596md-t",
4626 .data = &urt_umsh_8596md_parallel,
4627 }, {
4628 .compatible = "urt,umsh-8596md-1t",
4629 .data = &urt_umsh_8596md_parallel,
4630 }, {
4631 .compatible = "urt,umsh-8596md-7t",
4632 .data = &urt_umsh_8596md_parallel,
4633 }, {
4634 .compatible = "urt,umsh-8596md-11t",
4635 .data = &urt_umsh_8596md_lvds,
4636 }, {
4637 .compatible = "urt,umsh-8596md-19t",
4638 .data = &urt_umsh_8596md_lvds,
4639 }, {
4640 .compatible = "urt,umsh-8596md-20t",
4641 .data = &urt_umsh_8596md_parallel,
4642 }, {
4643 .compatible = "vxt,vl050-8048nt-c01",
4644 .data = &vl050_8048nt_c01,
4645 }, {
4646 .compatible = "winstar,wf35ltiacd",
4647 .data = &winstar_wf35ltiacd,
4648 }, {
4649 /* Must be the last entry */
4650 .compatible = "panel-dpi",
4651 .data = &panel_dpi,
4652 }, {
4653 /* sentinel */
4654 }
4655 };
4656 MODULE_DEVICE_TABLE(of, platform_of_match);
4657
of_child_node_is_present(const struct device_node * node,const char * name)4658 static bool of_child_node_is_present(const struct device_node *node,
4659 const char *name)
4660 {
4661 struct device_node *child;
4662
4663 child = of_get_child_by_name(node, name);
4664 of_node_put(child);
4665
4666 return !!child;
4667 }
4668
panel_simple_of_get_desc_data(struct device * dev,struct panel_desc * desc)4669 static int panel_simple_of_get_desc_data(struct device *dev,
4670 struct panel_desc *desc)
4671 {
4672 struct device_node *np = dev->of_node;
4673 u32 bus_flags;
4674 const void *data;
4675 int len;
4676 int err;
4677
4678 if (of_child_node_is_present(np, "display-timings")) {
4679 struct drm_display_mode *mode;
4680
4681 mode = devm_kzalloc(dev, sizeof(*mode), GFP_KERNEL);
4682 if (!mode)
4683 return -ENOMEM;
4684
4685 if (!of_get_drm_display_mode(np, mode, &bus_flags,
4686 OF_USE_NATIVE_MODE)) {
4687 desc->modes = mode;
4688 desc->num_modes = 1;
4689 desc->bus_flags = bus_flags;
4690 }
4691 } else if (of_child_node_is_present(np, "panel-timing")) {
4692 struct display_timing *timing;
4693 struct videomode vm;
4694
4695 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
4696 if (!timing)
4697 return -ENOMEM;
4698
4699 if (!of_get_display_timing(np, "panel-timing", timing)) {
4700 desc->timings = timing;
4701 desc->num_timings = 1;
4702
4703 bus_flags = 0;
4704 vm.flags = timing->flags;
4705 drm_bus_flags_from_videomode(&vm, &bus_flags);
4706 desc->bus_flags = bus_flags;
4707 }
4708 }
4709
4710 if (desc->num_modes || desc->num_timings) {
4711 of_property_read_u32(np, "bpc", &desc->bpc);
4712 of_property_read_u32(np, "bus-format", &desc->bus_format);
4713 of_property_read_u32(np, "width-mm", &desc->size.width);
4714 of_property_read_u32(np, "height-mm", &desc->size.height);
4715 }
4716
4717 of_property_read_u32(np, "prepare-delay-ms", &desc->delay.prepare);
4718 of_property_read_u32(np, "enable-delay-ms", &desc->delay.enable);
4719 of_property_read_u32(np, "disable-delay-ms", &desc->delay.disable);
4720 of_property_read_u32(np, "unprepare-delay-ms", &desc->delay.unprepare);
4721 of_property_read_u32(np, "reset-delay-ms", &desc->delay.reset);
4722 of_property_read_u32(np, "init-delay-ms", &desc->delay.init);
4723
4724 data = of_get_property(np, "panel-init-sequence", &len);
4725 if (data) {
4726 desc->init_seq = devm_kzalloc(dev, sizeof(*desc->init_seq),
4727 GFP_KERNEL);
4728 if (!desc->init_seq)
4729 return -ENOMEM;
4730
4731 err = panel_simple_parse_cmd_seq(dev, data, len,
4732 desc->init_seq);
4733 if (err) {
4734 dev_err(dev, "failed to parse init sequence\n");
4735 return err;
4736 }
4737 }
4738
4739 data = of_get_property(np, "panel-exit-sequence", &len);
4740 if (data) {
4741 desc->exit_seq = devm_kzalloc(dev, sizeof(*desc->exit_seq),
4742 GFP_KERNEL);
4743 if (!desc->exit_seq)
4744 return -ENOMEM;
4745
4746 err = panel_simple_parse_cmd_seq(dev, data, len,
4747 desc->exit_seq);
4748 if (err) {
4749 dev_err(dev, "failed to parse exit sequence\n");
4750 return err;
4751 }
4752 }
4753
4754 return 0;
4755 }
4756
panel_simple_platform_probe(struct platform_device * pdev)4757 static int panel_simple_platform_probe(struct platform_device *pdev)
4758 {
4759 struct device *dev = &pdev->dev;
4760 const struct of_device_id *id;
4761 const struct panel_desc *desc;
4762 struct panel_desc *d;
4763 int err;
4764
4765 id = of_match_node(platform_of_match, pdev->dev.of_node);
4766 if (!id)
4767 return -ENODEV;
4768
4769 if (!id->data) {
4770 d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
4771 if (!d)
4772 return -ENOMEM;
4773
4774 err = panel_simple_of_get_desc_data(dev, d);
4775 if (err) {
4776 dev_err(dev, "failed to get desc data: %d\n", err);
4777 return err;
4778 }
4779 }
4780
4781 desc = id->data ? id->data : d;
4782
4783 return panel_simple_probe(&pdev->dev, desc);
4784 }
4785
panel_simple_platform_remove(struct platform_device * pdev)4786 static int panel_simple_platform_remove(struct platform_device *pdev)
4787 {
4788 return panel_simple_remove(&pdev->dev);
4789 }
4790
panel_simple_platform_shutdown(struct platform_device * pdev)4791 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4792 {
4793 panel_simple_shutdown(&pdev->dev);
4794 }
4795
4796 static struct platform_driver panel_simple_platform_driver = {
4797 .driver = {
4798 .name = "panel-simple",
4799 .of_match_table = platform_of_match,
4800 },
4801 .probe = panel_simple_platform_probe,
4802 .remove = panel_simple_platform_remove,
4803 .shutdown = panel_simple_platform_shutdown,
4804 };
4805
4806 struct panel_desc_dsi {
4807 struct panel_desc desc;
4808
4809 unsigned long flags;
4810 enum mipi_dsi_pixel_format format;
4811 unsigned int lanes;
4812 };
4813
4814 static const struct drm_display_mode auo_b080uan01_mode = {
4815 .clock = 154500,
4816 .hdisplay = 1200,
4817 .hsync_start = 1200 + 62,
4818 .hsync_end = 1200 + 62 + 4,
4819 .htotal = 1200 + 62 + 4 + 62,
4820 .vdisplay = 1920,
4821 .vsync_start = 1920 + 9,
4822 .vsync_end = 1920 + 9 + 2,
4823 .vtotal = 1920 + 9 + 2 + 8,
4824 };
4825
4826 static const struct panel_desc_dsi auo_b080uan01 = {
4827 .desc = {
4828 .modes = &auo_b080uan01_mode,
4829 .num_modes = 1,
4830 .bpc = 8,
4831 .size = {
4832 .width = 108,
4833 .height = 272,
4834 },
4835 .connector_type = DRM_MODE_CONNECTOR_DSI,
4836 },
4837 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4838 .format = MIPI_DSI_FMT_RGB888,
4839 .lanes = 4,
4840 };
4841
4842 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4843 .clock = 160000,
4844 .hdisplay = 1200,
4845 .hsync_start = 1200 + 120,
4846 .hsync_end = 1200 + 120 + 20,
4847 .htotal = 1200 + 120 + 20 + 21,
4848 .vdisplay = 1920,
4849 .vsync_start = 1920 + 21,
4850 .vsync_end = 1920 + 21 + 3,
4851 .vtotal = 1920 + 21 + 3 + 18,
4852 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4853 };
4854
4855 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4856 .desc = {
4857 .modes = &boe_tv080wum_nl0_mode,
4858 .num_modes = 1,
4859 .size = {
4860 .width = 107,
4861 .height = 172,
4862 },
4863 .connector_type = DRM_MODE_CONNECTOR_DSI,
4864 },
4865 .flags = MIPI_DSI_MODE_VIDEO |
4866 MIPI_DSI_MODE_VIDEO_BURST |
4867 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4868 .format = MIPI_DSI_FMT_RGB888,
4869 .lanes = 4,
4870 };
4871
4872 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4873 .clock = 71000,
4874 .hdisplay = 800,
4875 .hsync_start = 800 + 32,
4876 .hsync_end = 800 + 32 + 1,
4877 .htotal = 800 + 32 + 1 + 57,
4878 .vdisplay = 1280,
4879 .vsync_start = 1280 + 28,
4880 .vsync_end = 1280 + 28 + 1,
4881 .vtotal = 1280 + 28 + 1 + 14,
4882 };
4883
4884 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4885 .desc = {
4886 .modes = &lg_ld070wx3_sl01_mode,
4887 .num_modes = 1,
4888 .bpc = 8,
4889 .size = {
4890 .width = 94,
4891 .height = 151,
4892 },
4893 .connector_type = DRM_MODE_CONNECTOR_DSI,
4894 },
4895 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4896 .format = MIPI_DSI_FMT_RGB888,
4897 .lanes = 4,
4898 };
4899
4900 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4901 .clock = 67000,
4902 .hdisplay = 720,
4903 .hsync_start = 720 + 12,
4904 .hsync_end = 720 + 12 + 4,
4905 .htotal = 720 + 12 + 4 + 112,
4906 .vdisplay = 1280,
4907 .vsync_start = 1280 + 8,
4908 .vsync_end = 1280 + 8 + 4,
4909 .vtotal = 1280 + 8 + 4 + 12,
4910 };
4911
4912 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4913 .desc = {
4914 .modes = &lg_lh500wx1_sd03_mode,
4915 .num_modes = 1,
4916 .bpc = 8,
4917 .size = {
4918 .width = 62,
4919 .height = 110,
4920 },
4921 .connector_type = DRM_MODE_CONNECTOR_DSI,
4922 },
4923 .flags = MIPI_DSI_MODE_VIDEO,
4924 .format = MIPI_DSI_FMT_RGB888,
4925 .lanes = 4,
4926 };
4927
4928 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4929 .clock = 157200,
4930 .hdisplay = 1920,
4931 .hsync_start = 1920 + 154,
4932 .hsync_end = 1920 + 154 + 16,
4933 .htotal = 1920 + 154 + 16 + 32,
4934 .vdisplay = 1200,
4935 .vsync_start = 1200 + 17,
4936 .vsync_end = 1200 + 17 + 2,
4937 .vtotal = 1200 + 17 + 2 + 16,
4938 };
4939
4940 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4941 .desc = {
4942 .modes = &panasonic_vvx10f004b00_mode,
4943 .num_modes = 1,
4944 .bpc = 8,
4945 .size = {
4946 .width = 217,
4947 .height = 136,
4948 },
4949 .connector_type = DRM_MODE_CONNECTOR_DSI,
4950 },
4951 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4952 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4953 .format = MIPI_DSI_FMT_RGB888,
4954 .lanes = 4,
4955 };
4956
4957 static const struct drm_display_mode lg_acx467akm_7_mode = {
4958 .clock = 150000,
4959 .hdisplay = 1080,
4960 .hsync_start = 1080 + 2,
4961 .hsync_end = 1080 + 2 + 2,
4962 .htotal = 1080 + 2 + 2 + 2,
4963 .vdisplay = 1920,
4964 .vsync_start = 1920 + 2,
4965 .vsync_end = 1920 + 2 + 2,
4966 .vtotal = 1920 + 2 + 2 + 2,
4967 };
4968
4969 static const struct panel_desc_dsi lg_acx467akm_7 = {
4970 .desc = {
4971 .modes = &lg_acx467akm_7_mode,
4972 .num_modes = 1,
4973 .bpc = 8,
4974 .size = {
4975 .width = 62,
4976 .height = 110,
4977 },
4978 .connector_type = DRM_MODE_CONNECTOR_DSI,
4979 },
4980 .flags = 0,
4981 .format = MIPI_DSI_FMT_RGB888,
4982 .lanes = 4,
4983 };
4984
4985 static const struct drm_display_mode osd101t2045_53ts_mode = {
4986 .clock = 154500,
4987 .hdisplay = 1920,
4988 .hsync_start = 1920 + 112,
4989 .hsync_end = 1920 + 112 + 16,
4990 .htotal = 1920 + 112 + 16 + 32,
4991 .vdisplay = 1200,
4992 .vsync_start = 1200 + 16,
4993 .vsync_end = 1200 + 16 + 2,
4994 .vtotal = 1200 + 16 + 2 + 16,
4995 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4996 };
4997
4998 static const struct panel_desc_dsi osd101t2045_53ts = {
4999 .desc = {
5000 .modes = &osd101t2045_53ts_mode,
5001 .num_modes = 1,
5002 .bpc = 8,
5003 .size = {
5004 .width = 217,
5005 .height = 136,
5006 },
5007 .connector_type = DRM_MODE_CONNECTOR_DSI,
5008 },
5009 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
5010 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5011 MIPI_DSI_MODE_EOT_PACKET,
5012 .format = MIPI_DSI_FMT_RGB888,
5013 .lanes = 4,
5014 };
5015
5016 static const struct of_device_id dsi_of_match[] = {
5017 {
5018 .compatible = "simple-panel-dsi",
5019 .data = NULL,
5020 }, {
5021 .compatible = "auo,b080uan01",
5022 .data = &auo_b080uan01
5023 }, {
5024 .compatible = "boe,tv080wum-nl0",
5025 .data = &boe_tv080wum_nl0
5026 }, {
5027 .compatible = "lg,ld070wx3-sl01",
5028 .data = &lg_ld070wx3_sl01
5029 }, {
5030 .compatible = "lg,lh500wx1-sd03",
5031 .data = &lg_lh500wx1_sd03
5032 }, {
5033 .compatible = "panasonic,vvx10f004b00",
5034 .data = &panasonic_vvx10f004b00
5035 }, {
5036 .compatible = "lg,acx467akm-7",
5037 .data = &lg_acx467akm_7
5038 }, {
5039 .compatible = "osddisplays,osd101t2045-53ts",
5040 .data = &osd101t2045_53ts
5041 }, {
5042 /* sentinel */
5043 }
5044 };
5045 MODULE_DEVICE_TABLE(of, dsi_of_match);
5046
panel_simple_dsi_of_get_desc_data(struct device * dev,struct panel_desc_dsi * desc)5047 static int panel_simple_dsi_of_get_desc_data(struct device *dev,
5048 struct panel_desc_dsi *desc)
5049 {
5050 struct device_node *np = dev->of_node;
5051 u32 val;
5052 int err;
5053
5054 err = panel_simple_of_get_desc_data(dev, &desc->desc);
5055 if (err)
5056 return err;
5057
5058 if (!of_property_read_u32(np, "dsi,flags", &val))
5059 desc->flags = val;
5060 if (!of_property_read_u32(np, "dsi,format", &val))
5061 desc->format = val;
5062 if (!of_property_read_u32(np, "dsi,lanes", &val))
5063 desc->lanes = val;
5064
5065 return 0;
5066 }
5067
panel_simple_dsi_probe(struct mipi_dsi_device * dsi)5068 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
5069 {
5070 struct panel_simple *panel;
5071 struct device *dev = &dsi->dev;
5072 const struct panel_desc_dsi *desc;
5073 struct panel_desc_dsi *d;
5074 const struct of_device_id *id;
5075 int err;
5076
5077 id = of_match_node(dsi_of_match, dsi->dev.of_node);
5078 if (!id)
5079 return -ENODEV;
5080
5081 if (!id->data) {
5082 d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
5083 if (!d)
5084 return -ENOMEM;
5085
5086 err = panel_simple_dsi_of_get_desc_data(dev, d);
5087 if (err) {
5088 dev_err(dev, "failed to get desc data: %d\n", err);
5089 return err;
5090 }
5091 }
5092
5093 desc = id->data ? id->data : d;
5094
5095 err = panel_simple_probe(&dsi->dev, &desc->desc);
5096 if (err < 0)
5097 return err;
5098
5099 panel = dev_get_drvdata(dev);
5100 panel->dsi = dsi;
5101
5102 if (!panel->base.backlight) {
5103 struct backlight_properties props;
5104
5105 memset(&props, 0, sizeof(props));
5106 props.type = BACKLIGHT_RAW;
5107 props.brightness = 255;
5108 props.max_brightness = 255;
5109
5110 panel->base.backlight =
5111 devm_backlight_device_register(dev, "dcs-backlight",
5112 dev, panel, &dcs_bl_ops,
5113 &props);
5114 if (IS_ERR(panel->base.backlight)) {
5115 err = PTR_ERR(panel->base.backlight);
5116 dev_err(dev, "failed to register dcs backlight: %d\n",
5117 err);
5118 return err;
5119 }
5120 }
5121
5122 dsi->mode_flags = desc->flags;
5123 dsi->format = desc->format;
5124 dsi->lanes = desc->lanes;
5125
5126 err = mipi_dsi_attach(dsi);
5127 if (err) {
5128 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
5129
5130 drm_panel_remove(&panel->base);
5131 }
5132
5133 return err;
5134 }
5135
panel_simple_dsi_remove(struct mipi_dsi_device * dsi)5136 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
5137 {
5138 int err;
5139
5140 err = mipi_dsi_detach(dsi);
5141 if (err < 0)
5142 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
5143
5144 return panel_simple_remove(&dsi->dev);
5145 }
5146
panel_simple_dsi_shutdown(struct mipi_dsi_device * dsi)5147 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
5148 {
5149 panel_simple_shutdown(&dsi->dev);
5150 }
5151
5152 static struct mipi_dsi_driver panel_simple_dsi_driver = {
5153 .driver = {
5154 .name = "panel-simple-dsi",
5155 .of_match_table = dsi_of_match,
5156 },
5157 .probe = panel_simple_dsi_probe,
5158 .remove = panel_simple_dsi_remove,
5159 .shutdown = panel_simple_dsi_shutdown,
5160 };
5161
panel_simple_spi_read(struct device * dev,const u8 cmd,u8 * data)5162 static int panel_simple_spi_read(struct device *dev, const u8 cmd, u8 *data)
5163 {
5164 return 0;
5165 }
5166
panel_simple_spi_write_word(struct device * dev,u16 data)5167 static int panel_simple_spi_write_word(struct device *dev, u16 data)
5168 {
5169 struct spi_device *spi = to_spi_device(dev);
5170 struct spi_transfer xfer = {
5171 .len = 2,
5172 .tx_buf = &data,
5173 };
5174 struct spi_message msg;
5175
5176 spi_message_init(&msg);
5177 spi_message_add_tail(&xfer, &msg);
5178
5179 return spi_sync(spi, &msg);
5180 }
5181
panel_simple_spi_write(struct device * dev,const u8 * data,size_t len,u8 type)5182 static int panel_simple_spi_write(struct device *dev, const u8 *data, size_t len, u8 type)
5183 {
5184 int ret = 0;
5185 int i;
5186 u16 mask = type ? 0x100 : 0;
5187
5188 for (i = 0; i < len; i++) {
5189 ret = panel_simple_spi_write_word(dev, *data | mask);
5190 if (ret) {
5191 dev_err(dev, "failed to write spi seq: %*ph\n", (int)len, data);
5192 return ret;
5193 }
5194 data++;
5195 }
5196
5197 return ret;
5198 }
5199
5200 static const struct of_device_id panel_simple_spi_of_match[] = {
5201 { .compatible = "simple-panel-spi", .data = NULL },
5202 { /* sentinel */ }
5203 };
5204 MODULE_DEVICE_TABLE(of, panel_simple_spi_of_match);
5205
panel_simple_spi_probe(struct spi_device * spi)5206 static int panel_simple_spi_probe(struct spi_device *spi)
5207 {
5208 struct device *dev = &spi->dev;
5209 const struct of_device_id *id;
5210 const struct panel_desc *desc;
5211 struct panel_desc *d;
5212 int ret;
5213
5214 id = of_match_node(panel_simple_spi_of_match, dev->of_node);
5215 if (!id)
5216 return -ENODEV;
5217
5218 if (!id->data) {
5219 d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
5220 if (!d)
5221 return -ENOMEM;
5222
5223 ret = panel_simple_of_get_desc_data(dev, d);
5224 if (ret) {
5225 dev_err(dev, "failed to get desc data: %d\n", ret);
5226 return ret;
5227 }
5228
5229 d->spi_write = panel_simple_spi_write;
5230 d->spi_read = panel_simple_spi_read;
5231 d->cmd_type = CMD_TYPE_SPI;
5232 }
5233 desc = id->data ? id->data : d;
5234
5235 /*
5236 * Set spi to 3 lines and 9bits/word mode.
5237 */
5238 spi->bits_per_word = 9;
5239 spi->mode = SPI_MODE_3;
5240 ret = spi_setup(spi);
5241 if (ret < 0) {
5242 dev_err(dev, "spi setup failed.\n");
5243 return ret;
5244 }
5245
5246 return panel_simple_probe(dev, desc);
5247 }
5248
panel_simple_spi_remove(struct spi_device * spi)5249 static int panel_simple_spi_remove(struct spi_device *spi)
5250 {
5251 return panel_simple_remove(&spi->dev);
5252 }
5253
panel_simple_spi_shutdown(struct spi_device * spi)5254 static void panel_simple_spi_shutdown(struct spi_device *spi)
5255 {
5256 panel_simple_shutdown(&spi->dev);
5257 }
5258
5259 static struct spi_driver panel_simple_spi_driver = {
5260 .driver = {
5261 .name = "panel-simple-spi",
5262 .of_match_table = panel_simple_spi_of_match,
5263 },
5264 .probe = panel_simple_spi_probe,
5265 .remove = panel_simple_spi_remove,
5266 .shutdown = panel_simple_spi_shutdown,
5267 };
5268
panel_simple_init(void)5269 static int __init panel_simple_init(void)
5270 {
5271 int err;
5272
5273 err = platform_driver_register(&panel_simple_platform_driver);
5274 if (err < 0)
5275 return err;
5276
5277 if (IS_ENABLED(CONFIG_SPI_MASTER)) {
5278 err = spi_register_driver(&panel_simple_spi_driver);
5279 if (err < 0)
5280 return err;
5281 }
5282
5283 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
5284 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
5285 if (err < 0)
5286 return err;
5287 }
5288
5289 return 0;
5290 }
5291 module_init(panel_simple_init);
5292
panel_simple_exit(void)5293 static void __exit panel_simple_exit(void)
5294 {
5295 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
5296 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
5297
5298 if (IS_ENABLED(CONFIG_SPI_MASTER))
5299 spi_unregister_driver(&panel_simple_spi_driver);
5300
5301 platform_driver_unregister(&panel_simple_platform_driver);
5302 }
5303 module_exit(panel_simple_exit);
5304
5305 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
5306 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
5307 MODULE_LICENSE("GPL and additional rights");
5308