1 // SPDX-License-Identifier: GPL-2.0 2 /******************************************************************************** 3 * 4 * Copyright (C) 2017 NEXTCHIP Inc. All rights reserved. 5 * Module : video_auto_detect.h 6 * Description : 7 * Author : 8 * Date : 9 * Version : Version 1.0 10 * 11 ******************************************************************************** 12 * History : 13 * 14 * 15 ********************************************************************************/ 16 #ifndef _RAPTOR3_VIDEO_AUTO_DETECT_H_ 17 #define _RAPTOR3_VIDEO_AUTO_DETECT_H_ 18 19 #include "nvp6158_common.h" 20 21 typedef enum CH_NUM 22 { 23 CH1 = 0, 24 CH2, 25 CH3, 26 CH4 27 } CH_NUM; 28 29 typedef struct _video_input_vafe { 30 unsigned char powerdown; //B0 0x00/1/2/3 [0] 31 unsigned char gain; //B0 0x00/1/2/3 [4] 32 unsigned char spd; //B5/6/7/8 0x00 [5:4] 33 34 unsigned char ctrlreg; //B5/6/7/8 0x01 [6] 35 unsigned char ctrlibs; //B5/6/7/8 0x01 [5:4] 36 unsigned char adcspd; //B5/6/7/8 0x01 [2] 37 unsigned char clplevel; //B5/6/7/8 0x01 [1:0] 38 39 40 unsigned char eq_band; //B5/6/7/8 0x58 [6:4] 41 unsigned char lpf_front_band; //B5/6/7/8 0x58 [1:0] 42 43 unsigned char clpmode; //B5/6/7/8 0x59 [7] 44 unsigned char f_lpf_bypass; //B5/6/7/8 0x59 [4] 45 unsigned char clproff; //B5/6/7/8 0x59 [3] 46 unsigned char b_lpf_bypass; //B5/6/7/8 0x59 [0] 47 48 unsigned char duty; //B5/6/7/8 0x5B [6:4] 49 unsigned char ref_vol; //B5/6/7/8 0x5B [1:0] 50 51 unsigned char lpf_back_band; //B5/6/7/8 0x5C [6:4] 52 unsigned char clk_sel; //B5/6/7/8 0x5C [3] 53 unsigned char eq_gainsel; //B5/6/7/8 0x5C [2:0] 54 55 } video_input_vafe; 56 57 typedef struct _video_input_auto_detect { 58 unsigned char ch; 59 unsigned char devnum; 60 61 unsigned char d_cmp; //B5/6/7/8 0x03 62 unsigned char slice_level; //B5/6/7/8 0x08 63 unsigned char control_mode; //B5/6/7/8 0x47 64 unsigned char gdf_fix_coeff; //B5/6/7/8 0x50 65 unsigned char dfe_ref_sel; //B5/6/7/8 0x76 66 unsigned char wpd_77; //B5/6/7/8 0x77 67 unsigned char wpd_78; //B5/6/7/8 0x78 68 unsigned char wpd_79; //B5/6/7/8 0x79 69 unsigned char auto_gnos_mode; //B5/6/7/8 0x82 70 unsigned char auto_sync_mode; //B5/6/7/8 0x83 71 unsigned char hafc_bypass; //B5/6/7/8 0xB8 72 73 unsigned char novid_vfc_init; //B13 0x31 74 unsigned char stable_mode_1; //B13 0x0 75 unsigned char stable_mode_2; //B13 0x1 76 77 unsigned char novid_det; //B0 0x23/0x27/0x2B/0x2F 78 video_input_vafe vafe; 79 } video_input_auto_detect; 80 81 typedef struct _video_input_novid { 82 unsigned char ch; 83 unsigned char novid; //B0 0xa8 [3:0] MSB 1Ch ~ LSB 4Ch 84 unsigned char devnum; 85 } video_input_novid; 86 87 typedef struct _video_input_vfc { 88 unsigned char ch; 89 unsigned char vfc; //B5/6/7/8 0xf0 90 unsigned char devnum; 91 } video_input_vfc; 92 93 typedef struct _video_input_onvid_set { 94 unsigned char ch; 95 unsigned char auto_gnos_mode; //B5/6/7/8 0x82 96 unsigned char auto_sync_mode; //B5/6/7/8 0x83 97 unsigned char op_md; //B5/6/7/8 0xB8 98 } video_input_onvid_set; 99 100 typedef struct _video_input_onvid_set_2 { 101 unsigned char ch; 102 unsigned char dfe_ref_sel; //B5/6/7/8 0x76 103 unsigned char wpd_77; //B5/6/7/8 0x77 104 unsigned char wpd_78; //B5/6/7/8 0x78 105 unsigned char wpd_79; //B5/6/7/8 0x79 106 unsigned char slice_mode; //B5/6/7/8 0x0E 107 } video_input_onvid_set_2; 108 109 typedef struct _video_input_novid_set { 110 unsigned char ch; 111 unsigned char devnum; 112 unsigned char control_mode; 113 unsigned char gdf_fix_coeff; 114 unsigned char auto_gnos_mode; 115 unsigned char auto_sync_mode; 116 unsigned char hafc_bypass; 117 unsigned char dfe_ref_sel; //B5/6/7/8 0x76 118 unsigned char wpd_77; //B5/6/7/8 0x77 119 unsigned char wpd_78; //B5/6/7/8 0x78 120 unsigned char wpd_79; //B5/6/7/8 0x79 121 unsigned char slice_mode; //B5/6/7/8 0x0E 122 } video_input_novid_set; 123 124 typedef struct _video_input_cable_dist { 125 unsigned char ch; 126 unsigned char devnum; 127 unsigned char dist; // B13 0xA0 128 unsigned char FmtDef; 129 unsigned char cabletype; // 0:coax, 1:utp, 2:reserved1, 3:reserved2 130 } video_input_cable_dist; 131 132 typedef struct _video_input_sam_val { 133 unsigned char ch; 134 unsigned char devnum; 135 /* 136 unsigned char sam_val_1; // B13 0xCD [7:0] 137 unsigned char sam_val_2; // B13 0xCC [9:8] 138 */ 139 unsigned int sam_val; 140 } video_input_sam_val; 141 142 typedef struct _video_input_hsync_accum { 143 unsigned char ch; 144 unsigned char devnum; 145 unsigned char h_lock; // Bank 0 0xE2 [3:0] [Ch3:Ch0] 146 unsigned int hsync_accum_val1; // Value 1 // 170210 Add 147 unsigned int hsync_accum_val2; // Value 2 // 170210 Add 148 unsigned int hsync_accum_result; // Value 1 - Value 2 // 170210 Fix 149 } video_input_hsync_accum; 150 151 typedef struct _video_input_agc_val { 152 unsigned char ch; 153 unsigned char devnum; 154 unsigned char agc_lock; 155 unsigned char agc_val; // B13 0xB8 156 } video_input_agc_val; 157 158 typedef struct _video_input_format_set_done { // [add] 170209 format set done 159 unsigned char ch; 160 unsigned char set_val; // B13 0x70 [3:0] each channel 161 } video_input_format_set_done; 162 163 typedef struct _video_input_fsc_val { 164 unsigned char ch; 165 unsigned char devnum; 166 unsigned int fsc_val1; 167 unsigned int fsc_val2; 168 unsigned int fsc_final; 169 } video_input_fsc_val; 170 171 typedef struct _video_input_aeq_set { // 170214 AEQ Set 172 unsigned char ch; 173 unsigned char aeq_val; //B5/6/7/8 0x58 [7:4] 174 } video_input_aeq_set; 175 176 typedef struct _video_input_deq_set { // 170214 DEQ Set 177 unsigned char ch; 178 unsigned char deq_val; // B9 0x80/0xA0/0xC0/0xE0 [3:0] 179 } video_input_deq_set; 180 181 typedef struct _video_input_vfc_set { // 170215 VFC Setting Enable (temp) 182 unsigned char ch; 183 unsigned char set_val; 184 } video_input_vfc_set; 185 186 187 typedef struct _video_input_acc_gain_val { // 170215 acc gain value read 188 unsigned char ch; 189 unsigned char devnum; 190 unsigned int acc_gain_val; 191 unsigned char func_sel; 192 } video_input_acc_gain_val; 193 194 typedef struct _video_input_sleep_time_val { // 170215 acc gain value read 195 unsigned char sleep_val; 196 } video_input_sleep_time_val; 197 198 typedef struct _video_input_agc_reset_val { // 170221 agc init 199 unsigned char ch; 200 unsigned char reset_val; 201 } video_input_agc_reset_val; 202 203 typedef struct _video_output_data_out_mode { 204 unsigned char ch; 205 unsigned char devnum; 206 unsigned char set_val; 207 } video_output_data_out_mode; 208 209 typedef struct _video_input_manual_mode { 210 unsigned char ch; 211 unsigned char dev_num; 212 } video_input_manual_mode; 213 214 typedef struct _video_input_onvideo_check_s { 215 unsigned char vfc; 216 unsigned char sw_rst_ret; 217 decoder_dev_ch_info_s info; 218 } video_input_onvideo_check_s; 219 220 221 void nvp6158_video_input_auto_detect_set(video_input_auto_detect *vin_auto_det); 222 void nvp6158_video_input_vfc_read(video_input_vfc *vin_vfc); 223 void nvp6158_video_input_novid_read(video_input_novid *vin_novid); // 170204 novid 224 void nvp6158_video_input_no_video_set(video_input_novid *auto_novid); // 170206 novideo set 225 void nvp6158_video_input_cable_dist_read(video_input_cable_dist *vin_cable_dist); // 170207 Cable Distance 226 void nvp6158_video_input_sam_val_read(video_input_sam_val *vin_sam_val ); // 170207 SAM Value 227 void nvp6158_video_input_hsync_accum_read(video_input_hsync_accum *vin_hsync_accum ); // 170207 Hsync Accumulation 228 void nvp6158_video_input_agc_val_read(video_input_agc_val *vin_agc_val); // 170207 AGC Value 229 void nvp6158_video_input_fsc_val_read(video_input_fsc_val *vin_fsc_val); // 170214 fsc value read 230 void nvp6158_video_input_aeq_val_set(video_input_aeq_set *vin_aeq_val); // 170214 aeq value set 231 void nvp6158_video_input_deq_val_set(video_input_deq_set *vin_deq_val); // 170214 deq value set 232 void nvp6158_video_input_acc_gain_val_read(video_input_acc_gain_val *vin_acc_gain); // 170215 acc gain value read 233 void nvp6158_video_output_data_out_mode_set(video_output_data_out_mode *vo_data_out_mode); // 170329 Data Out Mode Setting Func 234 void nvp6158_video_input_manual_mode_set(video_input_manual_mode *vin_manual_det); // 170330 Manual Mode Set 235 void nvp6158_video_input_onvideo_set(decoder_dev_ch_info_s *decoder_info); 236 237 void nvp6158_video_input_onvideo_check_data(video_input_vfc *vin_vfc); 238 void nvp6158_video_input_auto_ch_sw_rst(decoder_dev_ch_info_s *decoder_info); 239 240 int nvp6158_video_input_cable_measure_way( unsigned char ch, unsigned char devnum ); 241 void nvp6158_video_input_vafe_reset(decoder_dev_ch_info_s *decoder_info); 242 void nvp6158_video_input_vafe_control(decoder_dev_ch_info_s *decoder_info, int cmd); 243 void nvp6158_video_input_manual_agc_stable_endi(decoder_dev_ch_info_s *decoder_info, int endi); 244 void nvp6158_video_input_ahd_tvi_distinguish(decoder_dev_ch_info_s *decoder_info); 245 int nvp6158_video_input_cvi_tvi_distinguish(decoder_dev_ch_info_s *decoder_info); 246 void nvp6158_video_input_cvi_ahd_1080p_distinguish(decoder_dev_ch_info_s *decoder_info); 247 void nvp6158_video_input_ahd_nrt_distinguish(decoder_dev_ch_info_s *decoder_info); 248 unsigned char __nvp6158_IsOver3MRTVideoFormat( decoder_dev_ch_info_s *decoder_info ); 249 NC_VIVO_CH_FORMATDEF NVP6158_NC_VD_AUTO_VFCtoFMTDEF(unsigned char ch, unsigned char VFC); 250 void nvp6168_video_input_hsync_accum_read(video_input_hsync_accum *vin_hsync_accum ); 251 void nvp6168_video_input_onvideo_set(decoder_dev_ch_info_s *decoder_info); 252 void nvp6168_video_input_vfc_read(video_input_vfc *vin_vfc); 253 void nvp6168_video_input_auto_detect_set(video_input_auto_detect * vin_auto_det); 254 void nvp6168_video_input_no_video_set(video_input_novid * auto_novid); 255 void nvp6168_video_input_cvi_tvi_5M20p_distinguish(decoder_dev_ch_info_s *decoder_info); 256 void nvp6168_video_input_manual_mode_set(video_input_manual_mode *vin_manual_det); 257 258 259 260 #endif /* _RAPTOR3_VIDEO_AUTO_DETECT_H_ */ 261