1 /* 2 * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * This file contains the CSS-firmware specific definitions for the third 7 * generation of platforms. 8 */ 9 10 #ifndef NRD_CSS_FW_DEF3_H 11 #define NRD_CSS_FW_DEF3_H 12 13 #include <nrd_css_def3.h> 14 15 /******************************************************************************* 16 * BL sizes 17 ******************************************************************************/ 18 19 #define NRD_CSS_BL1_RW_SIZE UL(64 * 1024) /* 64KB */ 20 21 #define NRD_CSS_BL1_RO_BASE NRD_CSS_SHARED_SRAM_BASE 22 #define NRD_CSS_BL1_RO_SIZE UL(0x00019000) 23 24 # define NRD_CSS_BL2_SIZE UL(0x30000) 25 26 /* 27 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 28 * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2 29 * and BL1-RW. NRD_BL31_SIZE - is tuned with respect to the actual BL31 30 * PROGBITS size which is around 64-68KB at the time this change is being made. 31 * A buffer of ~35KB is added to account for future expansion of the image, 32 * making it a total of 100KB. 33 */ 34 #define NRD_CSS_BL31_SIZE UL(116 * 1024) /* 116 KB */ 35 36 #define NRD_CSS_DRAM1_CARVEOUT_SIZE UL(0x0C000000) /* 192MB */ 37 38 /******************************************************************************* 39 * Console config 40 ******************************************************************************/ 41 42 #define NRD_CSS_UART_CLK_IN_HZ UL(7372800) 43 44 /******************************************************************************* 45 * Watchdog config 46 ******************************************************************************/ 47 48 #define NRD_CSS_AP_SECURE_WDOG_TIMEOUT UL(100) 49 50 /******************************************************************************* 51 * RMM Console Config 52 ******************************************************************************/ 53 54 #define NRD_CSS_RMM_CONSOLE_BASE NRD_CSS_REALM_UART_BASE 55 #define NRD_CSS_RMM_CONSOLE_BAUD ARM_CONSOLE_BAUDRATE 56 #define NRD_CSS_RMM_CONSOLE_CLK_IN_HZ UL(14745600) 57 #define NRD_CSS_RMM_CONSOLE_NAME "pl011" 58 #define NRD_CSS_RMM_CONSOLE_COUNT UL(1) 59 60 /******************************************************************************* 61 * MMU mapping 62 ******************************************************************************/ 63 64 #define NRD_CSS_PERIPH_MMAP(n) \ 65 MAP_REGION_FLAT( \ 66 NRD_REMOTE_CHIP_MEM_OFFSET(n) + \ 67 NRD_CSS_PERIPH_BASE, \ 68 NRD_CSS_PERIPH_SIZE, \ 69 MT_DEVICE | MT_RW | EL3_PAS) 70 71 #define NRD_CSS_SHARED_RAM_MMAP(n) \ 72 MAP_REGION_FLAT( \ 73 NRD_REMOTE_CHIP_MEM_OFFSET(n) + \ 74 ARM_SHARED_RAM_BASE, \ 75 ARM_SHARED_RAM_SIZE, \ 76 MT_MEMORY | MT_RW | EL3_PAS) 77 78 #define NRD_CSS_GPC_SMMU_SMMUV3_MMAP \ 79 MAP_REGION_FLAT( \ 80 NRD_CSS_GPC_SMMUV3_BASE, \ 81 NRD_CSS_GPC_SMMUV3_SIZE, \ 82 MT_DEVICE | MT_RW | EL3_PAS) 83 84 #define NRD_CSS_BL1_RW_MMAP \ 85 MAP_REGION_FLAT( \ 86 BL1_RW_BASE, \ 87 BL1_RW_LIMIT - BL1_RW_BASE, \ 88 MT_MEMORY | MT_RW | EL3_PAS) 89 90 #define NRD_CSS_NS_DRAM1_MMAP \ 91 MAP_REGION_FLAT( \ 92 ARM_NS_DRAM1_BASE, \ 93 ARM_NS_DRAM1_SIZE, \ 94 MT_MEMORY | MT_RW | MT_NS) 95 96 #define NRD_CSS_GPT_L1_DRAM_MMAP \ 97 MAP_REGION_FLAT( \ 98 ARM_L1_GPT_BASE, \ 99 ARM_L1_GPT_SIZE, \ 100 MT_MEMORY | MT_RW | EL3_PAS) 101 102 #define NRD_CSS_EL3_RMM_SHARED_MEM_MMAP \ 103 MAP_REGION_FLAT( \ 104 ARM_EL3_RMM_SHARED_BASE, \ 105 ARM_EL3_RMM_SHARED_SIZE, \ 106 MT_MEMORY | MT_RW | MT_REALM) 107 108 #define NRD_CSS_RMM_REGION_MMAP \ 109 MAP_REGION_FLAT( \ 110 ARM_REALM_BASE, \ 111 ARM_REALM_SIZE, \ 112 MT_MEMORY | MT_RW | MT_REALM) 113 114 #if SPD_spmd && SPMD_SPM_AT_SEL2 115 #define NRD_CSS_SPM_CORE_REGION_MMAP \ 116 MAP_REGION_FLAT( \ 117 BL32_BASE, \ 118 BL32_LIMIT - BL32_BASE, \ 119 MT_MEMORY | MT_RW | MT_SECURE) 120 #endif 121 122 /******************************************************************************* 123 * Helper macros 124 ******************************************************************************/ 125 126 #define NRD_CSS_PAGE_ALIGN_CEIL(x) (((x) + PAGE_SIZE_MASK) & ~(PAGE_SIZE_MASK)) 127 128 #if RESET_TO_BL31 129 /******************************************************************************* 130 * BL31 specific defines. 131 ******************************************************************************/ 132 133 /* Define the DTB image base and size */ 134 #define NRD_CSS_BL31_PRELOAD_DTB_BASE UL(0xF3000000) 135 #define NRD_CSS_BL31_PRELOAD_DTB_SIZE UL(0x1000) 136 #define NRD_CSS_MAP_BL31_DTB MAP_REGION_FLAT( \ 137 NRD_CSS_BL31_PRELOAD_DTB_BASE, \ 138 NRD_CSS_BL31_PRELOAD_DTB_SIZE, \ 139 MT_RW_DATA | MT_NS) 140 #endif /* RESET_TO_BL31 */ 141 142 #endif /* NRD_CSS_FW_DEF3_H */ 143