1 /*
2 * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <plat/common/platform.h>
9 #include <lib/pm/mtk_pm.h>
10
11 #define MTK_PM_ST_SMP_READY BIT(0)
12 #define MTK_PM_ST_PWR_READY BIT(1)
13 #define MTK_PM_ST_RESET_READY BIT(2)
14
15 static uintptr_t mtk_secure_entrypoint;
16 static plat_init_func mtk_plat_smp_init;
17 static plat_psci_ops_t mtk_pm_ops;
18 static unsigned int mtk_pm_status;
19
plat_pm_get_warm_entry(void)20 uintptr_t plat_pm_get_warm_entry(void)
21 {
22 return mtk_secure_entrypoint;
23 }
24
plat_pm_ops_setup_pwr(struct plat_pm_pwr_ctrl * ops)25 int plat_pm_ops_setup_pwr(struct plat_pm_pwr_ctrl *ops)
26 {
27 if (!ops) {
28 return MTK_CPUPM_E_FAIL;
29 }
30
31 #if CONFIG_MTK_CPU_SUSPEND_EN
32 if (!mtk_pm_ops.pwr_domain_suspend) {
33 mtk_pm_ops.pwr_domain_suspend = ops->pwr_domain_suspend;
34 }
35
36 if (!mtk_pm_ops.pwr_domain_suspend_finish) {
37 mtk_pm_ops.pwr_domain_suspend_finish = ops->pwr_domain_suspend_finish;
38 }
39
40 if (!mtk_pm_ops.validate_power_state) {
41 mtk_pm_ops.validate_power_state = ops->validate_power_state;
42 }
43
44 if (!mtk_pm_ops.get_sys_suspend_power_state) {
45 mtk_pm_ops.get_sys_suspend_power_state = ops->get_sys_suspend_power_state;
46 }
47
48 if (!mtk_pm_ops.pwr_domain_pwr_down)
49 mtk_pm_ops.pwr_domain_pwr_down = ops->pwr_domain_pwr_down_wfi;
50
51 mtk_pm_status |= MTK_PM_ST_PWR_READY;
52 #endif
53 return MTK_CPUPM_E_OK;
54 }
55
plat_pm_ops_setup_smp(struct plat_pm_smp_ctrl * ops)56 int plat_pm_ops_setup_smp(struct plat_pm_smp_ctrl *ops)
57 {
58 if (!ops) {
59 return MTK_CPUPM_E_FAIL;
60 }
61
62 #if CONFIG_MTK_SMP_EN
63 if (!mtk_pm_ops.pwr_domain_on) {
64 mtk_pm_ops.pwr_domain_on = ops->pwr_domain_on;
65 }
66
67 if (!mtk_pm_ops.pwr_domain_on_finish) {
68 mtk_pm_ops.pwr_domain_on_finish = ops->pwr_domain_on_finish;
69 }
70
71 if (!mtk_pm_ops.pwr_domain_off) {
72 mtk_pm_ops.pwr_domain_off = ops->pwr_domain_off;
73 }
74
75 if (!mtk_plat_smp_init) {
76 mtk_plat_smp_init = ops->init;
77 }
78
79 mtk_pm_status |= MTK_PM_ST_SMP_READY;
80 #endif
81 return MTK_CPUPM_E_OK;
82 }
83
plat_pm_ops_setup_reset(struct plat_pm_reset_ctrl * ops)84 int plat_pm_ops_setup_reset(struct plat_pm_reset_ctrl *ops)
85 {
86 if (!ops) {
87 return MTK_CPUPM_E_FAIL;
88 }
89
90 if (!mtk_pm_ops.system_off) {
91 mtk_pm_ops.system_off = ops->system_off;
92 }
93
94 if (!mtk_pm_ops.system_reset) {
95 mtk_pm_ops.system_reset = ops->system_reset;
96 }
97
98 if (!mtk_pm_ops.system_reset2) {
99 mtk_pm_ops.system_reset2 = ops->system_reset2;
100 }
101
102 mtk_pm_status |= MTK_PM_ST_RESET_READY;
103
104 return MTK_CPUPM_E_OK;
105 }
106
plat_setup_psci_ops(uintptr_t sec_entrypoint,const plat_psci_ops_t ** psci_ops)107 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
108 const plat_psci_ops_t **psci_ops)
109 {
110 *psci_ops = &mtk_pm_ops;
111 mtk_secure_entrypoint = sec_entrypoint;
112
113 if (mtk_plat_smp_init) {
114 unsigned int cpu_id = plat_my_core_pos();
115
116 mtk_plat_smp_init(cpu_id, mtk_secure_entrypoint);
117 }
118 INFO("%s, smp:(%d), pwr_ctrl:(%d), system_reset:(%d)\n", __func__,
119 !!(mtk_pm_status & MTK_PM_ST_SMP_READY),
120 !!(mtk_pm_status & MTK_PM_ST_PWR_READY),
121 !!(mtk_pm_status & MTK_PM_ST_RESET_READY));
122 return 0;
123 }
124