1 /*
2 * Copyright (c) 2025, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9
10 #include <common/debug.h>
11
12 #include <drivers/spm/mt_spm_vcorefs_api.h>
13 #include <mt_spm_vcorefs_common.h>
14 #include <mt_spm_vcorefs_exp.h>
15 #include <mt_spm_vcorefs_ext.h>
16 #include <mtk_sip_svc.h>
17
mtk_vcorefs_handler(u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * handle,struct smccc_res * smccc_ret)18 static u_register_t mtk_vcorefs_handler(u_register_t x1,
19 u_register_t x2,
20 u_register_t x3,
21 u_register_t x4,
22 void *handle,
23 struct smccc_res *smccc_ret)
24 {
25 uint64_t ret = VCOREFS_E_NOT_SUPPORTED;
26 uint64_t cmd = x1;
27 uint32_t val = 0;
28
29 switch (cmd) {
30 case VCOREFS_SMC_VCORE_DVFS_INIT:
31 ret = spm_vcorefs_plat_init(x2, x3, &val);
32 smccc_ret->a1 = val;
33 break;
34 case VCOREFS_SMC_VCORE_DVFS_KICK:
35 ret = spm_vcorefs_plat_kick();
36 break;
37 case VCOREFS_SMC_CMD_OPP_TYPE:
38 ret = spm_vcorefs_get_opp_type(&val);
39 smccc_ret->a1 = val;
40 break;
41 case VCOREFS_SMC_CMD_FW_TYPE:
42 ret = spm_vcorefs_get_fw_type(&val);
43 smccc_ret->a1 = val;
44 break;
45 case VCOREFS_SMC_CMD_GET_UV:
46 ret = spm_vcorefs_get_vcore_uv(x2, &val);
47 smccc_ret->a1 = val;
48 break;
49 case VCOREFS_SMC_CMD_GET_FREQ:
50 ret = spm_vcorefs_get_dram_freq(x2, &val);
51 smccc_ret->a1 = val;
52 break;
53 case VCOREFS_SMC_CMD_GET_NUM_V:
54 ret = spm_vcorefs_get_vcore_opp_num(&val);
55 smccc_ret->a1 = val;
56 break;
57 case VCOREFS_SMC_CMD_GET_NUM_F:
58 ret = spm_vcorefs_get_dram_opp_num(&val);
59 smccc_ret->a1 = val;
60 break;
61 case VCOREFS_SMC_CMD_GET_VCORE_INFO:
62 ret = spm_vcorefs_get_vcore_info(x2, &val);
63 smccc_ret->a1 = val;
64 break;
65 case VCOREFS_SMC_CMD_QOS_MODE:
66 ret = spm_vcorefs_qos_mode(x2);
67 break;
68 #ifdef MTK_VCORE_DVFS_PAUSE
69 case VCOREFS_SMC_CMD_PAUSE_ENABLE:
70 ret = spm_vcorefs_pause_enable(x2);
71 break;
72 #endif
73 #ifdef MTK_VCORE_DVFS_RES_MEM
74 case VCOREFS_SMC_RSC_MEM_REQ:
75 ret = spm_vcorefs_rsc_mem_req(true);
76 break;
77 case VCOREFS_SMC_RSC_MEM_REL:
78 ret = spm_vcorefs_rsc_mem_req(false);
79 break;
80 #endif
81 default:
82 break;
83 }
84 return ret;
85 }
86
87 DECLARE_SMC_HANDLER(MTK_SIP_VCORE_CONTROL, mtk_vcorefs_handler);
88
89 #ifdef CONFIG_MTK_VCOREDVFS_LK_SUPPORT
mtk_vcorefs_bl_handler(u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * handle,struct smccc_res * smccc_ret)90 static u_register_t mtk_vcorefs_bl_handler(u_register_t x1,
91 u_register_t x2,
92 u_register_t x3,
93 u_register_t x4,
94 void *handle,
95 struct smccc_res *smccc_ret)
96 {
97 uint64_t = VCOREFS_E_NOT_SUPPORTED;
98 uint32_t val = 0;
99
100 switch (x1) {
101 case VCOREFS_SMC_VCORE_DVFS_INIT:
102 ret = spm_vcorefs_plat_init(x2, x3, &val);
103 smccc_ret->a1 = val;
104 break;
105 case VCOREFS_SMC_VCORE_DVFS_KICK:
106 ret = spm_vcorefs_plat_kick();
107 break;
108 default:
109 break;
110 }
111 return ret;
112 }
113
114 DECLARE_SMC_HANDLER(MTK_SIP_BL_SPM_VCOREFS_CONTROL, mtk_vcorefs_bl_handler);
115 #endif
116