1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_SMC_H 8 #define MT_SPM_SMC_H 9 10 /* 11 * SPM dispatcher's smc id definition 12 * Please adding custom smc id here for spm dispatcher 13 */ 14 #define MT_SPM_STATUS_SUSPEND_SLEEP BIT(27) 15 16 enum mt_spm_smc_uid { 17 MT_SPM_SMC_UID_STATUS, 18 MT_SPM_SMC_UID_PCM_WDT, 19 MT_SPM_SMC_UID_PCM_TIMER, 20 MT_SPM_SMC_UID_FW_TYPE, 21 MT_SPM_SMC_UID_PHYPLL_MODE, 22 MT_SPM_SMC_UID_SET_PENDING_IRQ_INIT, 23 MT_SPM_SMC_UID_FW_INIT = 0x5731, 24 }; 25 26 /* 27 * SPM dbg dispatcher's smc id definition 28 * Please adding custom smc id here for spm dbg dispatcher 29 */ 30 enum mt_spm_dbg_smc_uid { 31 MT_SPM_DBG_SMC_UID_IDLE_PWR_CTRL, 32 MT_SPM_DBG_SMC_UID_IDLE_CNT, 33 MT_SPM_DBG_SMC_UID_SUSPEND_PWR_CTRL, 34 MT_SPM_DBG_SMC_UID_SUSPEND_DBG_CTRL, 35 MT_SPM_DBG_SMC_UID_FS, 36 MT_SPM_DBG_SMC_UID_RC_SWITCH, 37 MT_SPM_DBG_SMC_UID_RC_CNT, 38 MT_SPM_DBG_SMC_UID_COND_CHECK, 39 MT_SPM_DBG_SMC_UID_COND_BLOCK, 40 MT_SPM_DBG_SMC_UID_BLOCK_LATCH, 41 MT_SPM_DBG_SMC_UID_BLOCK_DETAIL, 42 MT_SPM_DBG_SMC_UID_RES_NUM, 43 MT_SPM_DBG_SMC_UID_RES_REQ, 44 MT_SPM_DBG_SMC_UID_RES_USAGE, 45 MT_SPM_DBG_SMC_UID_RES_USER_NUM, 46 MT_SPM_DBG_SMC_UID_RES_USER_VALID, 47 MT_SPM_DBG_SMC_UID_RES_USER_NAME, 48 MT_SPM_DBG_SMC_UID_DOE_RESOURCE_CTRL, 49 MT_SPM_DBG_SMC_UID_DOE_RC, 50 MT_SPM_DBG_SMC_UID_RC_COND_CTRL, 51 MT_SPM_DBG_SMC_UID_RC_RES_CTRL, 52 MT_SPM_DBG_SMC_UID_RC_RES_INFO, 53 MT_SPM_DBG_SMC_UID_RC_BBLPM, 54 MT_SPM_DBG_SMC_UID_RC_TRACE, 55 MT_SPM_DBG_SMC_UID_RC_TRACE_TIME, 56 MT_SPM_DBG_SMC_UID_DUMP_PLL, 57 MT_SPM_DBG_SMC_HWCG_NUM, 58 MT_SPM_DBG_SMC_HWCG_STATUS, 59 MT_SPM_DBG_SMC_HWCG_SETTING, 60 MT_SPM_DBG_SMC_HWCG_DEF_SETTING, 61 MT_SPM_DBG_SMC_HWCG_RES_NAME, 62 MT_SPM_DBG_SMC_UID_RC_NOTIFY_CTRL, 63 MT_SPM_DBG_SMC_VCORE_LP_ENABLE, 64 MT_SPM_DBG_SMC_VCORE_LP_VOLT, 65 MT_SPM_DBG_SMC_VSRAM_LP_ENABLE, 66 MT_SPM_DBG_SMC_VSRAM_LP_VOLT, 67 MT_SPM_DBG_SMC_PERI_REQ_NUM, 68 MT_SPM_DBG_SMC_PERI_REQ_STATUS, 69 MT_SPM_DBG_SMC_PERI_REQ_SETTING, 70 MT_SPM_DBG_SMC_PERI_REQ_DEF_SETTING, 71 MT_SPM_DBG_SMC_PERI_REQ_RES_NAME, 72 MT_SPM_DBG_SMC_PERI_REQ_STATUS_RAW, 73 MT_SPM_DBG_SMC_IDLE_PWR_STAT, 74 MT_SPM_DBG_SMC_SUSPEND_PWR_STAT, 75 MT_SPM_DBG_SMC_LP_REQ_STAT, 76 MT_SPM_DBG_SMC_COMMON_SODI_CTRL, 77 MT_SPM_DBG_SMC_SPM_TIMESTAMP, 78 MT_SPM_DBG_SMC_SPM_TIMESTAMP_SIZE, 79 MT_SPM_DBG_SMC_UID_COMMON_SODI_PWR_CTRL, 80 }; 81 82 enum wake_status_enum { 83 WAKE_STA_ASSERT_PC, 84 WAKE_STA_R12, 85 WAKE_STA_R12_EXT, 86 WAKE_STA_RAW_STA, 87 WAKE_STA_RAW_EXT_STA, 88 WAKE_STA_WAKE_MISC, 89 WAKE_STA_TIMER_OUT, 90 WAKE_STA_R13, 91 WAKE_STA_IDLE_STA, 92 WAKE_STA_REQ_STA, 93 WAKE_STA_DEBUG_FLAG, 94 WAKE_STA_DEBUG_FLAG1, 95 WAKE_STA_EVENT_REG, 96 WAKE_STA_ISR, 97 WAKE_STA_MAX_COUNT, 98 }; 99 100 #endif /* MT_SPM_SMC_H */ 101