1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
4 */
5
6 #define MODULE_TAG "mpp_soc"
7
8 #include <sys/ioctl.h>
9 #include <errno.h>
10 #include <fcntl.h>
11 #include <string.h>
12
13 #include "mpp_env.h"
14 #include "mpp_mem.h"
15 #include "mpp_debug.h"
16 #include "mpp_common.h"
17 #include "mpp_singleton.h"
18
19 #include "mpp_soc.h"
20 #include "mpp_platform.h"
21
22 #define MAX_SOC_NAME_LENGTH 128
23
24 #define get_srv_soc() \
25 ({ \
26 MppSocSrv *__tmp; \
27 if (!srv_soc) { \
28 mpp_soc_srv_init(); \
29 } \
30 if (srv_soc) { \
31 __tmp = srv_soc; \
32 } else { \
33 mpp_err("mpp soc srv not init at %s\n", __FUNCTION__); \
34 __tmp = NULL; \
35 } \
36 __tmp; \
37 })
38
39 #define CODING_TO_IDX(type) \
40 ((rk_u32)(type) >= (rk_u32)MPP_VIDEO_CodingKhronosExtensions) ? \
41 ((rk_u32)(-1)) : \
42 ((rk_u32)(type) >= (rk_u32)MPP_VIDEO_CodingVC1) ? \
43 ((rk_u32)(type) - (rk_u32)MPP_VIDEO_CodingVC1 + 16) : \
44 ((rk_u32)(type) - (rk_u32)MPP_VIDEO_CodingUnused)
45
46 #define HAVE_MPEG2 ((rk_u32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingMPEG2))))
47 #define HAVE_H263 ((rk_u32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingH263))))
48 #define HAVE_MPEG4 ((rk_u32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingMPEG4))))
49 #define HAVE_AVC ((rk_u32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVC))))
50 #define HAVE_MJPEG ((rk_u32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingMJPEG))))
51 #define HAVE_VP8 ((rk_u32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingVP8))))
52 #define HAVE_VP9 ((rk_u32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingVP9))))
53 #define HAVE_HEVC ((rk_u32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingHEVC))))
54 #define HAVE_AVSP ((rk_u32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVSPLUS))))
55 #define HAVE_AVS ((rk_u32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVS))))
56 #define HAVE_AVS2 ((rk_u32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVS2))))
57 #define HAVE_AV1 ((rk_u32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAV1))))
58
59 #define CAP_CODING_VDPU (HAVE_MPEG2|HAVE_H263|HAVE_MPEG4|HAVE_AVC|HAVE_MJPEG|HAVE_VP8|HAVE_AVS)
60 #define CAP_CODING_JPEGD_PP (HAVE_MJPEG)
61 #define CAP_CODING_AVSD (HAVE_AVS)
62 #define CAP_CODING_AVSPD (HAVE_AVSP)
63 #define CAP_CODING_AV1D (HAVE_AV1)
64 #define CAP_CODING_HEVC (HAVE_HEVC)
65 #define CAP_CODING_VDPU341 (HAVE_AVC|HAVE_HEVC|HAVE_VP9)
66 #define CAP_CODING_VDPU341_LITE (HAVE_AVC|HAVE_HEVC)
67 #define CAP_CODING_VDPU381 (HAVE_AVC|HAVE_HEVC|HAVE_VP9|HAVE_AVS2)
68 #define CAP_CODING_VDPU382 (HAVE_AVC|HAVE_HEVC|HAVE_AVS2)
69 #define CAP_CODING_VDPU383 (HAVE_AVC|HAVE_HEVC|HAVE_VP9|HAVE_AVS2|HAVE_AV1)
70 #define CAP_CODING_VDPU384A (HAVE_AVC|HAVE_HEVC)
71
72 #define CAP_CODING_VEPU1 (HAVE_AVC|HAVE_MJPEG|HAVE_VP8)
73 #define CAP_CODING_VEPU_LITE (HAVE_AVC|HAVE_MJPEG)
74 #define CAP_CODING_VEPU22 (HAVE_HEVC)
75 #define CAP_CODING_VEPU54X (HAVE_AVC|HAVE_HEVC)
76 #define CAP_CODING_VEPU540C (HAVE_AVC|HAVE_HEVC|HAVE_MJPEG)
77 #define CAP_CODING_VEPU511 (HAVE_AVC|HAVE_HEVC|HAVE_MJPEG)
78
79 static const MppDecHwCap vdpu1 = {
80 .cap_coding = CAP_CODING_VDPU,
81 .type = VPU_CLIENT_VDPU1,
82 .cap_fbc = 0,
83 .cap_4k = 0,
84 .cap_8k = 0,
85 .cap_colmv_compress = 0,
86 .cap_hw_h265_rps = 0,
87 .cap_hw_vp9_prob = 0,
88 .cap_jpg_pp_out = 0,
89 .cap_10bit = 0,
90 .cap_down_scale = 0,
91 .cap_lmt_linebuf = 1,
92 .cap_core_num = 1,
93 .cap_hw_jpg_fix = 0,
94 .reserved = 0,
95 };
96
97 static const MppDecHwCap vdpu1_2160p = {
98 .cap_coding = CAP_CODING_VDPU,
99 .type = VPU_CLIENT_VDPU1,
100 .cap_fbc = 0,
101 .cap_4k = 1,
102 .cap_8k = 0,
103 .cap_colmv_compress = 0,
104 .cap_hw_h265_rps = 0,
105 .cap_hw_vp9_prob = 0,
106 .cap_jpg_pp_out = 0,
107 .cap_10bit = 0,
108 .cap_down_scale = 0,
109 .cap_lmt_linebuf = 1,
110 .cap_core_num = 1,
111 .cap_hw_jpg_fix = 0,
112 .reserved = 0,
113 };
114
115 static const MppDecHwCap vdpu1_jpeg_pp = {
116 .cap_coding = CAP_CODING_JPEGD_PP,
117 .type = VPU_CLIENT_VDPU1_PP,
118 .cap_fbc = 0,
119 .cap_4k = 1,
120 .cap_8k = 1,
121 .cap_colmv_compress = 0,
122 .cap_hw_h265_rps = 0,
123 .cap_hw_vp9_prob = 0,
124 .cap_jpg_pp_out = 1,
125 .cap_10bit = 0,
126 .cap_down_scale = 0,
127 .cap_lmt_linebuf = 1,
128 .cap_core_num = 1,
129 .cap_hw_jpg_fix = 0,
130 .reserved = 0,
131 };
132
133 static const MppDecHwCap vdpu2 = {
134 .cap_coding = CAP_CODING_VDPU,
135 .type = VPU_CLIENT_VDPU2,
136 .cap_fbc = 0,
137 .cap_4k = 0,
138 .cap_8k = 0,
139 .cap_colmv_compress = 0,
140 .cap_hw_h265_rps = 0,
141 .cap_hw_vp9_prob = 0,
142 .cap_jpg_pp_out = 0,
143 .cap_10bit = 0,
144 .cap_down_scale = 0,
145 .cap_lmt_linebuf = 1,
146 .cap_core_num = 1,
147 .cap_hw_jpg_fix = 0,
148 .reserved = 0,
149 };
150
151 static const MppDecHwCap vdpu2_jpeg = {
152 .cap_coding = HAVE_MJPEG,
153 .type = VPU_CLIENT_VDPU2,
154 .cap_fbc = 0,
155 .cap_4k = 0,
156 .cap_8k = 0,
157 .cap_colmv_compress = 0,
158 .cap_hw_h265_rps = 0,
159 .cap_hw_vp9_prob = 0,
160 .cap_jpg_pp_out = 0,
161 .cap_10bit = 0,
162 .cap_down_scale = 0,
163 .cap_lmt_linebuf = 1,
164 .cap_core_num = 1,
165 .cap_hw_jpg_fix = 0,
166 .reserved = 0,
167 };
168
169 static const MppDecHwCap vdpu2_jpeg_pp = {
170 .cap_coding = CAP_CODING_JPEGD_PP,
171 .type = VPU_CLIENT_VDPU2_PP,
172 .cap_fbc = 0,
173 .cap_4k = 0,
174 .cap_8k = 0,
175 .cap_colmv_compress = 0,
176 .cap_hw_h265_rps = 0,
177 .cap_hw_vp9_prob = 0,
178 .cap_jpg_pp_out = 1,
179 .cap_10bit = 0,
180 .cap_down_scale = 0,
181 .cap_lmt_linebuf = 1,
182 .cap_core_num = 1,
183 .cap_hw_jpg_fix = 0,
184 .reserved = 0,
185 };
186
187 static const MppDecHwCap vdpu2_jpeg_fix = {
188 .cap_coding = HAVE_MJPEG,
189 .type = VPU_CLIENT_VDPU2,
190 .cap_fbc = 0,
191 .cap_4k = 0,
192 .cap_8k = 0,
193 .cap_colmv_compress = 0,
194 .cap_hw_h265_rps = 0,
195 .cap_hw_vp9_prob = 0,
196 .cap_jpg_pp_out = 0,
197 .cap_10bit = 0,
198 .cap_down_scale = 0,
199 .cap_lmt_linebuf = 1,
200 .cap_core_num = 1,
201 .cap_hw_jpg_fix = 1,
202 .reserved = 0,
203 };
204
205 static const MppDecHwCap vdpu2_jpeg_pp_fix = {
206 .cap_coding = CAP_CODING_JPEGD_PP,
207 .type = VPU_CLIENT_VDPU2_PP,
208 .cap_fbc = 0,
209 .cap_4k = 0,
210 .cap_8k = 0,
211 .cap_colmv_compress = 0,
212 .cap_hw_h265_rps = 0,
213 .cap_hw_vp9_prob = 0,
214 .cap_jpg_pp_out = 1,
215 .cap_10bit = 0,
216 .cap_down_scale = 0,
217 .cap_lmt_linebuf = 1,
218 .cap_core_num = 1,
219 .cap_hw_jpg_fix = 1,
220 .reserved = 0,
221 };
222
223 static const MppDecHwCap rk_hevc = {
224 .cap_coding = CAP_CODING_HEVC,
225 .type = VPU_CLIENT_HEVC_DEC,
226 .cap_fbc = 0,
227 .cap_4k = 1,
228 .cap_8k = 0,
229 .cap_colmv_compress = 0,
230 .cap_hw_h265_rps = 0,
231 .cap_hw_vp9_prob = 0,
232 .cap_jpg_pp_out = 0,
233 .cap_10bit = 1,
234 .cap_down_scale = 0,
235 .cap_lmt_linebuf = 1,
236 .cap_core_num = 1,
237 .cap_hw_jpg_fix = 0,
238 .reserved = 0,
239 };
240
241 static const MppDecHwCap rk_hevc_1080p = {
242 .cap_coding = CAP_CODING_HEVC,
243 .type = VPU_CLIENT_HEVC_DEC,
244 .cap_fbc = 0,
245 .cap_4k = 0,
246 .cap_8k = 0,
247 .cap_colmv_compress = 0,
248 .cap_hw_h265_rps = 0,
249 .cap_hw_vp9_prob = 0,
250 .cap_jpg_pp_out = 0,
251 .cap_10bit = 0,
252 .cap_down_scale = 0,
253 .cap_lmt_linebuf = 1,
254 .cap_core_num = 1,
255 .cap_hw_jpg_fix = 0,
256 .reserved = 0,
257 };
258
259 static const MppDecHwCap vdpu341 = {
260 .cap_coding = CAP_CODING_VDPU341,
261 .type = VPU_CLIENT_RKVDEC,
262 .cap_fbc = 0,
263 .cap_4k = 1,
264 .cap_8k = 0,
265 .cap_colmv_compress = 1,
266 .cap_hw_h265_rps = 0,
267 .cap_hw_vp9_prob = 0,
268 .cap_jpg_pp_out = 0,
269 .cap_10bit = 1,
270 .cap_down_scale = 0,
271 .cap_lmt_linebuf = 1,
272 .cap_core_num = 1,
273 .cap_hw_jpg_fix = 0,
274 .reserved = 0,
275 };
276
277 static const MppDecHwCap vdpu341_lite = {
278 .cap_coding = CAP_CODING_VDPU341_LITE,
279 .type = VPU_CLIENT_RKVDEC,
280 .cap_fbc = 0,
281 .cap_4k = 1,
282 .cap_8k = 0,
283 .cap_colmv_compress = 1,
284 .cap_hw_h265_rps = 0,
285 .cap_hw_vp9_prob = 0,
286 .cap_jpg_pp_out = 0,
287 .cap_10bit = 1,
288 .cap_down_scale = 0,
289 .cap_lmt_linebuf = 1,
290 .cap_core_num = 1,
291 .cap_hw_jpg_fix = 0,
292 .reserved = 0,
293 };
294
295 static const MppDecHwCap vdpu341_lite_1080p = {
296 .cap_coding = CAP_CODING_VDPU341_LITE,
297 .type = VPU_CLIENT_RKVDEC,
298 .cap_fbc = 0,
299 .cap_4k = 0,
300 .cap_8k = 0,
301 .cap_colmv_compress = 1,
302 .cap_hw_h265_rps = 0,
303 .cap_hw_vp9_prob = 0,
304 .cap_jpg_pp_out = 0,
305 .cap_10bit = 0,
306 .cap_down_scale = 0,
307 .cap_lmt_linebuf = 1,
308 .cap_core_num = 1,
309 .cap_hw_jpg_fix = 0,
310 .reserved = 0,
311 };
312
313 static const MppDecHwCap vdpu341_h264 = {
314 .cap_coding = HAVE_AVC,
315 .type = VPU_CLIENT_RKVDEC,
316 .cap_fbc = 0,
317 .cap_4k = 1,
318 .cap_8k = 0,
319 .cap_colmv_compress = 1,
320 .cap_hw_h265_rps = 0,
321 .cap_hw_vp9_prob = 0,
322 .cap_jpg_pp_out = 0,
323 .cap_10bit = 0,
324 .cap_down_scale = 0,
325 .cap_lmt_linebuf = 1,
326 .cap_core_num = 1,
327 .cap_hw_jpg_fix = 0,
328 .reserved = 0,
329 };
330
331 /* vdpu34x support AFBC_V2 output */
332 static const MppDecHwCap vdpu34x = {
333 .cap_coding = CAP_CODING_VDPU341,
334 .type = VPU_CLIENT_RKVDEC,
335 .cap_fbc = 2,
336 .cap_4k = 1,
337 .cap_8k = 1,
338 .cap_colmv_compress = 1,
339 .cap_hw_h265_rps = 1,
340 .cap_hw_vp9_prob = 1,
341 .cap_jpg_pp_out = 0,
342 .cap_10bit = 1,
343 .cap_down_scale = 0,
344 .cap_lmt_linebuf = 0,
345 .cap_core_num = 1,
346 .cap_hw_jpg_fix = 0,
347 .reserved = 0,
348 };
349
350 static const MppDecHwCap vdpu38x = {
351 .cap_coding = CAP_CODING_VDPU381,
352 .type = VPU_CLIENT_RKVDEC,
353 .cap_fbc = 2,
354 .cap_4k = 1,
355 .cap_8k = 1,
356 .cap_colmv_compress = 1,
357 .cap_hw_h265_rps = 1,
358 .cap_hw_vp9_prob = 1,
359 .cap_jpg_pp_out = 0,
360 .cap_10bit = 1,
361 .cap_down_scale = 1,
362 .cap_lmt_linebuf = 0,
363 .cap_core_num = 2,
364 .cap_hw_jpg_fix = 0,
365 .reserved = 0,
366 };
367
368 static const MppDecHwCap vdpu382a = {
369 .cap_coding = CAP_CODING_VDPU381,
370 .type = VPU_CLIENT_RKVDEC,
371 .cap_fbc = 2,
372 .cap_4k = 1,
373 .cap_8k = 1,
374 .cap_colmv_compress = 1,
375 .cap_hw_h265_rps = 1,
376 .cap_hw_vp9_prob = 1,
377 .cap_jpg_pp_out = 0,
378 .cap_10bit = 1,
379 .cap_down_scale = 1,
380 .cap_lmt_linebuf = 0,
381 .cap_core_num = 1,
382 .cap_hw_jpg_fix = 0,
383 .reserved = 0,
384 };
385
386 static const MppDecHwCap vdpu382 = {
387 .cap_coding = CAP_CODING_VDPU382,
388 .type = VPU_CLIENT_RKVDEC,
389 .cap_fbc = 2,
390 .cap_4k = 1,
391 .cap_8k = 1,
392 .cap_colmv_compress = 1,
393 .cap_hw_h265_rps = 1,
394 .cap_hw_vp9_prob = 1,
395 .cap_jpg_pp_out = 0,
396 .cap_10bit = 1,
397 .cap_down_scale = 1,
398 .cap_lmt_linebuf = 0,
399 .cap_core_num = 1,
400 .cap_hw_jpg_fix = 0,
401 .reserved = 0,
402 };
403
404 static const MppDecHwCap vdpu382_lite = {
405 .cap_coding = CAP_CODING_VDPU341,
406 .type = VPU_CLIENT_RKVDEC,
407 .cap_fbc = 0,
408 .cap_4k = 1,
409 .cap_8k = 1,
410 .cap_colmv_compress = 0,
411 .cap_hw_h265_rps = 1,
412 .cap_hw_vp9_prob = 1,
413 .cap_jpg_pp_out = 0,
414 .cap_10bit = 0,
415 .cap_down_scale = 1,
416 .cap_lmt_linebuf = 0,
417 .cap_core_num = 1,
418 .cap_hw_jpg_fix = 0,
419 .reserved = 0,
420 };
421
422 static const MppDecHwCap vdpu383 = {
423 .cap_coding = CAP_CODING_VDPU383,
424 .type = VPU_CLIENT_RKVDEC,
425 .cap_fbc = 2,
426 .cap_4k = 1,
427 .cap_8k = 1,
428 .cap_colmv_compress = 1,
429 .cap_hw_h265_rps = 1,
430 .cap_hw_vp9_prob = 1,
431 .cap_jpg_pp_out = 0,
432 .cap_10bit = 1,
433 .cap_down_scale = 1,
434 .cap_lmt_linebuf = 0,
435 .cap_core_num = 1,
436 .cap_hw_jpg_fix = 0,
437 .reserved = 0,
438 };
439
440 static const MppDecHwCap vdpu384a = {
441 .cap_coding = CAP_CODING_VDPU384A,
442 .type = VPU_CLIENT_RKVDEC,
443 .cap_fbc = 0,
444 .cap_4k = 1,
445 .cap_8k = 1,
446 .cap_colmv_compress = 1,
447 .cap_hw_h265_rps = 1,
448 .cap_hw_vp9_prob = 0,
449 .cap_jpg_pp_out = 0,
450 .cap_10bit = 1,
451 .cap_down_scale = 1,
452 .cap_lmt_linebuf = 0,
453 .cap_core_num = 1,
454 .cap_hw_jpg_fix = 0,
455 .reserved = 0,
456 };
457
458 static const MppDecHwCap avspd = {
459 .cap_coding = CAP_CODING_AVSPD,
460 .type = VPU_CLIENT_AVSPLUS_DEC,
461 .cap_fbc = 0,
462 .cap_4k = 0,
463 .cap_8k = 0,
464 .cap_colmv_compress = 0,
465 .cap_hw_h265_rps = 0,
466 .cap_hw_vp9_prob = 0,
467 .cap_jpg_pp_out = 0,
468 .cap_10bit = 0,
469 .cap_down_scale = 0,
470 .cap_lmt_linebuf = 1,
471 .cap_core_num = 1,
472 .cap_hw_jpg_fix = 0,
473 .reserved = 0,
474 };
475
476 static const MppDecHwCap rkjpegd = {
477 .cap_coding = HAVE_MJPEG,
478 .type = VPU_CLIENT_JPEG_DEC,
479 .cap_fbc = 0,
480 .cap_4k = 1,
481 .cap_8k = 0,
482 .cap_colmv_compress = 0,
483 .cap_hw_h265_rps = 0,
484 .cap_hw_vp9_prob = 0,
485 .cap_jpg_pp_out = 0,
486 .cap_10bit = 0,
487 .cap_down_scale = 0,
488 .cap_lmt_linebuf = 0,
489 .cap_core_num = 1,
490 .cap_hw_jpg_fix = 1,
491 .reserved = 0,
492 };
493
494 static const MppDecHwCap av1d = {
495 .cap_coding = CAP_CODING_AV1D,
496 .type = VPU_CLIENT_AV1DEC,
497 .cap_fbc = 1,
498 .cap_4k = 1,
499 .cap_8k = 0,
500 .cap_colmv_compress = 0,
501 .cap_hw_h265_rps = 0,
502 .cap_hw_vp9_prob = 0,
503 .cap_jpg_pp_out = 0,
504 .cap_10bit = 0,
505 .cap_down_scale = 0,
506 .cap_lmt_linebuf = 1,
507 .cap_core_num = 1,
508 .cap_hw_jpg_fix = 0,
509 .reserved = 0,
510 };
511
512 static const MppEncHwCap vepu1 = {
513 .cap_coding = CAP_CODING_VEPU1,
514 .type = VPU_CLIENT_VEPU1,
515 .cap_fbc = 0,
516 .cap_4k = 0,
517 .cap_8k = 0,
518 .cap_hw_osd = 0,
519 .cap_hw_roi = 0,
520 .reserved = 0,
521 };
522
523 static const MppEncHwCap vepu2 = {
524 .cap_coding = CAP_CODING_VEPU1,
525 .type = VPU_CLIENT_VEPU2,
526 .cap_fbc = 0,
527 .cap_4k = 0,
528 .cap_8k = 0,
529 .cap_hw_osd = 0,
530 .cap_hw_roi = 0,
531 .reserved = 0,
532 };
533
534 static const MppEncHwCap vepu2_no_vp8 = {
535 .cap_coding = HAVE_AVC | HAVE_MJPEG,
536 .type = VPU_CLIENT_VEPU2,
537 .cap_fbc = 0,
538 .cap_4k = 0,
539 .cap_8k = 0,
540 .cap_hw_osd = 0,
541 .cap_hw_roi = 0,
542 .reserved = 0,
543 };
544
545 static const MppEncHwCap vepu2_no_jpeg = {
546 .cap_coding = HAVE_AVC | HAVE_VP8,
547 .type = VPU_CLIENT_VEPU2,
548 .cap_fbc = 0,
549 .cap_4k = 0,
550 .cap_8k = 0,
551 .cap_hw_osd = 0,
552 .cap_hw_roi = 0,
553 .reserved = 0,
554 };
555
556 static const MppEncHwCap vepu2_jpeg = {
557 .cap_coding = HAVE_MJPEG,
558 .type = VPU_CLIENT_VEPU2,
559 .cap_fbc = 0,
560 .cap_4k = 0,
561 .cap_8k = 0,
562 .cap_hw_osd = 0,
563 .cap_hw_roi = 0,
564 .reserved = 0,
565 };
566
567 static const MppEncHwCap vepu2_jpeg_enhanced = {
568 .cap_coding = HAVE_MJPEG,
569 .type = VPU_CLIENT_VEPU2_JPEG,
570 .cap_fbc = 0,
571 .cap_4k = 1,
572 .cap_8k = 0,
573 .cap_hw_osd = 0,
574 .cap_hw_roi = 0,
575 .reserved = 0,
576 };
577
578 static const MppEncHwCap vepu22 = {
579 .cap_coding = CAP_CODING_HEVC,
580 .type = VPU_CLIENT_VEPU22,
581 .cap_fbc = 0,
582 .cap_4k = 0,
583 .cap_8k = 0,
584 .cap_hw_osd = 0,
585 .cap_hw_roi = 0,
586 .reserved = 0,
587 };
588
589 static const MppEncHwCap vepu540p = {
590 .cap_coding = HAVE_AVC,
591 .type = VPU_CLIENT_RKVENC,
592 .cap_fbc = 0,
593 .cap_4k = 0,
594 .cap_8k = 0,
595 .cap_hw_osd = 1,
596 .cap_hw_roi = 1,
597 .reserved = 0,
598 };
599
600 static const MppEncHwCap vepu541 = {
601 .cap_coding = CAP_CODING_VEPU54X,
602 .type = VPU_CLIENT_RKVENC,
603 .cap_fbc = 1,
604 .cap_4k = 1,
605 .cap_8k = 0,
606 .cap_hw_osd = 1,
607 .cap_hw_roi = 1,
608 .reserved = 0,
609 };
610
611 /* vepu540 support both AFBC_V1 and AFBC_V2 input */
612 static const MppEncHwCap vepu540 = {
613 .cap_coding = CAP_CODING_VEPU54X,
614 .type = VPU_CLIENT_RKVENC,
615 .cap_fbc = 0x1 | 0x2,
616 .cap_4k = 0,
617 .cap_8k = 0,
618 .cap_hw_osd = 1,
619 .cap_hw_roi = 1,
620 .reserved = 0,
621 };
622
623 /* vepu58x */
624 static const MppEncHwCap vepu58x = {
625 .cap_coding = CAP_CODING_VEPU54X,
626 .type = VPU_CLIENT_RKVENC,
627 .cap_fbc = 0x1 | 0x2,
628 .cap_4k = 1,
629 .cap_8k = 1,
630 .cap_hw_osd = 1,
631 .cap_hw_roi = 1,
632 .reserved = 0,
633 };
634
635 static const MppEncHwCap vepu540c = {
636 .cap_coding = CAP_CODING_VEPU540C,
637 .type = VPU_CLIENT_RKVENC,
638 .cap_fbc = 0x1 | 0x2,
639 .cap_4k = 0,
640 .cap_8k = 0,
641 .cap_hw_osd = 0,
642 .cap_hw_roi = 1,
643 .reserved = 0,
644 };
645
646 static const MppEncHwCap vepu540c_no_hevc = {
647 .cap_coding = (HAVE_AVC | HAVE_MJPEG),
648 .type = VPU_CLIENT_RKVENC,
649 .cap_fbc = 0,
650 .cap_4k = 1,
651 .cap_8k = 1,
652 .cap_hw_osd = 0,
653 .cap_hw_roi = 1,
654 .reserved = 0,
655 };
656
657 static const MppEncHwCap vepu510 = {
658 .cap_coding = CAP_CODING_VEPU54X,
659 .type = VPU_CLIENT_RKVENC,
660 .cap_fbc = 0,
661 .cap_4k = 1,
662 .cap_8k = 1,
663 .cap_hw_osd = 0,
664 .cap_hw_roi = 1,
665 .reserved = 0,
666 };
667
668 static const MppEncHwCap vepu511 = {
669 .cap_coding = CAP_CODING_VEPU511,
670 .type = VPU_CLIENT_RKVENC,
671 .cap_fbc = 2,
672 .cap_4k = 1,
673 .cap_8k = 0,
674 .cap_hw_osd = 1,
675 .cap_hw_roi = 1,
676 .reserved = 0,
677 };
678
679 static const MppEncHwCap rkjpege_vpu720 = {
680 .cap_coding = HAVE_MJPEG,
681 .type = VPU_CLIENT_JPEG_ENC,
682 .cap_fbc = 0,
683 .cap_4k = 1,
684 .cap_8k = 1,
685 .cap_hw_osd = 0,
686 .cap_hw_roi = 0,
687 .reserved = 0,
688 };
689
690 /*
691 * NOTE:
692 * vpu1 = vdpu1 + vepu1
693 * vpu2 = vdpu2 + vepu2
694 */
695 static const MppSocInfo mpp_soc_infos[] = {
696 { /*
697 * rk3036 has
698 * 1 - vdpu1
699 * 2 - RK hevc decoder
700 * rk3036 do NOT have encoder
701 */
702 "rk3036",
703 ROCKCHIP_SOC_RK3036,
704 HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_HEVC_DEC,
705 { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
706 { NULL, NULL, NULL, NULL, },
707 },
708 { /* rk3066 has vpu1 only */
709 "rk3066",
710 ROCKCHIP_SOC_RK3066,
711 HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1,
712 { &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, NULL, },
713 { &vepu1, NULL, NULL, NULL, },
714 },
715 { /* rk3188 has vpu1 only */
716 "rk3188",
717 ROCKCHIP_SOC_RK3188,
718 HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1,
719 { &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, NULL, },
720 { &vepu1, NULL, NULL, NULL, },
721 },
722 { /*
723 * rk3288 has
724 * 1 - vpu1 with 2160p AVC decoder
725 * 2 - RK hevc 4K decoder
726 */
727 "rk3288",
728 ROCKCHIP_SOC_RK3288,
729 HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
730 { &rk_hevc, &vdpu1_2160p, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
731 { &vepu1, NULL, NULL, NULL, },
732 },
733 { /*
734 * rk3126 has
735 * 1 - vpu1
736 * 2 - RK hevc 1080p decoder
737 */
738 "rk3126",
739 ROCKCHIP_SOC_RK312X,
740 HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
741 { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
742 { &vepu1, NULL, NULL, NULL, },
743 },
744 { /*
745 * rk3128 has
746 * 1 - vpu1
747 * 2 - RK hevc 1080p decoder
748 */
749 "rk3128",
750 ROCKCHIP_SOC_RK312X,
751 HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
752 { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
753 { &vepu1, NULL, NULL, NULL, },
754 },
755 { /*
756 * rk3128h has
757 * 1 - vpu2
758 * 2 - RK H.264/H.265 1080p@60fps decoder
759 * NOTE: rk3128H do NOT have jpeg encoder
760 */
761 "rk3128h",
762 ROCKCHIP_SOC_RK3128H,
763 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
764 { &vdpu341_lite_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
765 { &vepu2_no_jpeg, NULL, NULL, NULL, },
766 },
767 { /*
768 * rk3368 has
769 * 1 - vpu1
770 * 2 - RK hevc 4K decoder
771 */
772 "rk3368",
773 ROCKCHIP_SOC_RK3368,
774 HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
775 { &rk_hevc, &vdpu1_2160p, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
776 { &vepu1, NULL, NULL, NULL, },
777 },
778 { /*
779 * rk3399 has
780 * 1 - vpu2
781 * 2 - H.264/H.265/VP9 4K decoder
782 */
783 "rk3399",
784 ROCKCHIP_SOC_RK3399,
785 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
786 { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
787 { &vepu2, NULL, NULL, NULL, },
788 },
789 { /*
790 * rk3328 has codec:
791 * 1 - vpu2
792 * 2 - RK H.264/H.265/VP9 4K decoder
793 * 4 - H.265 encoder
794 */
795 "rk3328",
796 ROCKCHIP_SOC_RK3328,
797 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_VEPU22,
798 { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
799 { &vepu2, &vepu22, NULL, NULL, },
800 },
801 { /*
802 * rk3228 have codec:
803 * 1 - vpu2
804 * 2 - RK H.264/H.265 4K decoder
805 * NOTE: rk3228 do NOT have jpeg encoder
806 */
807 "rk3228",
808 ROCKCHIP_SOC_RK3228,
809 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
810 { &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
811 { &vepu2_no_jpeg, NULL, NULL, NULL, },
812 },
813 { /*
814 * rk3228h has
815 * 1 - vpu2
816 * 2 - RK H.264/H.265 4K decoder
817 * 3 - avs+ decoder
818 * 4 - H.265 1080p encoder
819 * rk3228h first for string matching
820 */
821 "rk3228h",
822 ROCKCHIP_SOC_RK3228H,
823 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_AVSDEC | HAVE_VEPU22,
824 { &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, &avspd, NULL, NULL, },
825 { &vepu2_no_jpeg, &vepu22, NULL, NULL, },
826 },
827 { /*
828 * rk3229 has
829 * 1 - vpu2
830 * 2 - H.264/H.265/VP9 4K decoder
831 */
832 "rk3229",
833 ROCKCHIP_SOC_RK3229,
834 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
835 { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
836 { &vepu2, NULL, NULL, NULL, },
837 },
838 { /*
839 * rv1108 has codec:
840 * 1 - vpu2 for jpeg encoder and decoder
841 * 2 - RK H.264 4K decoder
842 * 3 - RK H.264 4K encoder
843 */
844 "rv1108",
845 ROCKCHIP_SOC_RV1108,
846 HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC,
847 { &vdpu2_jpeg, &vdpu341_h264, NULL, NULL, NULL, NULL, },
848 { &vepu2_jpeg, &vepu540p, NULL, NULL, },
849 },
850 { /*
851 * rv1109 has codec:
852 * 1 - vpu2 for jpeg encoder and decoder
853 * 2 - RK H.264/H.265 4K decoder
854 * 3 - RK H.264/H.265 4K encoder
855 */
856 "rv1109",
857 ROCKCHIP_SOC_RV1109,
858 HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC,
859 { &vdpu2_jpeg_fix, &vdpu341_lite, NULL, NULL, NULL, NULL, },
860 { &vepu2_jpeg, &vepu541, NULL, NULL, },
861 },
862 { /*
863 * rv1126 has codec:
864 * 1 - vpu2 for jpeg encoder and decoder
865 * 2 - RK H.264/H.265 4K decoder
866 * 3 - RK H.264/H.265 4K encoder
867 */
868 "rv1126",
869 ROCKCHIP_SOC_RV1126,
870 HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC,
871 { &vdpu2_jpeg_fix, &vdpu341_lite, NULL, NULL, NULL, NULL, },
872 { &vepu2_jpeg, &vepu541, NULL, NULL, },
873 },
874 { /*
875 * rk3326 has
876 * 1 - vpu2
877 * 2 - RK hevc 1080p decoder
878 */
879 "rk3326",
880 ROCKCHIP_SOC_RK3326,
881 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_HEVC_DEC,
882 { &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp_fix, NULL, NULL, NULL, },
883 { &vepu2, NULL, NULL, NULL, },
884 },
885 { /*
886 * px30 has
887 * 1 - vpu2
888 * 2 - RK hevc 1080p decoder
889 */
890 "px30",
891 ROCKCHIP_SOC_RK3326,
892 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_HEVC_DEC,
893 { &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp_fix, NULL, NULL, NULL, },
894 { &vepu2, NULL, NULL, NULL, },
895 },
896 { /*
897 * px30 has vpu2 only
898 */
899 "rk1808",
900 ROCKCHIP_SOC_RK1808,
901 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2,
902 { &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, NULL, },
903 { &vepu2, NULL, NULL, NULL, },
904 },
905 { /*
906 * rk3566/rk3567/rk3568 has codec:
907 * 1 - vpu2 for jpeg encoder and decoder
908 * 2 - RK H.264/H.265/VP9 4K decoder
909 * 3 - RK H.264/H.265 4K encoder
910 * 3 - RK jpeg decoder
911 */
912 "rk3566",
913 ROCKCHIP_SOC_RK3566,
914 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
915 { &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp_fix, NULL, NULL, },
916 { &vepu540, &vepu2_no_vp8, NULL, NULL, },
917 },
918 { /*
919 * rk3566/rk3567/rk3568 has codec:
920 * 1 - vpu2 for jpeg encoder and decoder
921 * 2 - RK H.264/H.265/VP9 4K decoder
922 * 3 - RK H.264/H.265 4K encoder
923 * 3 - RK jpeg decoder
924 */
925 "rk3567",
926 ROCKCHIP_SOC_RK3567,
927 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
928 { &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp_fix, NULL, NULL, },
929 { &vepu540, &vepu2_no_vp8, NULL, NULL, },
930 },
931 { /*
932 * rk3566/rk3567/rk3568 has codec:
933 * 1 - vpu2 for jpeg encoder and decoder
934 * 2 - RK H.264/H.265/VP9 4K decoder
935 * 3 - RK H.264/H.265 4K encoder
936 * 3 - RK jpeg decoder
937 */
938 "rk3568",
939 ROCKCHIP_SOC_RK3568,
940 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
941 { &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp_fix, NULL, NULL, },
942 { &vepu540, &vepu2_no_vp8, NULL, NULL, },
943 },
944 { /*
945 * rk3588 has codec:
946 * 1 - vpu2 for jpeg/vp8 encoder and decoder
947 * 2 - RK H.264/H.265/VP9 8K decoder
948 * 3 - RK H.264/H.265 8K encoder
949 * 4 - RK jpeg decoder
950 */
951 "rk3588",
952 ROCKCHIP_SOC_RK3588,
953 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC |
954 HAVE_JPEG_DEC | HAVE_AV1DEC | HAVE_AVSDEC | HAVE_VEPU2_JPEG,
955 { &vdpu38x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp_fix, &av1d, &avspd},
956 { &vepu58x, &vepu2, &vepu2_jpeg_enhanced, NULL, },
957 },
958 { /*
959 * rk3528 has codec:
960 * 1 - vpu2 for jpeg/vp8 decoder
961 * 2 - RK H.264/H.265 4K decoder
962 * 3 - RK H.264/H.265 1080P encoder
963 * 4 - RK jpeg decoder
964 */
965 "rk3528",
966 ROCKCHIP_SOC_RK3528,
967 HAVE_RKVDEC | HAVE_RKVENC | HAVE_VDPU2 | HAVE_JPEG_DEC | HAVE_AVSDEC,
968 { &vdpu382, &rkjpegd, &vdpu2, &avspd, NULL, NULL, },
969 { &vepu540c, NULL, NULL, NULL, },
970 },
971 { /*
972 * rk3528a has codec:
973 * 1 - vpu2 for jpeg/vp8 decoder
974 * 2 - RK H.264/H.265/VP9 4K decoder
975 * 3 - RK H.264/H.265 1080P encoder
976 * 4 - RK jpeg decoder
977 */
978 "rk3528a",
979 ROCKCHIP_SOC_RK3528,
980 HAVE_RKVDEC | HAVE_RKVENC | HAVE_VDPU2 | HAVE_JPEG_DEC | HAVE_AVSDEC,
981 { &vdpu382a, &rkjpegd, &vdpu2, &avspd, NULL, NULL, },
982 { &vepu540c, NULL, NULL, NULL, },
983 },
984 { /*
985 * rk3562 has codec:
986 * 1 - RK H.264/H.265/VP9 4K decoder
987 * 2 - RK H.264 1080P encoder
988 * 3 - RK jpeg decoder
989 */
990 "rk3562",
991 ROCKCHIP_SOC_RK3562,
992 HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
993 { &vdpu382_lite, &rkjpegd, NULL, NULL, NULL, NULL, },
994 { &vepu540c_no_hevc, NULL, NULL, NULL, },
995 },
996 { /*
997 * rk3576 has codec:
998 * 1 - RK H.264/H.265/VP9/AVS2/AV1 8K decoder
999 * 2 - RK H.264/H.265 8K encoder
1000 * 3 - RK jpeg decoder/encoder
1001 */
1002 "rk3576",
1003 ROCKCHIP_SOC_RK3576,
1004 HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC | HAVE_JPEG_ENC,
1005 { &vdpu383, &rkjpegd, NULL, NULL, NULL, NULL},
1006 { &vepu510, &rkjpege_vpu720, NULL, NULL},
1007 },
1008 { /*
1009 * rv1126b has codec:
1010 * 1 - RK H.264/H.265 4K decoder
1011 * 2 - RK H.264/H.265/jpeg 4K encoder
1012 * 3 - RK jpeg decoder
1013 */
1014 "rv1126b",
1015 ROCKCHIP_SOC_RV1126B,
1016 HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
1017 { &vdpu384a, &rkjpegd, NULL, NULL, NULL, NULL},
1018 { &vepu511, NULL, NULL, NULL},
1019 },
1020 };
1021
1022 static const MppSocInfo mpp_soc_default = {
1023 "unknown",
1024 ROCKCHIP_SOC_AUTO,
1025 HAVE_VDPU2 | HAVE_VEPU2 | HAVE_VDPU1 | HAVE_VEPU1,
1026 { &vdpu2, &vdpu1, NULL, NULL, },
1027 { &vepu2, &vepu1, NULL, NULL, },
1028 };
1029
read_soc_name(char * name,rk_s32 size)1030 static void read_soc_name(char *name, rk_s32 size)
1031 {
1032 const char *path = "/proc/device-tree/compatible";
1033 char *ptr = NULL;
1034 rk_s32 fd = open(path, O_RDONLY);
1035
1036 if (fd < 0) {
1037 mpp_err("open %s error\n", path);
1038 } else {
1039 ssize_t soc_name_len = 0;
1040
1041 snprintf(name, size - 1, "unknown");
1042 soc_name_len = read(fd, name, size - 1);
1043 if (soc_name_len > 0) {
1044 name[soc_name_len] = '\0';
1045 /* replacing the termination character to space */
1046 for (ptr = name;; ptr = name) {
1047 ptr += strnlen(name, size);
1048 if (ptr >= name + soc_name_len - 1)
1049 break;
1050 *ptr = ' ';
1051 }
1052
1053 mpp_dbg_platform("chip name: %s\n", name);
1054 }
1055
1056 close(fd);
1057 }
1058 }
1059
check_soc_info(const char * soc_name)1060 static const MppSocInfo *check_soc_info(const char *soc_name)
1061 {
1062 rk_s32 i;
1063
1064 for (i = MPP_ARRAY_ELEMS(mpp_soc_infos) - 1; i >= 0; i--) {
1065 const char *compatible = mpp_soc_infos[i].compatible;
1066
1067 if (strstr(soc_name, compatible)) {
1068 mpp_dbg_platform("match chip name: %s\n", compatible);
1069 return &mpp_soc_infos[i];
1070 }
1071 }
1072
1073 return NULL;
1074 }
1075
1076 typedef struct MppSocSrv_t {
1077 char soc_name[MAX_SOC_NAME_LENGTH];
1078 const MppSocInfo *soc_info;
1079 rk_u32 dec_coding_cap;
1080 rk_u32 enc_coding_cap;
1081 } MppSocSrv;
1082
1083 static MppSocSrv *srv_soc = NULL;
1084
mpp_soc_srv_init()1085 static void mpp_soc_srv_init()
1086 {
1087 MppSocSrv *srv = srv_soc;
1088 rk_u32 vcodec_type = 0;
1089 rk_u32 i;
1090
1091 if (srv)
1092 return;
1093
1094 srv = mpp_calloc(MppSocSrv, 1);
1095 if (!srv) {
1096 mpp_err_f("failed to allocate soc service\n");
1097 return;
1098 }
1099
1100 srv_soc = srv;
1101
1102 mpp_env_get_u32("mpp_debug", &mpp_debug, 0);
1103
1104 read_soc_name(srv->soc_name, sizeof(srv->soc_name));
1105 srv->soc_info = check_soc_info(srv->soc_name);
1106 if (NULL == srv->soc_info) {
1107 mpp_dbg_platform("use default chip info\n");
1108 srv->soc_info = &mpp_soc_default;
1109 }
1110
1111 for (i = 0; i < MPP_ARRAY_ELEMS(srv->soc_info->dec_caps); i++) {
1112 const MppDecHwCap *cap = srv->soc_info->dec_caps[i];
1113
1114 if (cap && cap->cap_coding) {
1115 srv->dec_coding_cap |= cap->cap_coding;
1116 vcodec_type |= (1 << cap->type);
1117 }
1118 }
1119
1120 for (i = 0; i < MPP_ARRAY_ELEMS(srv->soc_info->enc_caps); i++) {
1121 const MppEncHwCap *cap = srv->soc_info->enc_caps[i];
1122
1123 if (cap && cap->cap_coding) {
1124 srv->enc_coding_cap |= cap->cap_coding;
1125 vcodec_type |= (1 << cap->type);
1126 }
1127 }
1128
1129 mpp_dbg_platform("coding caps: dec %08x enc %08x\n",
1130 srv->dec_coding_cap, srv->enc_coding_cap);
1131 mpp_dbg_platform("vcodec type from cap: %08x, from soc_info %08x\n",
1132 vcodec_type, srv->soc_info->vcodec_type);
1133 mpp_assert(srv->soc_info->vcodec_type == vcodec_type);
1134 }
1135
mpp_soc_srv_deinit()1136 static void mpp_soc_srv_deinit()
1137 {
1138 MPP_FREE(srv_soc);
1139 }
1140
mpp_get_soc_name(void)1141 const char *mpp_get_soc_name(void)
1142 {
1143 MppSocSrv *srv = get_srv_soc();
1144 const char *name = NULL;
1145
1146 if (srv)
1147 name = srv->soc_name;
1148
1149 return name;
1150 }
1151
mpp_get_soc_info(void)1152 const MppSocInfo *mpp_get_soc_info(void)
1153 {
1154 MppSocSrv *srv = get_srv_soc();
1155 const MppSocInfo *info = NULL;
1156
1157 if (srv)
1158 info = srv->soc_info;
1159
1160 return info;
1161 }
1162
mpp_get_soc_type(void)1163 RockchipSocType mpp_get_soc_type(void)
1164 {
1165 MppSocSrv *srv = get_srv_soc();
1166 RockchipSocType type = ROCKCHIP_SOC_AUTO;
1167
1168 if (srv)
1169 type = srv->soc_info->soc_type;
1170
1171 return type;
1172 }
1173
is_valid_cap_coding(rk_u32 cap,MppCodingType coding)1174 static rk_u32 is_valid_cap_coding(rk_u32 cap, MppCodingType coding)
1175 {
1176 rk_s32 index = CODING_TO_IDX(coding);
1177 if (index > 0 && index < 32 && (cap & (rk_u32)(1 << index)))
1178 return 1;
1179
1180 return 0;
1181 }
1182
mpp_check_soc_cap(MppCtxType type,MppCodingType coding)1183 rk_u32 mpp_check_soc_cap(MppCtxType type, MppCodingType coding)
1184 {
1185 MppSocSrv *srv = get_srv_soc();
1186 rk_u32 cap = 0;
1187
1188 if (srv) {
1189 if (type == MPP_CTX_DEC)
1190 cap = srv->dec_coding_cap;
1191 else if (type == MPP_CTX_ENC)
1192 cap = srv->enc_coding_cap;
1193 else
1194 return 0;
1195 }
1196
1197 if (!cap)
1198 return 0;
1199
1200 return is_valid_cap_coding(cap, coding);
1201 }
1202
mpp_get_dec_hw_info_by_client_type(MppClientType client_type)1203 const MppDecHwCap* mpp_get_dec_hw_info_by_client_type(MppClientType client_type)
1204 {
1205 const MppDecHwCap* hw_info = NULL;
1206 const MppSocInfo *info = mpp_get_soc_info();
1207 rk_u32 i = 0;
1208
1209 for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
1210 if (info->dec_caps[i] && info->dec_caps[i]->type == client_type) {
1211 hw_info = info->dec_caps[i];
1212 break;
1213 }
1214 }
1215
1216 return hw_info;
1217 }
1218
1219 MPP_SINGLETON(MPP_SGLN_SOC, mpp_soc, mpp_soc_srv_init, mpp_soc_srv_deinit);
1220