1 /* 2 * Copyright 2016 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __MPP_RC__ 18 #define __MPP_RC__ 19 20 #include "rk_venc_cmd.h" 21 22 #include "mpp_list.h" 23 24 /* 25 * mpp rate control contain common caculation methd 26 * 27 * 1. MppData - data statistic struct 28 * size - max valid data number 29 * len - valid data number 30 * pos - current load/store position 31 * val - buffer array pointer 32 */ 33 typedef struct { 34 RK_S32 size; 35 RK_S32 len; 36 RK_S32 pos; 37 RK_S32 *val; 38 } MppData; 39 40 /* 41 * 2. Proportion Integration Differentiation (PID) control 42 */ 43 typedef struct { 44 RK_S32 p; 45 RK_S32 i; 46 RK_S32 d; 47 RK_S32 coef_p; 48 RK_S32 coef_i; 49 RK_S32 coef_d; 50 RK_S32 div; 51 RK_S32 len; 52 RK_S32 count; 53 } MppPIDCtx; 54 55 /* 56 * MppRateControl has three steps work: 57 * 58 * 1. translate user requirement to bit rate parameters 59 * 2. calculate target bit from bit parameters 60 * 3. calculate qstep from target bit 61 * 62 * That is user setting -> target bit -> qstep. 63 * 64 * This struct will be used in both controller and hal. 65 * EncImpl provide step 1 and step 2. Hal provide step 3. 66 * 67 */ 68 typedef enum MppEncGopMode_e { 69 /* gop == 0 */ 70 MPP_GOP_ALL_INTER, 71 /* gop == 1 */ 72 MPP_GOP_ALL_INTRA, 73 /* gop < fps */ 74 MPP_GOP_SMALL, 75 /* gop >= fps */ 76 MPP_GOP_LARGE, 77 MPP_GOP_MODE_BUTT, 78 } MppEncGopMode; 79 80 typedef enum RC_PARAM_OPS { 81 RC_RECORD_REAL_BITS, 82 RC_RECORD_QP_SUM, 83 RC_RECORD_QP_MIN, 84 RC_RECORD_QP_MAX, 85 RC_RECORD_SET_QP, 86 RC_RECORD_REAL_QP, 87 RC_RECORD_SSE_SUM, 88 RC_RECORD_WIN_LEN 89 } RC_PARAM_OPS; 90 91 typedef struct RecordNode_t { 92 struct list_head list; 93 /* @frm_cnt starts from ONE */ 94 RK_U32 frm_cnt; 95 RK_U32 bps; 96 RK_U32 fps; 97 RK_S32 gop; 98 RK_S32 bits_per_pic; 99 RK_S32 bits_per_intra; 100 RK_S32 bits_per_inter; 101 RK_U32 tgt_bits; 102 RK_U32 bit_min; 103 RK_U32 bit_max; 104 RK_U32 real_bits; 105 RK_S32 acc_intra_bits_in_fps; 106 RK_S32 acc_inter_bits_in_fps; 107 RK_S32 last_fps_bits; 108 float last_intra_percent; 109 110 /* hardware result */ 111 RK_S32 qp_sum; 112 RK_S64 sse_sum; 113 RK_S32 set_qp; 114 RK_S32 qp_min; 115 RK_S32 qp_max; 116 RK_S32 real_qp; 117 RK_S32 wlen; 118 } RecordNode; 119 120 #ifdef __cplusplus 121 extern "C" { 122 #endif 123 124 MPP_RET mpp_data_init(MppData **p, RK_S32 len); 125 void mpp_data_deinit(MppData *p); 126 void mpp_data_update(MppData *p, RK_S32 val); 127 RK_S32 mpp_data_avg(MppData *p, RK_S32 len, RK_S32 num, RK_S32 denorm); 128 129 void mpp_pid_reset(MppPIDCtx *p); 130 void mpp_pid_set_param(MppPIDCtx *p, RK_S32 coef_p, RK_S32 coef_i, RK_S32 coef_d, RK_S32 div, RK_S32 len); 131 void mpp_pid_update(MppPIDCtx *p, RK_S32 val); 132 RK_S32 mpp_pid_calc(MppPIDCtx *ctx); 133 134 #ifdef __cplusplus 135 } 136 #endif 137 138 #endif /* __MPP_RC__ */ 139