1 /*
2 * Copyright 2015 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_h265e_v541"
18
19 #include <string.h>
20 #include <math.h>
21 #include <limits.h>
22
23 #include "mpp_env.h"
24 #include "mpp_mem.h"
25 #include "mpp_soc.h"
26 #include "mpp_common.h"
27 #include "mpp_device.h"
28 #include "mpp_frame_impl.h"
29
30 #include "h265e_syntax_new.h"
31 #include "hal_h265e_debug.h"
32 #include "hal_h265e_stream_amend.h"
33 #include "hal_h265e_vepu541_reg.h"
34 #include "hal_h265e_vepu54x_reg_l2.h"
35 #include "vepu541_common.h"
36 #include "vepu5xx_common.h"
37 #include "rkv_enc_def.h"
38 #include "mpp_enc_hal.h"
39 #include "hal_bufs.h"
40 #include "mpp_enc_ref.h"
41
42 #define hal_h265e_err(fmt, ...) \
43 do {\
44 mpp_err_f(fmt, ## __VA_ARGS__);\
45 } while (0)
46 #define VEPU541_L2_SIZE 768
47
48 #define TILE_BUF_SIZE MPP_ALIGN(128 * 1024, 256)
49
50 typedef struct vepu541_h265_fbk_t {
51 RK_U32 hw_status; /* 0:corret, 1:error */
52 RK_U32 qp_sum;
53 RK_U32 out_strm_size;
54 RK_U32 out_hw_strm_size;
55 RK_S64 sse_sum;
56 RK_U32 st_lvl64_inter_num;
57 RK_U32 st_lvl32_inter_num;
58 RK_U32 st_lvl16_inter_num;
59 RK_U32 st_lvl8_inter_num;
60 RK_U32 st_lvl32_intra_num;
61 RK_U32 st_lvl16_intra_num;
62 RK_U32 st_lvl8_intra_num;
63 RK_U32 st_lvl4_intra_num;
64 RK_U32 st_cu_num_qp[52];
65 RK_U32 st_madp;
66 RK_U32 st_madi;
67 RK_U32 st_mb_num;
68 RK_U32 st_ctu_num;
69 } vepu541_h265_fbk;
70
71 typedef struct H265eV541HalContext_t {
72 MppEncHalApi api;
73 MppDev dev;
74 void *regs;
75 void *l2_regs;
76 void *reg_out;
77
78 vepu541_h265_fbk feedback;
79 void *dump_files;
80 RK_U32 frame_cnt_gen_ready;
81
82 RK_S32 frame_type;
83 RK_S32 last_frame_type;
84
85 /* @frame_cnt starts from ZERO */
86 RK_U32 frame_cnt;
87 Vepu5xxOsdCfg osd_cfg;
88 MppEncROICfg *roi_data;
89 MppEncROICfg2 *roi_data2;
90 Vepu541RoiCfg *roi_buf_tmp;
91 MppBufferGroup roi_grp;
92 MppBuffer roi_buf;
93 RK_U32 roi_buf_size;
94 MppBuffer qpmap;
95
96 MppEncCfgSet *cfg;
97
98 MppBufferGroup tile_grp;
99 MppBuffer hw_tile_buf[2];
100
101 RK_U32 enc_mode;
102 RK_U32 frame_size;
103 RK_S32 max_buf_cnt;
104 RK_S32 hdr_status;
105 void *input_fmt;
106 RK_U8 *src_buf;
107 RK_U8 *dst_buf;
108 RK_S32 buf_size;
109 RK_U32 frame_num;
110 HalBufs dpb_bufs;
111 RK_U32 is_vepu540;
112 RK_S32 fbc_header_len;
113 } H265eV541HalContext;
114
115 static RK_U32 aq_thd_default[16] = {
116 0, 0, 0, 0,
117 3, 3, 5, 5,
118 8, 8, 8, 15,
119 15, 20, 25, 35
120 };
121
122 static RK_S32 aq_qp_dealt_default[16] = {
123 -8, -7, -6, -5,
124 -4, -3, -2, -1,
125 0, 1, 2, 3,
126 4, 5, 7, 8,
127 };
128
129 static RK_U16 lvl32_intra_cst_thd[4] = {2, 6, 16, 36};
130
131 static RK_U16 lvl16_intra_cst_thd[4] = {2, 6, 16, 36};
132
133 static RK_U8 lvl32_intra_cst_wgt[8] = {23, 22, 21, 20, 22, 24, 26};
134
135 static RK_U8 lvl16_intra_cst_wgt[8] = {17, 17, 17, 18, 17, 18, 18};
136
137 static RK_U16 atr_thd[4] = {0, 0, 0, 0};
138
139 static RK_U8 lvl16_4_atr_wgt[12] = {0};
140
141 //RK_U16 atf_thd[14] = {0, 4, 0, 4, 0, 4, 0, 4, 0, 4, 16, 16, 16, 16}; /*thd 4, sad 4, wgt 6*/
142 static RK_U16 atf_thd[14] = {4, 36, 4, 36, 4, 36, 4, 36, 0, 4, 22, 22, 22, 22}; /*thd 4, sad 4, wgt 6*/
143
144 static RK_U16 atf_sad_ofst[4] = {0, 0, 0, 0};
145
vepu54x_h265_setup_hal_bufs(H265eV541HalContext * ctx)146 static MPP_RET vepu54x_h265_setup_hal_bufs(H265eV541HalContext *ctx)
147 {
148 MPP_RET ret = MPP_OK;
149 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
150 RK_U32 frame_size;
151 VepuFmt input_fmt = VEPU5xx_FMT_YUV420P;
152 RK_S32 mb_wd64, mb_h64;
153 MppEncRefCfg ref_cfg = ctx->cfg->ref_cfg;
154 MppEncPrepCfg *prep = &ctx->cfg->prep;
155 RK_S32 old_max_cnt = ctx->max_buf_cnt;
156 RK_S32 new_max_cnt = 2;
157
158 hal_h265e_enter();
159
160 mb_wd64 = (prep->width + 63) / 64;
161 mb_h64 = (prep->height + 63) / 64 + 1;
162
163 frame_size = MPP_ALIGN(prep->width, 16) * MPP_ALIGN(prep->height, 16);
164 vepu5xx_set_fmt(fmt, ctx->cfg->prep.format);
165 input_fmt = (VepuFmt)fmt->format;
166 switch (input_fmt) {
167 case VEPU5xx_FMT_YUV400:
168 break;
169 case VEPU5xx_FMT_YUV420P:
170 case VEPU5xx_FMT_YUV420SP: {
171 frame_size = frame_size * 3 / 2;
172 } break;
173 case VEPU5xx_FMT_YUV422P:
174 case VEPU5xx_FMT_YUV422SP:
175 case VEPU5xx_FMT_YUYV422:
176 case VEPU5xx_FMT_UYVY422:
177 case VEPU5xx_FMT_BGR565: {
178 frame_size *= 2;
179 } break;
180 case VEPU5xx_FMT_BGR888: {
181 frame_size *= 3;
182 } break;
183 case VEPU5xx_FMT_BGRA8888: {
184 frame_size *= 4;
185 } break;
186 default: {
187 hal_h265e_err("invalid src color space: %d\n", input_fmt);
188 return MPP_NOK;
189 }
190 }
191
192 if (ref_cfg) {
193 MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
194 new_max_cnt = MPP_MAX(new_max_cnt, info->dpb_size + 1);
195 }
196
197 if (frame_size > ctx->frame_size || new_max_cnt > old_max_cnt) {
198 size_t size[3] = {0};
199
200 hal_bufs_deinit(ctx->dpb_bufs);
201 hal_bufs_init(&ctx->dpb_bufs);
202
203 ctx->fbc_header_len = MPP_ALIGN(((mb_wd64 * mb_h64) << 6), SZ_8K);
204 size[0] = ctx->fbc_header_len + ((mb_wd64 * mb_h64) << 12) * 3 / 2; //fbc_h + fbc_b
205 size[1] = (mb_wd64 * mb_h64 << 8);
206 size[2] = MPP_ALIGN(mb_wd64 * mb_h64 * 16 * 4, 256);
207 new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
208
209 hal_h265e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
210 ctx->frame_size, frame_size, old_max_cnt, new_max_cnt);
211
212 hal_bufs_setup(ctx->dpb_bufs, new_max_cnt, 3, size);
213
214 ctx->frame_size = frame_size;
215 ctx->max_buf_cnt = new_max_cnt;
216 }
217 hal_h265e_leave();
218 return ret;
219 }
220
vepu540_h265_set_l2_regs(H265eV54xL2RegSet * reg)221 static void vepu540_h265_set_l2_regs(H265eV54xL2RegSet *reg)
222 {
223 reg->pre_intra_cla0_B0.pre_intra_cla0_m0 = 10;
224 reg->pre_intra_cla0_B0.pre_intra_cla0_m1 = 11;
225 reg->pre_intra_cla0_B0.pre_intra_cla0_m2 = 12;
226 reg->pre_intra_cla0_B0.pre_intra_cla0_m3 = 13;
227 reg->pre_intra_cla0_B0.pre_intra_cla0_m4 = 14;
228 reg->pre_intra_cla0_B1.pre_intra_cla0_m5 = 9;
229 reg->pre_intra_cla0_B1.pre_intra_cla0_m6 = 15;
230 reg->pre_intra_cla0_B1.pre_intra_cla0_m7 = 8;
231 reg->pre_intra_cla0_B1.pre_intra_cla0_m8 = 16;
232 reg->pre_intra_cla0_B1.pre_intra_cla0_m9 = 7;
233
234 reg->pre_intra_cla1_B0.pre_intra_cla1_m0 = 10;
235 reg->pre_intra_cla1_B0.pre_intra_cla1_m1 = 9;
236 reg->pre_intra_cla1_B0.pre_intra_cla1_m2 = 8;
237 reg->pre_intra_cla1_B0.pre_intra_cla1_m3 = 7;
238 reg->pre_intra_cla1_B0.pre_intra_cla1_m4 = 6;
239 reg->pre_intra_cla1_B1.pre_intra_cla1_m5 = 11;
240 reg->pre_intra_cla1_B1.pre_intra_cla1_m6 = 5;
241 reg->pre_intra_cla1_B1.pre_intra_cla1_m7 = 12;
242 reg->pre_intra_cla1_B1.pre_intra_cla1_m8 = 4;
243 reg->pre_intra_cla1_B1.pre_intra_cla1_m9 = 13;
244
245 reg->pre_intra_cla2_B0.pre_intra_cla2_m0 = 18;
246 reg->pre_intra_cla2_B0.pre_intra_cla2_m1 = 17;
247 reg->pre_intra_cla2_B0.pre_intra_cla2_m2 = 16;
248 reg->pre_intra_cla2_B0.pre_intra_cla2_m3 = 15;
249 reg->pre_intra_cla2_B0.pre_intra_cla2_m4 = 14;
250 reg->pre_intra_cla2_B1.pre_intra_cla2_m5 = 19;
251 reg->pre_intra_cla2_B1.pre_intra_cla2_m6 = 13;
252 reg->pre_intra_cla2_B1.pre_intra_cla2_m7 = 20;
253 reg->pre_intra_cla2_B1.pre_intra_cla2_m8 = 12;
254 reg->pre_intra_cla2_B1.pre_intra_cla2_m9 = 21;
255
256 reg->pre_intra_cla3_B0.pre_intra_cla3_m0 = 18;
257 reg->pre_intra_cla3_B0.pre_intra_cla3_m1 = 19;
258 reg->pre_intra_cla3_B0.pre_intra_cla3_m2 = 20;
259 reg->pre_intra_cla3_B0.pre_intra_cla3_m3 = 21;
260 reg->pre_intra_cla3_B0.pre_intra_cla3_m4 = 22;
261 reg->pre_intra_cla3_B1.pre_intra_cla3_m5 = 17;
262 reg->pre_intra_cla3_B1.pre_intra_cla3_m6 = 23;
263 reg->pre_intra_cla3_B1.pre_intra_cla3_m7 = 16;
264 reg->pre_intra_cla3_B1.pre_intra_cla3_m8 = 24;
265 reg->pre_intra_cla3_B1.pre_intra_cla3_m9 = 15;
266
267 reg->pre_intra_cla4_B0.pre_intra_cla4_m0 = 25;
268 reg->pre_intra_cla4_B0.pre_intra_cla4_m1 = 26;
269 reg->pre_intra_cla4_B0.pre_intra_cla4_m2 = 24;
270 reg->pre_intra_cla4_B0.pre_intra_cla4_m3 = 23;
271 reg->pre_intra_cla4_B0.pre_intra_cla4_m4 = 22;
272 reg->pre_intra_cla4_B1.pre_intra_cla4_m5 = 27;
273 reg->pre_intra_cla4_B1.pre_intra_cla4_m6 = 21;
274 reg->pre_intra_cla4_B1.pre_intra_cla4_m7 = 28;
275 reg->pre_intra_cla4_B1.pre_intra_cla4_m8 = 20;
276 reg->pre_intra_cla4_B1.pre_intra_cla4_m9 = 29;
277 ;
278 reg->pre_intra_cla5_B0.pre_intra_cla5_m0 = 27;
279 reg->pre_intra_cla5_B0.pre_intra_cla5_m1 = 26;
280 reg->pre_intra_cla5_B0.pre_intra_cla5_m2 = 28;
281 reg->pre_intra_cla5_B0.pre_intra_cla5_m3 = 29;
282 reg->pre_intra_cla5_B0.pre_intra_cla5_m4 = 30;
283 reg->pre_intra_cla5_B1.pre_intra_cla5_m5 = 25;
284 reg->pre_intra_cla5_B1.pre_intra_cla5_m6 = 31;
285 reg->pre_intra_cla5_B1.pre_intra_cla5_m7 = 24;
286 reg->pre_intra_cla5_B1.pre_intra_cla5_m8 = 32;
287 reg->pre_intra_cla5_B1.pre_intra_cla5_m9 = 23;
288 ;
289 reg->pre_intra_cla6_B0.pre_intra_cla6_m0 = 34;
290 reg->pre_intra_cla6_B0.pre_intra_cla6_m1 = 33;
291 reg->pre_intra_cla6_B0.pre_intra_cla6_m2 = 32;
292 reg->pre_intra_cla6_B0.pre_intra_cla6_m3 = 31;
293 reg->pre_intra_cla6_B0.pre_intra_cla6_m4 = 30;
294 reg->pre_intra_cla6_B1.pre_intra_cla6_m5 = 2 ;
295 reg->pre_intra_cla6_B1.pre_intra_cla6_m6 = 29;
296 reg->pre_intra_cla6_B1.pre_intra_cla6_m7 = 3 ;
297 reg->pre_intra_cla6_B1.pre_intra_cla6_m8 = 28;
298 reg->pre_intra_cla6_B1.pre_intra_cla6_m9 = 4 ;
299 ;
300 reg->pre_intra_cla7_B0.pre_intra_cla7_m0 = 34;
301 reg->pre_intra_cla7_B0.pre_intra_cla7_m1 = 2 ;
302 reg->pre_intra_cla7_B0.pre_intra_cla7_m2 = 3 ;
303 reg->pre_intra_cla7_B0.pre_intra_cla7_m3 = 4 ;
304 reg->pre_intra_cla7_B0.pre_intra_cla7_m4 = 5 ;
305 reg->pre_intra_cla7_B1.pre_intra_cla7_m5 = 33;
306 reg->pre_intra_cla7_B1.pre_intra_cla7_m6 = 6 ;
307 reg->pre_intra_cla7_B1.pre_intra_cla7_m7 = 32;
308 reg->pre_intra_cla7_B1.pre_intra_cla7_m8 = 7 ;
309 reg->pre_intra_cla7_B1.pre_intra_cla7_m9 = 31;
310 ;
311 reg->pre_intra_cla8_B0.pre_intra_cla8_m0 = 10;
312 reg->pre_intra_cla8_B0.pre_intra_cla8_m1 = 26;
313 reg->pre_intra_cla8_B0.pre_intra_cla8_m2 = 18;
314 reg->pre_intra_cla8_B0.pre_intra_cla8_m3 = 34;
315 reg->pre_intra_cla8_B0.pre_intra_cla8_m4 = 6 ;
316 reg->pre_intra_cla8_B1.pre_intra_cla8_m5 = 14;
317 reg->pre_intra_cla8_B1.pre_intra_cla8_m6 = 22;
318 reg->pre_intra_cla8_B1.pre_intra_cla8_m7 = 30;
319 reg->pre_intra_cla8_B1.pre_intra_cla8_m8 = 2 ;
320 reg->pre_intra_cla8_B1.pre_intra_cla8_m9 = 24;
321 ;
322 reg->pre_intra_cla9_B0.pre_intra_cla9_m0 = 0 ;
323 reg->pre_intra_cla9_B0.pre_intra_cla9_m1 = 0 ;
324 reg->pre_intra_cla9_B0.pre_intra_cla9_m2 = 0 ;
325 reg->pre_intra_cla9_B0.pre_intra_cla9_m3 = 0 ;
326 reg->pre_intra_cla9_B0.pre_intra_cla9_m4 = 0 ;
327 reg->pre_intra_cla9_B1.pre_intra_cla9_m5 = 0 ;
328 reg->pre_intra_cla9_B1.pre_intra_cla9_m6 = 0 ;
329 reg->pre_intra_cla9_B1.pre_intra_cla9_m7 = 0 ;
330 reg->pre_intra_cla9_B1.pre_intra_cla9_m8 = 0 ;
331 reg->pre_intra_cla9_B1.pre_intra_cla9_m9 = 0 ;
332
333 reg->pre_intra_cla10_B0.pre_intra_cla10_m0 = 0;
334 reg->pre_intra_cla10_B0.pre_intra_cla10_m1 = 0;
335 reg->pre_intra_cla10_B0.pre_intra_cla10_m2 = 0;
336 reg->pre_intra_cla10_B0.pre_intra_cla10_m3 = 0;
337 reg->pre_intra_cla10_B0.pre_intra_cla10_m4 = 0;
338 reg->pre_intra_cla10_B1.pre_intra_cla10_m5 = 0;
339 reg->pre_intra_cla10_B1.pre_intra_cla10_m6 = 0;
340 reg->pre_intra_cla10_B1.pre_intra_cla10_m7 = 0;
341 reg->pre_intra_cla10_B1.pre_intra_cla10_m8 = 0;
342 reg->pre_intra_cla10_B1.pre_intra_cla10_m9 = 0;
343
344 reg->pre_intra_cla11_B0.pre_intra_cla11_m0 = 0;
345 reg->pre_intra_cla11_B0.pre_intra_cla11_m1 = 0;
346 reg->pre_intra_cla11_B0.pre_intra_cla11_m2 = 0;
347 reg->pre_intra_cla11_B0.pre_intra_cla11_m3 = 0;
348 reg->pre_intra_cla11_B0.pre_intra_cla11_m4 = 0;
349 reg->pre_intra_cla11_B1.pre_intra_cla11_m5 = 0;
350 reg->pre_intra_cla11_B1.pre_intra_cla11_m6 = 0;
351 reg->pre_intra_cla11_B1.pre_intra_cla11_m7 = 0;
352 reg->pre_intra_cla11_B1.pre_intra_cla11_m8 = 0;
353 reg->pre_intra_cla11_B1.pre_intra_cla11_m9 = 0;
354
355 reg->pre_intra_cla12_B0.pre_intra_cla12_m0 = 0;
356 reg->pre_intra_cla12_B0.pre_intra_cla12_m1 = 0;
357 reg->pre_intra_cla12_B0.pre_intra_cla12_m2 = 0;
358 reg->pre_intra_cla12_B0.pre_intra_cla12_m3 = 0;
359 reg->pre_intra_cla12_B0.pre_intra_cla12_m4 = 0;
360 reg->pre_intra_cla12_B1.pre_intra_cla12_m5 = 0;
361 reg->pre_intra_cla12_B1.pre_intra_cla12_m6 = 0;
362 reg->pre_intra_cla12_B1.pre_intra_cla12_m7 = 0;
363 reg->pre_intra_cla12_B1.pre_intra_cla12_m8 = 0;
364 reg->pre_intra_cla12_B1.pre_intra_cla12_m9 = 0;
365
366 reg->pre_intra_cla13_B0.pre_intra_cla13_m0 = 0;
367 reg->pre_intra_cla13_B0.pre_intra_cla13_m1 = 0;
368 reg->pre_intra_cla13_B0.pre_intra_cla13_m2 = 0;
369 reg->pre_intra_cla13_B0.pre_intra_cla13_m3 = 0;
370 reg->pre_intra_cla13_B0.pre_intra_cla13_m4 = 0;
371 reg->pre_intra_cla13_B1.pre_intra_cla13_m5 = 0;
372 reg->pre_intra_cla13_B1.pre_intra_cla13_m6 = 0;
373 reg->pre_intra_cla13_B1.pre_intra_cla13_m7 = 0;
374 reg->pre_intra_cla13_B1.pre_intra_cla13_m8 = 0;
375 reg->pre_intra_cla13_B1.pre_intra_cla13_m9 = 0;
376
377 reg->pre_intra_cla14_B0.pre_intra_cla14_m0 = 0;
378 reg->pre_intra_cla14_B0.pre_intra_cla14_m1 = 0;
379 reg->pre_intra_cla14_B0.pre_intra_cla14_m2 = 0;
380 reg->pre_intra_cla14_B0.pre_intra_cla14_m3 = 0;
381 reg->pre_intra_cla14_B0.pre_intra_cla14_m4 = 0;
382 reg->pre_intra_cla14_B1.pre_intra_cla14_m5 = 0;
383 reg->pre_intra_cla14_B1.pre_intra_cla14_m6 = 0;
384 reg->pre_intra_cla14_B1.pre_intra_cla14_m7 = 0;
385 reg->pre_intra_cla14_B1.pre_intra_cla14_m8 = 0;
386 reg->pre_intra_cla14_B1.pre_intra_cla14_m9 = 0;
387
388 reg->pre_intra_cla15_B0.pre_intra_cla15_m0 = 0;
389 reg->pre_intra_cla15_B0.pre_intra_cla15_m1 = 0;
390 reg->pre_intra_cla15_B0.pre_intra_cla15_m2 = 0;
391 reg->pre_intra_cla15_B0.pre_intra_cla15_m3 = 0;
392 reg->pre_intra_cla15_B0.pre_intra_cla15_m4 = 0;
393 reg->pre_intra_cla15_B1.pre_intra_cla15_m5 = 0;
394 reg->pre_intra_cla15_B1.pre_intra_cla15_m6 = 0;
395 reg->pre_intra_cla15_B1.pre_intra_cla15_m7 = 0;
396 reg->pre_intra_cla15_B1.pre_intra_cla15_m8 = 0;
397 reg->pre_intra_cla15_B1.pre_intra_cla15_m9 = 0;
398
399 reg->pre_intra_cla16_B0.pre_intra_cla16_m0 = 0;
400 reg->pre_intra_cla16_B0.pre_intra_cla16_m1 = 0;
401 reg->pre_intra_cla16_B0.pre_intra_cla16_m2 = 0;
402 reg->pre_intra_cla16_B0.pre_intra_cla16_m3 = 0;
403 reg->pre_intra_cla16_B0.pre_intra_cla16_m4 = 0;
404 reg->pre_intra_cla16_B1.pre_intra_cla16_m5 = 0;
405 reg->pre_intra_cla16_B1.pre_intra_cla16_m6 = 0;
406 reg->pre_intra_cla16_B1.pre_intra_cla16_m7 = 0;
407 reg->pre_intra_cla16_B1.pre_intra_cla16_m8 = 0;
408 reg->pre_intra_cla16_B1.pre_intra_cla16_m9 = 0;
409
410 reg->i16_sobel_t_hevc.intra_l16_sobel_t0 = 64 ;
411 reg->i16_sobel_t_hevc.intra_l16_sobel_t1 = 200;
412 reg->i16_sobel_a_00_hevc.intra_l16_sobel_a0_qp0 = 32 ;
413 reg->i16_sobel_a_00_hevc.intra_l16_sobel_a0_qp1 = 32 ;
414 reg->i16_sobel_a_00_hevc.intra_l16_sobel_a0_qp2 = 32 ;
415 reg->i16_sobel_a_00_hevc.intra_l16_sobel_a0_qp3 = 32 ;
416 reg->i16_sobel_a_00_hevc.intra_l16_sobel_a0_qp4 = 32 ;
417 reg->i16_sobel_a_01_hevc.intra_l16_sobel_a0_qp5 = 32 ;
418 reg->i16_sobel_a_01_hevc.intra_l16_sobel_a0_qp6 = 32 ;
419 reg->i16_sobel_a_01_hevc.intra_l16_sobel_a0_qp7 = 32 ;
420 reg->i16_sobel_a_01_hevc.intra_l16_sobel_a0_qp8 = 32 ;
421 reg->i16_sobel_b_00_hevc.intra_l16_sobel_b0_qp0 = 0 ;
422 reg->i16_sobel_b_00_hevc.intra_l16_sobel_b0_qp1 = 0 ;
423 reg->i16_sobel_b_01_hevc.intra_l16_sobel_b0_qp2 = 0 ;
424 reg->i16_sobel_b_01_hevc.intra_l16_sobel_b0_qp3 = 0 ;
425 reg->i16_sobel_b_02_hevc.intra_l16_sobel_b0_qp4 = 0 ;
426 reg->i16_sobel_b_02_hevc.intra_l16_sobel_b0_qp5 = 0 ;
427 reg->i16_sobel_b_03_hevc.intra_l16_sobel_b0_qp6 = 0 ;
428 reg->i16_sobel_b_03_hevc.intra_l16_sobel_b0_qp7 = 0 ;
429 reg->i16_sobel_b_04_hevc.intra_l16_sobel_b0_qp8 = 0 ;
430 reg->i16_sobel_c_00_hevc.intra_l16_sobel_c0_qp0 = 13;
431 reg->i16_sobel_c_00_hevc.intra_l16_sobel_c0_qp1 = 13;
432 reg->i16_sobel_c_00_hevc.intra_l16_sobel_c0_qp2 = 13;
433 reg->i16_sobel_c_00_hevc.intra_l16_sobel_c0_qp3 = 13;
434 reg->i16_sobel_c_00_hevc.intra_l16_sobel_c0_qp4 = 13;
435 reg->i16_sobel_c_01_hevc.intra_l16_sobel_c0_qp5 = 13;
436 reg->i16_sobel_c_01_hevc.intra_l16_sobel_c0_qp6 = 13;
437 reg->i16_sobel_c_01_hevc.intra_l16_sobel_c0_qp7 = 13;
438 reg->i16_sobel_c_01_hevc.intra_l16_sobel_c0_qp8 = 13;
439 reg->i16_sobel_d_00_hevc.intra_l16_sobel_d0_qp0 = 23750;
440 reg->i16_sobel_d_00_hevc.intra_l16_sobel_d0_qp1 = 23750;
441 reg->i16_sobel_d_01_hevc.intra_l16_sobel_d0_qp2 = 23750;
442 reg->i16_sobel_d_01_hevc.intra_l16_sobel_d0_qp3 = 23750;
443 reg->i16_sobel_d_02_hevc.intra_l16_sobel_d0_qp4 = 23750;
444 reg->i16_sobel_d_02_hevc.intra_l16_sobel_d0_qp5 = 23750;
445 reg->i16_sobel_d_03_hevc.intra_l16_sobel_d0_qp6 = 23750;
446 reg->i16_sobel_d_03_hevc.intra_l16_sobel_d0_qp7 = 23750;
447 reg->i16_sobel_d_04_hevc.intra_l16_sobel_d0_qp8 = 23750;
448
449 reg->i16_sobel_e_00_17_hevc[0] = 20000;
450 reg->i16_sobel_e_00_17_hevc[2] = 20000;
451 reg->i16_sobel_e_00_17_hevc[4] = 20000;
452 reg->i16_sobel_e_00_17_hevc[6] = 20000;
453 reg->i16_sobel_e_00_17_hevc[8] = 20000;
454 reg->i16_sobel_e_00_17_hevc[10] = 20000;
455 reg->i16_sobel_e_00_17_hevc[12] = 20000;
456 reg->i16_sobel_e_00_17_hevc[14] = 20000;
457 reg->i16_sobel_e_00_17_hevc[16] = 20000;
458 reg->i16_sobel_e_00_17_hevc[1] = 0;
459 reg->i16_sobel_e_00_17_hevc[3] = 0;
460 reg->i16_sobel_e_00_17_hevc[5] = 0;
461 reg->i16_sobel_e_00_17_hevc[7] = 0;
462 reg->i16_sobel_e_00_17_hevc[9] = 0;
463 reg->i16_sobel_e_00_17_hevc[11] = 0;
464 reg->i16_sobel_e_00_17_hevc[13] = 0;
465 reg->i16_sobel_e_00_17_hevc[15] = 0;
466 reg->i16_sobel_e_00_17_hevc[17] = 0;
467
468 reg->i32_sobel_t_00_hevc.intra_l32_sobel_t2 = 640 ;
469 reg->i32_sobel_t_00_hevc.intra_l32_sobel_t3 = 0 ;
470 reg->i32_sobel_t_01_hevc.intra_l32_sobel_t4 = 8 ;
471 reg->i32_sobel_t_02_hevc.intra_l32_sobel_t5 = 100 ;
472 reg->i32_sobel_t_02_hevc.intra_l32_sobel_t6 = 100 ;
473
474 reg->i32_sobel_a_hevc.intra_l32_sobel_a1_qp0 = 18;
475 reg->i32_sobel_a_hevc.intra_l32_sobel_a1_qp1 = 18;
476 reg->i32_sobel_a_hevc.intra_l32_sobel_a1_qp2 = 18;
477 reg->i32_sobel_a_hevc.intra_l32_sobel_a1_qp3 = 18;
478 reg->i32_sobel_a_hevc.intra_l32_sobel_a1_qp4 = 18;
479
480 reg->i32_sobel_b_00_hevc.intra_l32_sobel_b1_qp0 = 0;
481 reg->i32_sobel_b_00_hevc.intra_l32_sobel_b1_qp1 = 0;
482 reg->i32_sobel_b_01_hevc.intra_l32_sobel_b1_qp2 = 0;
483 reg->i32_sobel_b_01_hevc.intra_l32_sobel_b1_qp3 = 0;
484 reg->i32_sobel_b_02_hevc.intra_l32_sobel_b1_qp4 = 0;
485
486 reg->i32_sobel_c_hevc.intra_l32_sobel_c1_qp0 = 18;
487 reg->i32_sobel_c_hevc.intra_l32_sobel_c1_qp1 = 18;
488 reg->i32_sobel_c_hevc.intra_l32_sobel_c1_qp2 = 18;
489 reg->i32_sobel_c_hevc.intra_l32_sobel_c1_qp3 = 18;
490 reg->i32_sobel_c_hevc.intra_l32_sobel_c1_qp4 = 18;
491
492 reg->i32_sobel_d_00_hevc.intra_l32_sobel_d1_qp0 = 0;
493 reg->i32_sobel_d_00_hevc.intra_l32_sobel_d1_qp1 = 0;
494 reg->i32_sobel_d_01_hevc.intra_l32_sobel_d1_qp2 = 0;
495 reg->i32_sobel_d_01_hevc.intra_l32_sobel_d1_qp3 = 0;
496 reg->i32_sobel_d_02_hevc.intra_l32_sobel_d1_qp4 = 0;
497
498 reg->i32_sobel_e_00_09_hevc[0] = 20000;
499 reg->i32_sobel_e_00_09_hevc[2] = 20000;
500 reg->i32_sobel_e_00_09_hevc[4] = 20000;
501 reg->i32_sobel_e_00_09_hevc[6] = 20000;
502 reg->i32_sobel_e_00_09_hevc[8] = 20000;
503
504 reg->i32_sobel_e_00_09_hevc[1] = 0;
505 reg->i32_sobel_e_00_09_hevc[3] = 0;
506 reg->i32_sobel_e_00_09_hevc[5] = 0;
507 reg->i32_sobel_e_00_09_hevc[7] = 0;
508 reg->i32_sobel_e_00_09_hevc[9] = 0;
509 }
vepu541_h265_set_l2_regs(H265eV541HalContext * ctx,H265eV54xL2RegSet * regs)510 static void vepu541_h265_set_l2_regs(H265eV541HalContext *ctx, H265eV54xL2RegSet *regs)
511 {
512 MppEncHwCfg *hw = &ctx->cfg->hw;
513 RK_U32 i;
514
515 memcpy(®s->lvl32_intra_CST_THD0, lvl32_intra_cst_thd, sizeof(lvl32_intra_cst_thd));
516 memcpy(®s->lvl16_intra_CST_THD0, lvl16_intra_cst_thd, sizeof(lvl16_intra_cst_thd));
517 memcpy(®s->lvl32_intra_CST_WGT0, lvl32_intra_cst_wgt, sizeof(lvl32_intra_cst_wgt));
518 memcpy(®s->lvl16_intra_CST_WGT0, lvl16_intra_cst_wgt, sizeof(lvl16_intra_cst_wgt));
519 regs->rdo_quant.quant_f_bias_I = 171;
520 regs->rdo_quant.quant_f_bias_P = 85;
521 memcpy(®s->atr_thd0, atr_thd, sizeof(atr_thd));
522 memcpy(®s->lvl16_atr_wgt, lvl16_4_atr_wgt, sizeof(lvl16_4_atr_wgt));
523 if (!ctx->is_vepu540) {
524 memcpy(®s->thd_541.atf_thd0, atf_thd, sizeof(atf_thd));
525 regs->thd_541.atf_thd0.atf_thd0_i32 = 0;
526 regs->thd_541.atf_thd0.atf_thd1_i32 = 63;
527 regs->thd_541.atf_thd1.atf_thd0_i16 = 0;
528 regs->thd_541.atf_thd1.atf_thd1_i16 = 63;
529 regs->thd_541.atf_sad_thd0.atf_thd0_p64 = 0;
530 regs->thd_541.atf_sad_thd0.atf_thd1_p64 = 63;
531 regs->thd_541.atf_sad_thd1.atf_thd0_p32 = 0;
532 regs->thd_541.atf_sad_thd1.atf_thd1_p32 = 63;
533 regs->thd_541.atf_sad_wgt0.atf_thd0_p16 = 0;
534 regs->thd_541.atf_sad_wgt0.atf_thd1_p16 = 63;
535 } else {
536 memcpy(®s->thd_540.atf_thd0, atf_thd, sizeof(atf_thd));
537 regs->thd_540.atf_thd0.atf_thd0_i32 = 0;
538 regs->thd_540.atf_thd0.atf_thd1_i32 = 63;
539 regs->thd_540.atf_thd1.atf_thd0_i16 = 0;
540 regs->thd_540.atf_thd1.atf_thd1_i16 = 63;
541 regs->thd_540.atf_sad_thd0.atf_thd0_p64 = 0;
542 regs->thd_540.atf_sad_thd0.atf_thd1_p64 = 63;
543 regs->thd_540.atf_sad_thd1.atf_thd0_p32 = 0;
544 regs->thd_540.atf_sad_thd1.atf_thd1_p32 = 63;
545 regs->thd_540.atf_sad_wgt0.atf_thd0_p16 = 0;
546 regs->thd_540.atf_sad_wgt0.atf_thd1_p16 = 63;
547 vepu540_h265_set_l2_regs(regs);
548 }
549
550 if (ctx->cfg->tune.scene_mode == MPP_ENC_SCENE_MODE_IPC) {
551 regs->atf_sad_wgt1.atf_wgt_i16 = 19;
552 regs->atf_sad_wgt1.atf_wgt_i32 = 19;
553 regs->atf_sad_wgt2.atf_wgt_p32 = 13;
554 regs->atf_sad_wgt2.atf_wgt_p64 = 13;
555 regs->atf_sad_ofst0.atf_wgt_p16 = 13;
556 } else {
557 regs->atf_sad_wgt1.atf_wgt_i16 = 16;
558 regs->atf_sad_wgt1.atf_wgt_i32 = 16;
559 regs->atf_sad_wgt2.atf_wgt_p32 = 16;
560 regs->atf_sad_wgt2.atf_wgt_p64 = 16;
561 regs->atf_sad_ofst0.atf_wgt_p16 = 16;
562 }
563
564 memcpy(®s->atf_sad_ofst1, atf_sad_ofst, sizeof(atf_sad_ofst));
565 memcpy(®s->lamd_satd_qp[0], lamd_satd_qp, sizeof(lamd_satd_qp));
566 memcpy(®s->lamd_moda_qp[0], lamd_moda_qp, sizeof(lamd_moda_qp));
567 memcpy(®s->lamd_modb_qp[0], lamd_modb_qp, sizeof(lamd_modb_qp));
568
569 if (ctx->frame_type == INTRA_FRAME) {
570 for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
571 regs->aq_tthd[i] = hw->aq_thrd_i[i];
572 regs->aq_step[i] = hw->aq_step_i[i] & 0x3f;
573 }
574 } else {
575 for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
576 regs->aq_tthd[i] = hw->aq_thrd_p[i];
577 regs->aq_step[i] = hw->aq_step_p[i] & 0x3f;
578 }
579 }
580
581 if (hw->qbias_en) {
582 regs->rdo_quant.quant_f_bias_I = hw->qbias_i;
583 regs->rdo_quant.quant_f_bias_P = hw->qbias_p;
584 }
585
586 MppDevRegWrCfg cfg;
587 cfg.reg = regs;
588 if (ctx->is_vepu540) {
589 cfg.size = sizeof(H265eV54xL2RegSet);
590 } else {
591 cfg.size = VEPU541_L2_SIZE ;
592 }
593 cfg.offset = VEPU541_REG_BASE_L2;
594 mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
595 }
596
hal_h265e_v541_init(void * hal,MppEncHalCfg * cfg)597 MPP_RET hal_h265e_v541_init(void *hal, MppEncHalCfg *cfg)
598 {
599 MPP_RET ret = MPP_OK;
600 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
601
602 mpp_env_get_u32("hal_h265e_debug", &hal_h265e_debug, 0);
603 hal_h265e_enter();
604 ctx->reg_out = mpp_calloc(H265eV541IoctlOutputElem, 1);
605 ctx->regs = mpp_calloc(H265eV541RegSet, 1);
606 ctx->l2_regs = mpp_calloc(H265eV54xL2RegSet, 1);
607 ctx->input_fmt = mpp_calloc(VepuFmtCfg, 1);
608 ctx->cfg = cfg->cfg;
609 hal_bufs_init(&ctx->dpb_bufs);
610
611 ctx->frame_cnt = 0;
612 ctx->frame_cnt_gen_ready = 0;
613 ctx->enc_mode = RKV_ENC_MODE;
614 cfg->type = VPU_CLIENT_RKVENC;
615 ret = mpp_dev_init(&cfg->dev, cfg->type);
616 if (ret) {
617 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
618 return ret;
619 }
620
621 ctx->dev = cfg->dev;
622 {
623 RockchipSocType soc_type = mpp_get_soc_type();
624
625 if (soc_type == ROCKCHIP_SOC_RK3566 || soc_type == ROCKCHIP_SOC_RK3568)
626 ctx->is_vepu540 = 1;
627 }
628
629 ctx->osd_cfg.reg_base = ctx->regs;
630 ctx->osd_cfg.dev = ctx->dev;
631 ctx->osd_cfg.reg_cfg = NULL;
632 ctx->osd_cfg.plt_cfg = &ctx->cfg->plt_cfg;
633 ctx->osd_cfg.osd_data = NULL;
634 ctx->osd_cfg.osd_data2 = NULL;
635
636 ctx->frame_type = INTRA_FRAME;
637
638 { /* setup default hardware config */
639 MppEncHwCfg *hw = &cfg->cfg->hw;
640
641 hw->qp_delta_row_i = 0;
642 hw->qp_delta_row = 1;
643 hw->qbias_i = 171;
644 hw->qbias_p = 85;
645 hw->qbias_en = 0;
646
647 memcpy(hw->aq_thrd_i, aq_thd_default, sizeof(hw->aq_thrd_i));
648 memcpy(hw->aq_thrd_p, aq_thd_default, sizeof(hw->aq_thrd_p));
649 memcpy(hw->aq_step_i, aq_qp_dealt_default, sizeof(hw->aq_step_i));
650 memcpy(hw->aq_step_p, aq_qp_dealt_default, sizeof(hw->aq_step_p));
651 }
652
653 hal_h265e_leave();
654 return ret;
655 }
656
hal_h265e_v541_deinit(void * hal)657 MPP_RET hal_h265e_v541_deinit(void *hal)
658 {
659 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
660 hal_h265e_enter();
661 MPP_FREE(ctx->regs);
662 MPP_FREE(ctx->l2_regs);
663 MPP_FREE(ctx->reg_out);
664 MPP_FREE(ctx->input_fmt);
665 MPP_FREE(ctx->roi_buf_tmp);
666
667 if (ctx->roi_buf) {
668 mpp_buffer_put(ctx->roi_buf);
669 ctx->roi_buf = NULL;
670 }
671 hal_bufs_deinit(ctx->dpb_bufs);
672
673 if (ctx->roi_grp) {
674 mpp_buffer_group_put(ctx->roi_grp);
675 ctx->roi_grp = NULL;
676 }
677
678 if (ctx->hw_tile_buf[0]) {
679 mpp_buffer_put(ctx->hw_tile_buf[0]);
680 ctx->hw_tile_buf[0] = NULL;
681 }
682
683 if (ctx->hw_tile_buf[1]) {
684 mpp_buffer_put(ctx->hw_tile_buf[1]);
685 ctx->hw_tile_buf[1] = NULL;
686 }
687
688 if (ctx->tile_grp) {
689 mpp_buffer_group_put(ctx->tile_grp);
690 ctx->tile_grp = NULL;
691 }
692
693 if (ctx->dev) {
694 mpp_dev_deinit(ctx->dev);
695 ctx->dev = NULL;
696 }
697 hal_h265e_leave();
698 return MPP_OK;
699 }
700
hal_h265e_vepu54x_prepare(void * hal)701 static MPP_RET hal_h265e_vepu54x_prepare(void *hal)
702 {
703 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
704 MppEncPrepCfg *prep = &ctx->cfg->prep;
705
706 hal_h265e_dbg_func("enter %p\n", hal);
707
708 if (prep->change_res) {
709 RK_S32 i;
710
711 // pre-alloc required buffers to reduce first frame delay
712 vepu54x_h265_setup_hal_bufs(ctx);
713 for (i = 0; i < ctx->max_buf_cnt; i++)
714 hal_bufs_get_buf(ctx->dpb_bufs, i);
715
716 prep->change_res = 0;
717 }
718
719 hal_h265e_dbg_func("leave %p\n", hal);
720
721 return MPP_OK;
722 }
723
724 static MPP_RET
vepu541_h265_set_patch_info(MppDev dev,H265eSyntax_new * syn,VepuFmt input_fmt,HalEncTask * task)725 vepu541_h265_set_patch_info(MppDev dev, H265eSyntax_new *syn, VepuFmt input_fmt, HalEncTask *task)
726 {
727 RK_U32 hor_stride = syn->pp.hor_stride;
728 RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height;
729 RK_U32 frame_size = hor_stride * ver_stride;
730 RK_U32 u_offset = 0, v_offset = 0;
731 MPP_RET ret = MPP_OK;
732
733 if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) {
734 u_offset = mpp_frame_get_fbc_offset(task->frame);
735 v_offset = 0;
736 } else {
737 switch (input_fmt) {
738 case VEPU5xx_FMT_YUV420P: {
739 u_offset = frame_size;
740 v_offset = frame_size * 5 / 4;
741 } break;
742 case VEPU5xx_FMT_YUV420SP:
743 case VEPU5xx_FMT_YUV422SP: {
744 u_offset = frame_size;
745 v_offset = frame_size;
746 } break;
747 case VEPU5xx_FMT_YUV422P: {
748 u_offset = frame_size;
749 v_offset = frame_size * 3 / 2;
750 } break;
751 case VEPU5xx_FMT_YUYV422:
752 case VEPU5xx_FMT_UYVY422: {
753 u_offset = 0;
754 v_offset = 0;
755 } break;
756 case VEPU5xx_FMT_BGR565:
757 case VEPU5xx_FMT_BGR888:
758 case VEPU5xx_FMT_BGRA8888: {
759 u_offset = 0;
760 v_offset = 0;
761 } break;
762 default: {
763 hal_h265e_err("unknown color space: %d\n", input_fmt);
764 u_offset = frame_size;
765 v_offset = frame_size * 5 / 4;
766 }
767 }
768 }
769
770 /* input cb addr */
771 if (u_offset) {
772 mpp_dev_set_reg_offset(dev, 71, u_offset);
773 if (ret)
774 mpp_err_f("set input cb addr offset failed %d\n", ret);
775 }
776
777 /* input cr addr */
778 if (v_offset) {
779 mpp_dev_set_reg_offset(dev, 72, v_offset);
780 if (ret)
781 mpp_err_f("set input cr addr offset failed %d\n", ret);
782 }
783
784 mpp_dev_set_reg_offset(dev, 83, mpp_buffer_get_size(task->output));
785 if (ret)
786 mpp_err_f("set output max addr offset failed %d\n", ret);
787
788 return ret;
789 }
790
vepu541_h265_set_roi(void * dst_buf,void * src_buf,RK_S32 w,RK_S32 h)791 MPP_RET vepu541_h265_set_roi(void *dst_buf, void *src_buf, RK_S32 w, RK_S32 h)
792 {
793 Vepu541RoiCfg *src = (Vepu541RoiCfg *)src_buf;
794 Vepu541RoiCfg *dst = (Vepu541RoiCfg *)dst_buf;
795 RK_S32 mb_w = MPP_ALIGN(w, 64) / 64;
796 RK_S32 mb_h = MPP_ALIGN(h, 64) / 64;
797 RK_S32 ctu_line = mb_w;
798 RK_S32 i, j, cu16cnt;
799
800 for (j = 0; j < mb_h; j++) {
801 for ( i = 0; i < mb_w; i++) {
802 RK_S32 ctu_addr = j * ctu_line + i;
803 RK_S32 cu16_num_line = ctu_line * 4;
804 for ( cu16cnt = 0; cu16cnt < 16; cu16cnt++) {
805 RK_S32 cu16_x;
806 RK_S32 cu16_y;
807 RK_S32 cu16_addr_in_frame;
808 cu16_x = cu16cnt & 3;
809 cu16_y = cu16cnt / 4;
810 cu16_x += i * 4;
811 cu16_y += j * 4;
812 cu16_addr_in_frame = cu16_x + cu16_y * cu16_num_line;
813 dst[ctu_addr * 16 + cu16cnt] = src[cu16_addr_in_frame];
814 }
815 }
816 }
817 return MPP_OK;
818 }
819
setup_vepu541_intra_refresh(H265eV541RegSet * regs,H265eV541HalContext * ctx,RK_U32 refresh_idx)820 static MPP_RET setup_vepu541_intra_refresh(H265eV541RegSet *regs, H265eV541HalContext *ctx, RK_U32 refresh_idx)
821 {
822 MPP_RET ret = MPP_OK;
823 RK_U32 h = ctx->cfg->prep.height;
824 RK_U32 w = ctx->cfg->prep.width;
825 MppEncROIRegion *region = NULL;
826 RK_U32 stride_h = MPP_ALIGN(w / 16, 4);
827 RK_U32 stride_v = MPP_ALIGN(h / 16, 4);
828 RK_U32 i = 0;
829 RK_U32 roi_buf_size;
830
831 hal_h265e_dbg_func("enter\n");
832
833 if (!ctx->cfg->rc.refresh_en) {
834 ret = MPP_ERR_VALUE;
835 goto RET;
836 }
837
838 roi_buf_size = vepu541_get_roi_buf_size(w, h);
839 if (ctx->roi_buf_size < roi_buf_size) {
840 if (NULL == ctx->roi_grp)
841 mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
842 if (ctx->roi_buf)
843 mpp_buffer_put(ctx->roi_buf);
844 MPP_FREE(ctx->roi_buf_tmp);
845 ctx->roi_buf_tmp = mpp_calloc_size(Vepu541RoiCfg, roi_buf_size);
846 mpp_buffer_get(ctx->roi_grp, &ctx->roi_buf, roi_buf_size);
847 ctx->roi_buf_size = roi_buf_size;
848 }
849
850 mpp_assert(ctx->roi_buf);
851 mpp_assert(ctx->roi_buf_tmp);
852 RK_S32 fd = mpp_buffer_get_fd(ctx->roi_buf);
853 void *buf = ctx->roi_buf_tmp;
854 void *dst_buf = mpp_buffer_get_ptr(ctx->roi_buf);
855 Vepu541RoiCfg cfg;
856 Vepu541RoiCfg *ptr = (Vepu541RoiCfg *)buf;
857 cfg.force_intra = 0;
858 cfg.reserved = 0;
859 cfg.qp_area_idx = 0;
860 cfg.qp_area_en = 1;
861 cfg.qp_adj = 0;
862 cfg.qp_adj_mode = 0;
863
864 for (i = 0; i < stride_h * stride_v; i++, ptr++)
865 memcpy(ptr, &cfg, sizeof(cfg));
866
867 region = mpp_calloc(MppEncROIRegion, 1);
868
869 if (NULL == region) {
870 mpp_err_f("Failed to calloc for MppEncROIRegion !\n");
871 ret = MPP_ERR_MALLOC;
872 }
873
874 if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_ROW) {
875 region->x = 0;
876 region->w = w;
877 if (refresh_idx > 0) {
878 region->y = refresh_idx * 64 * ctx->cfg->rc.refresh_num - 128;
879 region->h = 64 * ctx->cfg->rc.refresh_num + 128;
880 } else {
881 region->y = refresh_idx * 64 * ctx->cfg->rc.refresh_num;
882 region->h = 64 * ctx->cfg->rc.refresh_num;
883 }
884 regs->me_rnge.cime_srch_v = 1;
885 } else if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_COL) {
886 region->y = 0;
887 region->h = h;
888 if (refresh_idx > 0) {
889 region->x = refresh_idx * 64 * ctx->cfg->rc.refresh_num - 128;
890 region->w = 64 * ctx->cfg->rc.refresh_num + 128;
891 } else {
892 region->x = refresh_idx * 64 * ctx->cfg->rc.refresh_num;
893 region->w = 64 * ctx->cfg->rc.refresh_num;
894 }
895 regs->me_rnge.cime_srch_h = 1;
896 }
897
898 region->intra = 1;
899 region->quality = -ctx->cfg->rc.qp_delta_ip;
900
901 region->area_map_en = 1;
902 region->qp_area_idx = 1;
903 region->abs_qp_en = 0;
904
905 regs->enc_pic.roi_en = 1;
906 regs->roi_addr_hevc = fd;
907 vepu541_set_one_roi(buf, region, w, h);
908 vepu541_h265_set_roi(dst_buf, buf, w, h);
909 mpp_free(region);
910 mpp_buffer_sync_end(ctx->roi_buf);
911
912 RET:
913 hal_h265e_dbg_func("leave, ret %d\n", ret);
914 return ret;
915 }
916
917 static MPP_RET
vepu541_h265_set_roi_regs(H265eV541HalContext * ctx,H265eV541RegSet * regs)918 vepu541_h265_set_roi_regs(H265eV541HalContext *ctx, H265eV541RegSet *regs)
919 {
920 if (ctx->roi_data2) {
921 MppEncROICfg2 *cfg = ( MppEncROICfg2 *)ctx->roi_data2;
922
923 regs->enc_pic.roi_en = 1;
924 regs->roi_addr_hevc = mpp_buffer_get_fd(cfg->base_cfg_buf);
925 } else if (ctx->qpmap) {
926 regs->enc_pic.roi_en = 1;
927 regs->roi_addr_hevc = mpp_buffer_get_fd(ctx->qpmap);
928 } else {
929 MppEncROICfg *cfg = (MppEncROICfg*)ctx->roi_data;
930 RK_U32 h = ctx->cfg->prep.height;
931 RK_U32 w = ctx->cfg->prep.width;
932 RK_U8 *roi_base;
933
934 if (!cfg)
935 return MPP_OK;
936
937 if (cfg->number && cfg->regions) {
938 RK_U32 roi_buf_size = vepu541_get_roi_buf_size(w, h);
939
940 if (!ctx->roi_buf || roi_buf_size != ctx->roi_buf_size) {
941 if (NULL == ctx->roi_grp)
942 mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
943 else if (roi_buf_size != ctx->roi_buf_size) {
944 if (ctx->roi_buf) {
945 mpp_buffer_put(ctx->roi_buf);
946 ctx->roi_buf = NULL;
947 }
948 MPP_FREE(ctx->roi_buf_tmp);
949 mpp_buffer_group_clear(ctx->roi_grp);
950 }
951 mpp_assert(ctx->roi_grp);
952 if (NULL == ctx->roi_buf)
953 mpp_buffer_get(ctx->roi_grp, &ctx->roi_buf, roi_buf_size);
954
955 if (ctx->roi_buf_tmp == NULL)
956 ctx->roi_buf_tmp = (Vepu541RoiCfg*)mpp_malloc(RK_U8, roi_buf_size);
957
958 ctx->roi_buf_size = roi_buf_size;
959 }
960
961 regs->enc_pic.roi_en = 1;
962 regs->roi_addr_hevc = mpp_buffer_get_fd(ctx->roi_buf);
963 roi_base = (RK_U8 *)mpp_buffer_get_ptr(ctx->roi_buf);
964 vepu541_set_roi(ctx->roi_buf_tmp, cfg, w, h);
965 vepu541_h265_set_roi(roi_base, ctx->roi_buf_tmp, w, h);
966 }
967 }
968
969 return MPP_OK;
970 }
971
vepu541_h265_set_rc_regs(H265eV541HalContext * ctx,H265eV541RegSet * regs,HalEncTask * task)972 static MPP_RET vepu541_h265_set_rc_regs(H265eV541HalContext *ctx, H265eV541RegSet *regs, HalEncTask *task)
973 {
974 H265eSyntax_new *syn = (H265eSyntax_new *)task->syntax.data;
975 EncRcTaskInfo *rc_cfg = &task->rc_task->info;
976 MppEncCfgSet *cfg = ctx->cfg;
977 MppEncRcCfg *rc = &cfg->rc;
978 MppEncHwCfg *hw = &cfg->hw;
979 MppEncH265Cfg *h265 = &cfg->h265;
980 RK_S32 mb_wd64, mb_h64;
981 mb_wd64 = (syn->pp.pic_width + 63) / 64;
982 mb_h64 = (syn->pp.pic_height + 63) / 64;
983
984 RK_U32 ctu_target_bits_mul_16 = (rc_cfg->bit_target << 4) / (mb_wd64 * mb_h64);
985 RK_U32 ctu_target_bits;
986 RK_S32 negative_bits_thd, positive_bits_thd;
987
988 if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) {
989 regs->enc_pic.pic_qp = rc_cfg->quality_target;
990 regs->synt_sli1.sli_qp = rc_cfg->quality_target;
991
992 regs->rc_qp.rc_max_qp = rc_cfg->quality_target;
993 regs->rc_qp.rc_min_qp = rc_cfg->quality_target;
994 } else {
995 if (ctu_target_bits_mul_16 >= 0x100000) {
996 ctu_target_bits_mul_16 = 0x50000;
997 }
998 ctu_target_bits = (ctu_target_bits_mul_16 * mb_wd64) >> 4;
999 negative_bits_thd = 0 - 5 * ctu_target_bits / 16;
1000 positive_bits_thd = 5 * ctu_target_bits / 16;
1001
1002 regs->enc_pic.pic_qp = rc_cfg->quality_target;
1003 regs->synt_sli1.sli_qp = rc_cfg->quality_target;
1004 regs->rc_cfg.rc_en = 1;
1005 regs->rc_cfg.aqmode_en = 1;
1006 regs->rc_cfg.qp_mode = 1;
1007
1008 regs->rc_cfg.rc_ctu_num = mb_wd64;
1009
1010 regs->rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ?
1011 hw->qp_delta_row_i : hw->qp_delta_row;
1012 regs->rc_qp.rc_max_qp = rc_cfg->quality_max;
1013 regs->rc_qp.rc_min_qp = rc_cfg->quality_min;
1014 regs->rc_tgt.ctu_ebits = ctu_target_bits_mul_16;
1015
1016 regs->rc_erp0.bits_thd0 = 2 * negative_bits_thd;
1017 regs->rc_erp1.bits_thd1 = negative_bits_thd;
1018 regs->rc_erp2.bits_thd2 = positive_bits_thd;
1019 regs->rc_erp3.bits_thd3 = 2 * positive_bits_thd;
1020 regs->rc_erp4.bits_thd4 = 0x7FFFFFFF;
1021 regs->rc_erp5.bits_thd5 = 0x7FFFFFFF;
1022 regs->rc_erp6.bits_thd6 = 0x7FFFFFFF;
1023 regs->rc_erp7.bits_thd7 = 0x7FFFFFFF;
1024 regs->rc_erp8.bits_thd8 = 0x7FFFFFFF;
1025
1026 regs->rc_adj0.qp_adjust0 = -2;
1027 regs->rc_adj0.qp_adjust1 = -1;
1028 regs->rc_adj0.qp_adjust2 = 0;
1029 regs->rc_adj0.qp_adjust3 = 1;
1030 regs->rc_adj0.qp_adjust4 = 2;
1031 regs->rc_adj1.qp_adjust5 = 0;
1032 regs->rc_adj1.qp_adjust6 = 0;
1033 regs->rc_adj1.qp_adjust7 = 0;
1034 regs->rc_adj1.qp_adjust8 = 0;
1035
1036 regs->qpmap0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min;
1037 regs->qpmap0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max;
1038 regs->qpmap0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min;
1039 regs->qpmap0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max;
1040 regs->qpmap0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;;
1041 regs->qpmap1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max;
1042 regs->qpmap1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;;
1043 regs->qpmap1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max;
1044 regs->qpmap1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;;
1045 regs->qpmap1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max;
1046 regs->qpmap2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;;
1047 regs->qpmap2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max;
1048 regs->qpmap2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;;
1049 regs->qpmap2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max;
1050 regs->qpmap2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;;
1051 regs->qpmap3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max;
1052 regs->qpmap3.qpmap_mode = h265->qpmap_mode;
1053 }
1054 if (ctx->frame_type == INTRA_FRAME) {
1055 regs->enc_pic.rdo_wgt_sel = 0;
1056 } else {
1057 regs->enc_pic.rdo_wgt_sel = 1;
1058 }
1059 return MPP_OK;
1060 }
1061
vepu541_h265_set_pp_regs(VepuFmtCfg * fmt,H265eV541HalContext * ctx,HalEncTask * task)1062 static MPP_RET vepu541_h265_set_pp_regs(VepuFmtCfg *fmt, H265eV541HalContext *ctx, HalEncTask *task)
1063 {
1064 RK_S32 stridey = 0;
1065 RK_S32 stridec = 0;
1066 H265eV541RegSet *regs = ctx->regs;
1067 MppEncPrepCfg *prep_cfg = &ctx->cfg->prep;
1068 MppFrameFormat prep_fmt = prep_cfg->format;
1069
1070 regs->dtrns_map.src_bus_edin = fmt->src_endian;
1071 regs->src_fmt.src_cfmt = fmt->format;
1072 regs->src_fmt.alpha_swap = fmt->alpha_swap;
1073 regs->src_fmt.rbuv_swap = fmt->rbuv_swap;
1074 regs->src_fmt.src_range = fmt->src_range;
1075 regs->src_proc.src_mirr = prep_cfg->mirroring > 0;
1076 regs->src_proc.src_rot = prep_cfg->rotation;
1077
1078 if (!ctx->frame_num && (prep_fmt == MPP_FMT_YUV420SP_VU || prep_fmt == MPP_FMT_YUV422SP_VU))
1079 mpp_logw("Warning: nv21/nv42 fmt not supported, will encode as nv12/nv24.\n");
1080
1081 if (MPP_FRAME_FMT_IS_FBC(prep_fmt)) {
1082 stridey = mpp_frame_get_fbc_hdr_stride(task->frame);
1083 if (!stridey)
1084 stridey = MPP_ALIGN(prep_cfg->hor_stride, 16);
1085 } else if (prep_cfg->hor_stride) {
1086 stridey = prep_cfg->hor_stride;
1087 } else {
1088 if (regs->src_fmt.src_cfmt == VEPU5xx_FMT_BGRA8888)
1089 stridey = prep_cfg->width * 4;
1090 else if (regs->src_fmt.src_cfmt == VEPU5xx_FMT_BGR888)
1091 stridey = prep_cfg->width * 3;
1092 else if (regs->src_fmt.src_cfmt == VEPU5xx_FMT_BGR565 ||
1093 regs->src_fmt.src_cfmt == VEPU5xx_FMT_YUYV422 ||
1094 regs->src_fmt.src_cfmt == VEPU5xx_FMT_UYVY422)
1095 stridey = prep_cfg->width * 2;
1096 }
1097
1098 stridec = (regs->src_fmt.src_cfmt == VEPU5xx_FMT_YUV422SP ||
1099 regs->src_fmt.src_cfmt == VEPU5xx_FMT_YUV420SP) ?
1100 stridey : stridey / 2;
1101
1102 if (regs->src_fmt.src_cfmt < VEPU5xx_FMT_ARGB1555) {
1103 const VepuRgb2YuvCfg *cfg_coeffs = cfg_coeffs = get_rgb2yuv_cfg(prep_cfg->range, prep_cfg->color);
1104
1105 hal_h265e_dbg_simple("input color range %d colorspace %d", prep_cfg->range, prep_cfg->color);
1106
1107 regs->src_udfy.wght_r2y = cfg_coeffs->_2y.r_coeff;
1108 regs->src_udfy.wght_g2y = cfg_coeffs->_2y.g_coeff;
1109 regs->src_udfy.wght_b2y = cfg_coeffs->_2y.b_coeff;
1110
1111 regs->src_udfu.wght_r2u = cfg_coeffs->_2u.r_coeff;
1112 regs->src_udfu.wght_g2u = cfg_coeffs->_2u.g_coeff;
1113 regs->src_udfu.wght_b2u = cfg_coeffs->_2u.b_coeff;
1114
1115 regs->src_udfv.wght_r2v = cfg_coeffs->_2v.r_coeff;
1116 regs->src_udfv.wght_g2v = cfg_coeffs->_2v.g_coeff;
1117 regs->src_udfv.wght_b2v = cfg_coeffs->_2v.b_coeff;
1118
1119 regs->src_udfo.ofst_y = cfg_coeffs->_2y.offset;
1120 regs->src_udfo.ofst_u = cfg_coeffs->_2u.offset;
1121 regs->src_udfo.ofst_v = cfg_coeffs->_2v.offset;
1122
1123 hal_h265e_dbg_simple("use color range %d colorspace %d", cfg_coeffs->dst_range, cfg_coeffs->color);
1124 }
1125
1126 regs->src_strid.src_ystrid = stridey;
1127 regs->src_strid.src_cstrid = stridec;
1128
1129 return MPP_OK;
1130 }
1131
vepu541_h265_set_slice_regs(H265eSyntax_new * syn,H265eV541RegSet * regs)1132 static void vepu541_h265_set_slice_regs(H265eSyntax_new *syn, H265eV541RegSet *regs)
1133 {
1134 regs->synt_sps.smpl_adpt_ofst_en = syn->pp.sample_adaptive_offset_enabled_flag;//slice->m_sps->m_bUseSAO;
1135 regs->synt_sps.num_st_ref_pic = syn->pp.num_short_term_ref_pic_sets;
1136 regs->synt_sps.num_lt_ref_pic = syn->pp.num_long_term_ref_pics_sps;
1137 regs->synt_sps.lt_ref_pic_prsnt = syn->pp.long_term_ref_pics_present_flag;
1138 regs->synt_sps.tmpl_mvp_en = syn->pp.sps_temporal_mvp_enabled_flag;
1139 regs->synt_sps.log2_max_poc_lsb = syn->pp.log2_max_pic_order_cnt_lsb_minus4;
1140 regs->synt_sps.strg_intra_smth = syn->pp.strong_intra_smoothing_enabled_flag;
1141
1142 regs->synt_pps.dpdnt_sli_seg_en = syn->pp.dependent_slice_segments_enabled_flag;
1143 regs->synt_pps.out_flg_prsnt_flg = syn->pp.output_flag_present_flag;
1144 regs->synt_pps.num_extr_sli_hdr = syn->pp.num_extra_slice_header_bits;
1145 regs->synt_pps.sgn_dat_hid_en = syn->pp.sign_data_hiding_enabled_flag;
1146 regs->synt_pps.cbc_init_prsnt_flg = syn->pp.cabac_init_present_flag;
1147 regs->synt_pps.pic_init_qp = syn->pp.init_qp_minus26 + 26;
1148 regs->synt_pps.cu_qp_dlt_en = syn->pp.cu_qp_delta_enabled_flag;
1149 regs->synt_pps.chrm_qp_ofst_prsn = syn->pp.pps_slice_chroma_qp_offsets_present_flag;
1150 regs->synt_pps.lp_fltr_acrs_sli = syn->pp.pps_loop_filter_across_slices_enabled_flag;
1151 regs->synt_pps.dblk_fltr_ovrd_en = syn->pp.deblocking_filter_override_enabled_flag;
1152 regs->synt_pps.lst_mdfy_prsnt_flg = syn->pp.lists_modification_present_flag;
1153 regs->synt_pps.sli_seg_hdr_extn = syn->pp.slice_segment_header_extension_present_flag;
1154 regs->synt_pps.cu_qp_dlt_depth = syn->pp.diff_cu_qp_delta_depth;
1155 regs->synt_pps.lpf_fltr_acrs_til = syn->pp.loop_filter_across_tiles_enabled_flag;
1156
1157 regs->synt_sli0.cbc_init_flg = syn->sp.cbc_init_flg;
1158 regs->synt_sli0.mvd_l1_zero_flg = syn->sp.mvd_l1_zero_flg;
1159 regs->synt_sli0.merge_up_flag = syn->sp.merge_up_flag;
1160 regs->synt_sli0.merge_left_flag = syn->sp.merge_left_flag;
1161 regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
1162
1163 regs->synt_sli0.num_refidx_l1_act = syn->sp.num_refidx_l1_act;
1164 regs->synt_sli0.num_refidx_l0_act = syn->sp.num_refidx_l0_act;
1165
1166 regs->synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd;
1167
1168 regs->synt_sli0.sli_sao_chrm_flg = syn->sp.sli_sao_chrm_flg;
1169 regs->synt_sli0.sli_sao_luma_flg = syn->sp.sli_sao_luma_flg;
1170 regs->synt_sli0.sli_tmprl_mvp_en = syn->sp.sli_tmprl_mvp_en;
1171 regs->enc_pic.tot_poc_num = syn->sp.tot_poc_num;
1172
1173 regs->synt_sli0.pic_out_flg = syn->sp.pic_out_flg;
1174 regs->synt_sli0.sli_type = syn->sp.slice_type;
1175 regs->synt_sli0.sli_rsrv_flg = syn->sp.slice_rsrv_flg;
1176 regs->synt_sli0.dpdnt_sli_seg_flg = syn->sp.dpdnt_sli_seg_flg;
1177 regs->synt_sli0.sli_pps_id = syn->sp.sli_pps_id;
1178 regs->synt_sli0.no_out_pri_pic = syn->sp.no_out_pri_pic;
1179
1180
1181 regs->synt_sli1.sli_tc_ofst_div2 = syn->sp.sli_tc_ofst_div2;;
1182 regs->synt_sli1.sli_beta_ofst_div2 = syn->sp.sli_beta_ofst_div2;
1183 regs->synt_sli1.sli_lp_fltr_acrs_sli = syn->sp.sli_lp_fltr_acrs_sli;
1184 regs->synt_sli1.sli_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis;
1185 regs->synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg;
1186 regs->synt_sli1.sli_cb_qp_ofst = syn->pp.pps_slice_chroma_qp_offsets_present_flag ?
1187 syn->sp.sli_cb_qp_ofst : syn->pp.pps_cb_qp_offset;
1188 regs->synt_sli1.max_mrg_cnd = syn->sp.max_mrg_cnd;
1189
1190 regs->synt_sli1.col_ref_idx = syn->sp.col_ref_idx;
1191 regs->synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg;
1192 regs->synt_sli2_rodr.sli_poc_lsb = syn->sp.sli_poc_lsb;
1193 regs->synt_sli2_rodr.sli_hdr_ext_len = syn->sp.sli_hdr_ext_len;
1194
1195 }
1196
vepu541_h265_set_ref_regs(H265eSyntax_new * syn,H265eV541RegSet * regs)1197 static void vepu541_h265_set_ref_regs(H265eSyntax_new *syn, H265eV541RegSet *regs)
1198 {
1199 regs->synt_ref_mark0.st_ref_pic_flg = syn->sp.st_ref_pic_flg;
1200 regs->synt_ref_mark0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0;
1201 regs->synt_ref_mark0.num_lt_pic = syn->sp.num_lt_pic;
1202
1203 regs->synt_ref_mark1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
1204 regs->synt_ref_mark1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
1205 regs->synt_ref_mark1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0;
1206 regs->synt_ref_mark1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1;
1207 regs->synt_ref_mark1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2;
1208 regs->synt_ref_mark1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
1209 regs->synt_ref_mark1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
1210 regs->synt_ref_mark1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1;
1211 regs->synt_ref_mark1.num_neg_pic = syn->sp.num_neg_pic;
1212 regs->synt_ref_mark1.num_pos_pic = syn->sp.num_pos_pic;
1213
1214 regs->synt_ref_mark1.used_by_s0_flg = syn->sp.used_by_s0_flg;
1215 regs->synt_ref_mark2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10;
1216 regs->synt_ref_mark2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11;
1217 regs->synt_ref_mark3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12;
1218 regs->synt_ref_mark3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13;
1219
1220 regs->synt_ref_mark4.poc_lsb_lt1 = syn->sp.poc_lsb_lt1;
1221 regs->synt_ref_mark5.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1;
1222 regs->synt_ref_mark4.poc_lsb_lt2 = syn->sp.poc_lsb_lt2;
1223 regs->synt_ref_mark1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2;
1224 regs->synt_ref_mark5.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2;
1225 regs->synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0;
1226 regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
1227
1228 return;
1229 }
vepu541_h265_set_me_regs(H265eV541HalContext * ctx,H265eSyntax_new * syn,H265eV541RegSet * regs)1230 static void vepu541_h265_set_me_regs(H265eV541HalContext *ctx, H265eSyntax_new *syn, H265eV541RegSet *regs)
1231 {
1232
1233 RK_U32 cime_w = 11, cime_h = 7;
1234 RK_S32 merangx = (cime_w + 1) * 32;
1235 RK_S32 merangy = (cime_h + 1) * 32;
1236 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6;
1237
1238 if (merangx > 384) {
1239 merangx = 384;
1240 }
1241 if (merangy > 320) {
1242 merangy = 320;
1243 }
1244
1245 if (syn->pp.pic_width < merangx + 60 || syn->pp.pic_width <= 352) {
1246 if (merangx > syn->pp.pic_width ) {
1247 merangx = syn->pp.pic_width;
1248 }
1249 merangx = merangx / 4 * 2;
1250 }
1251
1252 if (syn->pp.pic_height < merangy + 60 || syn->pp.pic_height <= 288) {
1253 if (merangy > syn->pp.pic_height) {
1254 merangy = syn->pp.pic_height;
1255 }
1256 merangy = merangy / 4 * 2;
1257 }
1258
1259 {
1260 RK_S32 merange_x = merangx / 2;
1261 RK_S32 merange_y = merangy / 2;
1262 RK_S32 mxneg = ((-(merange_x << 2)) >> 2) / 4;
1263 RK_S32 myneg = ((-(merange_y << 2)) >> 2) / 4;
1264 RK_S32 mxpos = (((merange_x << 2) - 4) >> 2) / 4;
1265 RK_S32 mypos = (((merange_y << 2) - 4) >> 2) / 4;
1266
1267 mxneg = MPP_MIN(abs(mxneg), mxpos) * 4;
1268 myneg = MPP_MIN(abs(myneg), mypos) * 4;
1269
1270 merangx = mxneg * 2;
1271 merangy = myneg * 2;
1272 }
1273 regs->me_rnge.cime_srch_h = merangx / 32;
1274 regs->me_rnge.cime_srch_v = merangy / 32;
1275
1276 regs->me_rnge.rime_srch_h = 7;
1277 regs->me_rnge.rime_srch_v = 5;
1278 regs->me_rnge.dlt_frm_num = 0x1;
1279
1280 regs->me_cnst.pmv_mdst_h = 5;
1281 regs->me_cnst.pmv_mdst_v = 5;
1282 regs->me_cnst.mv_limit = 0;
1283 regs->me_cnst.mv_num = 2;
1284
1285 if (syn->pp.sps_temporal_mvp_enabled_flag &&
1286 (ctx->frame_type != INTRA_FRAME)) {
1287 if (ctx->last_frame_type == INTRA_FRAME) {
1288 regs->me_cnst.colmv_load = 0;
1289 } else {
1290 regs->me_cnst.colmv_load = 1;
1291 }
1292 regs->me_cnst.colmv_store = 1;
1293 }
1294
1295 if (syn->pp.pic_width > 2688) {
1296 regs->me_ram.cime_rama_h = 12;
1297 } else if (syn->pp.pic_width > 2048) {
1298 regs->me_ram.cime_rama_h = 16;
1299 } else {
1300 regs->me_ram.cime_rama_h = 20;
1301 }
1302
1303 {
1304 RK_S32 swin_scope_wd16 = (regs->me_rnge.cime_srch_h + 3 + 1) / 4 * 2 + 1;
1305 RK_S32 tmpMin = (regs->me_rnge.cime_srch_v + 3) / 4 * 2 + 1;
1306 if (regs->me_ram.cime_rama_h / 4 < tmpMin) {
1307 tmpMin = regs->me_ram.cime_rama_h / 4;
1308 }
1309 regs->me_ram.cime_rama_max =
1310 (pic_wd64 * (tmpMin - 1)) + ((pic_wd64 >= swin_scope_wd16) ? swin_scope_wd16 : pic_wd64 * 2);
1311 }
1312 regs->me_ram.cach_l2_tag = 0x0;
1313
1314 pic_wd64 = pic_wd64 << 6;
1315
1316 if (pic_wd64 <= 512)
1317 regs->me_ram.cach_l2_tag = 0x0;
1318 else if (pic_wd64 <= 1024)
1319 regs->me_ram.cach_l2_tag = 0x1;
1320 else if (pic_wd64 <= 2048)
1321 regs->me_ram.cach_l2_tag = 0x2;
1322 else if (pic_wd64 <= 4096)
1323 regs->me_ram.cach_l2_tag = 0x3;
1324 }
1325
vepu540_h265_set_me_ram(H265eSyntax_new * syn,H265eV541RegSet * regs,RK_U32 index,RK_S32 tile_start_x)1326 static void vepu540_h265_set_me_ram(H265eSyntax_new *syn, H265eV541RegSet *regs,
1327 RK_U32 index, RK_S32 tile_start_x)
1328 {
1329 RK_U32 cime_w = 11, cime_h = 7;
1330 RK_U32 pic_cime_temp = 0;
1331 if (syn->pp.tiles_enabled_flag == 0) {
1332 pic_cime_temp = ((regs->enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 * 64;
1333 regs->me_ram.cime_linebuf_w = pic_cime_temp / 64;
1334 } else {
1335 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6;
1336 RK_S32 tile_ctu_stax = tile_start_x;
1337 RK_S32 tile_ctu_endx = tile_start_x + syn->pp.column_width_minus1[index];
1338 RK_S32 cime_srch_w = regs->me_rnge.cime_srch_h;
1339
1340 if (tile_ctu_stax < (cime_srch_w + 3) / 4) {
1341 if (tile_ctu_endx + 1 + (cime_srch_w + 3) / 4 > pic_wd64)
1342 pic_cime_temp = pic_wd64 * 64;
1343 else
1344 pic_cime_temp = (tile_ctu_endx + 1 + (cime_srch_w + 3) / 4) * 64;
1345 } else {
1346 if (tile_ctu_endx + 1 + (cime_srch_w + 3) / 4 > pic_wd64)
1347 pic_cime_temp = (pic_wd64 - tile_ctu_stax + (cime_srch_w + 3) / 4) * 64;
1348 else
1349 pic_cime_temp = (tile_ctu_endx - tile_ctu_stax + 1 + (cime_srch_w + 3) / 4 * 2) * 64;
1350 }
1351 regs->me_ram.cime_linebuf_w = pic_cime_temp / 64;
1352
1353 }
1354
1355 {
1356
1357 RK_S32 w_temp = 1296;
1358 RK_S32 h_temp = 4;
1359 RK_S32 h_val_0 = 4;
1360 RK_S32 h_val_1 = 24;
1361
1362 while ((w_temp > ((h_temp - h_val_0)*regs->me_ram.cime_linebuf_w * 4 + ((h_val_1 - h_temp) * 4 * 7)))
1363 && (h_temp < 17)) {
1364 h_temp = h_temp + h_val_0;
1365 }
1366 if (w_temp < (RK_S32)((h_temp - h_val_0)*regs->me_ram.cime_linebuf_w * 4 + ((h_val_1 - h_temp) * 4 * 7)))
1367 h_temp = h_temp - h_val_0;
1368
1369 regs->me_ram.cime_rama_h = h_temp;
1370 }
1371
1372 // calc cime_rama_max
1373 {
1374 RK_S32 pic_wd64 = pic_cime_temp / 64;
1375 RK_S32 swin_scope_wd16 = (cime_w + 3 + 1) / 4 * 2 + 1;
1376 RK_S32 tmpMin = (cime_h + 3) / 4 * 2 + 1;
1377 if (regs->me_ram.cime_rama_h / 4 < tmpMin) {
1378 tmpMin = regs->me_ram.cime_rama_h / 4;
1379 }
1380 regs->me_ram.cime_rama_max = (pic_wd64 * (tmpMin - 1)) + ((pic_wd64 >= swin_scope_wd16) ? swin_scope_wd16 : pic_wd64 * 2);
1381 }
1382
1383 hal_h265e_dbg_detail("cime_rama_h %d, cime_rama_max %d, cime_linebuf_w %d",
1384 regs->me_ram.cime_rama_h, regs->me_ram.cime_rama_max, regs->me_ram.cime_linebuf_w);
1385 }
vepu54x_h265_set_hw_address(H265eV541HalContext * ctx,H265eV541RegSet * regs,HalEncTask * task)1386 void vepu54x_h265_set_hw_address(H265eV541HalContext *ctx, H265eV541RegSet *regs, HalEncTask *task)
1387 {
1388 HalEncTask *enc_task = task;
1389 HalBuf *recon_buf, *ref_buf;
1390 MppBuffer md_info_buf = enc_task->md_info;
1391 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
1392
1393 hal_h265e_enter();
1394
1395 regs->adr_srcy_hevc = mpp_buffer_get_fd(enc_task->input);
1396 regs->adr_srcu_hevc = regs->adr_srcy_hevc;
1397 regs->adr_srcv_hevc = regs->adr_srcy_hevc;
1398
1399 recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx);
1400 ref_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.ref_pic.slot_idx);
1401 if (!syn->sp.non_reference_flag) {
1402 regs->rfpw_h_addr_hevc = mpp_buffer_get_fd(recon_buf->buf[0]);
1403 regs->rfpw_b_addr_hevc = regs->rfpw_h_addr_hevc;
1404
1405 mpp_dev_set_reg_offset(ctx->dev, 75, ctx->fbc_header_len);
1406 }
1407
1408 regs->dspw_addr_hevc = mpp_buffer_get_fd(recon_buf->buf[1]);
1409 regs->cmvw_addr_hevc = mpp_buffer_get_fd(recon_buf->buf[2]);
1410 regs->rfpr_h_addr_hevc = mpp_buffer_get_fd(ref_buf->buf[0]);
1411 regs->rfpr_b_addr_hevc = regs->rfpr_h_addr_hevc;
1412 regs->dspr_addr_hevc = mpp_buffer_get_fd(ref_buf->buf[1]);
1413 regs->cmvr_addr_hevc = mpp_buffer_get_fd(ref_buf->buf[2]);
1414
1415 mpp_dev_set_reg_offset(ctx->dev, 77, ctx->fbc_header_len);
1416
1417 if (syn->pp.tiles_enabled_flag) {
1418 if (NULL == ctx->tile_grp)
1419 mpp_buffer_group_get_internal(&ctx->tile_grp, MPP_BUFFER_TYPE_ION);
1420
1421 mpp_assert(ctx->tile_grp);
1422
1423 if (NULL == ctx->hw_tile_buf[0]) {
1424 mpp_buffer_get(ctx->tile_grp, &ctx->hw_tile_buf[0], TILE_BUF_SIZE);
1425 }
1426
1427 if (NULL == ctx->hw_tile_buf[1]) {
1428 mpp_buffer_get(ctx->tile_grp, &ctx->hw_tile_buf[1], TILE_BUF_SIZE);
1429 }
1430
1431 regs->lpfw_addr_hevc = mpp_buffer_get_fd(ctx->hw_tile_buf[0]);
1432 regs->lpfr_addr_hevc = mpp_buffer_get_fd(ctx->hw_tile_buf[1]);
1433 }
1434
1435 if (md_info_buf) {
1436 regs->enc_pic.mei_stor = 1;
1437 regs->meiw_addr_hevc = mpp_buffer_get_fd(md_info_buf);
1438 } else {
1439 regs->enc_pic.mei_stor = 0;
1440 regs->meiw_addr_hevc = 0;
1441 }
1442
1443 regs->bsbb_addr_hevc = mpp_buffer_get_fd(enc_task->output);
1444 /* TODO: stream size relative with syntax */
1445 regs->bsbt_addr_hevc = regs->bsbb_addr_hevc;
1446 regs->bsbr_addr_hevc = regs->bsbb_addr_hevc;
1447 regs->bsbw_addr_hevc = regs->bsbb_addr_hevc;
1448
1449 mpp_dev_set_reg_offset(ctx->dev, 86, mpp_packet_get_length(task->packet));
1450
1451 regs->pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
1452 regs->pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
1453 }
1454
setup_vepu541_split(H265eV541RegSet * regs,MppEncSliceSplit * cfg)1455 static void setup_vepu541_split(H265eV541RegSet *regs, MppEncSliceSplit *cfg)
1456 {
1457 hal_h265e_dbg_func("enter\n");
1458
1459 switch (cfg->split_mode) {
1460 case MPP_ENC_SPLIT_NONE : {
1461 regs->sli_spl.sli_splt = 0;
1462 regs->sli_spl.sli_splt_mode = 0;
1463 regs->sli_spl.sli_splt_cpst = 0;
1464 regs->sli_spl.sli_max_num_m1 = 0;
1465 regs->sli_spl.sli_flsh = 0;
1466 regs->sli_spl.sli_splt_cnum_m1 = 0;
1467
1468 regs->sli_spl_byte.sli_splt_byte = 0;
1469 regs->enc_pic.slen_fifo = 0;
1470 } break;
1471 case MPP_ENC_SPLIT_BY_BYTE : {
1472 regs->sli_spl.sli_splt = 1;
1473 regs->sli_spl.sli_splt_mode = 0;
1474 regs->sli_spl.sli_splt_cpst = 0;
1475 regs->sli_spl.sli_max_num_m1 = 500;
1476 regs->sli_spl.sli_flsh = 1;
1477 regs->sli_spl.sli_splt_cnum_m1 = 0;
1478
1479 regs->sli_spl_byte.sli_splt_byte = cfg->split_arg;
1480 regs->enc_pic.slen_fifo = 0;
1481 } break;
1482 case MPP_ENC_SPLIT_BY_CTU : {
1483 regs->sli_spl.sli_splt = 1;
1484 regs->sli_spl.sli_splt_mode = 1;
1485 regs->sli_spl.sli_splt_cpst = 0;
1486 regs->sli_spl.sli_max_num_m1 = 500;
1487 regs->sli_spl.sli_flsh = 1;
1488 regs->sli_spl.sli_splt_cnum_m1 = cfg->split_arg - 1;
1489
1490 regs->sli_spl_byte.sli_splt_byte = 0;
1491 regs->enc_pic.slen_fifo = 0;
1492 } break;
1493 default : {
1494 mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
1495 } break;
1496 }
1497
1498 hal_h265e_dbg_func("leave\n");
1499 }
1500
hal_h265e_v541_gen_regs(void * hal,HalEncTask * task)1501 MPP_RET hal_h265e_v541_gen_regs(void *hal, HalEncTask *task)
1502 {
1503 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
1504 HalEncTask *enc_task = task;
1505 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
1506 H265eV541RegSet *regs = ctx->regs;
1507 RK_U32 pic_width_align8, pic_height_align8;
1508 RK_S32 pic_wd64, pic_h64;
1509 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
1510 EncFrmStatus *frm_status = &task->rc_task->frm;
1511
1512 hal_h265e_enter();
1513 pic_width_align8 = (syn->pp.pic_width + 7) & (~7);
1514 pic_height_align8 = (syn->pp.pic_height + 7) & (~7);
1515 pic_wd64 = (syn->pp.pic_width + 63) / 64;
1516 pic_h64 = (syn->pp.pic_height + 63) / 64;
1517
1518 hal_h265e_dbg_simple("frame %d | type %d | start gen regs",
1519 ctx->frame_cnt, ctx->frame_type);
1520
1521
1522 memset(regs, 0, sizeof(H265eV541RegSet));
1523 regs->enc_strt.lkt_num = 0;
1524 regs->enc_strt.rkvenc_cmd = ctx->enc_mode;
1525 regs->enc_strt.enc_cke = 1;
1526 regs->enc_clr.safe_clr = 0x0;
1527
1528 regs->lkt_addr.lkt_addr = 0x0;
1529 regs->int_en.enc_done_en = 1;
1530 regs->int_en.lkt_done_en = 1;
1531 regs->int_en.sclr_done_en = 1;
1532 regs->int_en.slc_done_en = 1;
1533 regs->int_en.bsf_ovflw_en = 1;
1534 regs->int_en.brsp_ostd_en = 1;
1535 regs->int_en.wbus_err_en = 1;
1536 regs->int_en.rbus_err_en = 1;
1537 regs->int_en.wdg_en = 0;
1538
1539 regs->enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1;
1540 regs->enc_rsl.pic_wfill = (syn->pp.pic_width & 0x7)
1541 ? (8 - (syn->pp.pic_width & 0x7)) : 0;
1542 regs->enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1;
1543 regs->enc_rsl.pic_hfill = (syn->pp.pic_height & 0x7)
1544 ? (8 - (syn->pp.pic_height & 0x7)) : 0;
1545
1546 regs->enc_pic.enc_stnd = 1; //H265
1547 regs->enc_pic.cur_frm_ref = !syn->sp.non_reference_flag; //current frame will be refered
1548 regs->enc_pic.bs_scp = 1;
1549 regs->enc_pic.node_int = 0;
1550 regs->enc_pic.log2_ctu_num = ceil(log2((double)pic_wd64 * pic_h64));
1551
1552 regs->enc_pic.rdo_wgt_sel = (ctx->frame_type == INTRA_FRAME) ? 0 : 1;
1553
1554 regs->enc_wdg.vs_load_thd = 0;
1555 regs->enc_wdg.rfp_load_thd = 0;
1556
1557 if (ctx->is_vepu540) {
1558 regs->dtrns_cfg_540.cime_dspw_orsd = (ctx->frame_type == INTER_P_FRAME);
1559 regs->dtrns_cfg_540.axi_brsp_cke = 0x0;
1560 } else {
1561 regs->dtrns_cfg_541.cime_dspw_orsd = (ctx->frame_type == INTER_P_FRAME);
1562 regs->dtrns_cfg_541.axi_brsp_cke = 0x0;
1563 }
1564
1565 regs->dtrns_map.lpfw_bus_ordr = 0x0;
1566 regs->dtrns_map.cmvw_bus_ordr = 0x0;
1567 regs->dtrns_map.dspw_bus_ordr = 0x0;
1568 regs->dtrns_map.rfpw_bus_ordr = 0x0;
1569 regs->dtrns_map.src_bus_edin = 0x0;
1570 regs->dtrns_map.meiw_bus_edin = 0x0;
1571 regs->dtrns_map.bsw_bus_edin = 0x7;
1572 regs->dtrns_map.lktr_bus_edin = 0x0;
1573 regs->dtrns_map.roir_bus_edin = 0x0;
1574 regs->dtrns_map.lktw_bus_edin = 0x0;
1575 regs->dtrns_map.afbc_bsize = 0x1;
1576
1577
1578 regs->src_proc.src_mirr = 0;
1579 regs->src_proc.src_rot = 0;
1580 regs->src_proc.txa_en = 1;
1581 regs->src_proc.afbcd_en = (MPP_FRAME_FMT_IS_FBC(syn->pp.mpp_format)) ? 1 : 0;
1582
1583 if (!ctx->is_vepu540)
1584 vepu541_h265_set_patch_info(ctx->dev, syn, (VepuFmt)fmt->format, task);
1585
1586 regs->klut_ofst.chrm_kult_ofst = (ctx->frame_type == INTRA_FRAME) ? 0 : 3;
1587 memcpy(®s->klut_wgt0, &klut_weight[0], sizeof(klut_weight));
1588
1589 regs->adr_srcy_hevc = mpp_buffer_get_fd(enc_task->input);
1590 regs->adr_srcu_hevc = regs->adr_srcy_hevc;
1591 regs->adr_srcv_hevc = regs->adr_srcy_hevc;
1592
1593 setup_vepu541_split(regs, &ctx->cfg->split);
1594
1595 vepu541_h265_set_me_regs(ctx, syn, regs);
1596
1597 regs->rdo_cfg.chrm_special = 1;
1598 regs->rdo_cfg.cu_inter_en = 0xf;
1599 regs->rdo_cfg.cu_intra_en = 0xf;
1600
1601 if (syn->pp.num_long_term_ref_pics_sps) {
1602 regs->rdo_cfg.ltm_col = 0;
1603 regs->rdo_cfg.ltm_idx0l0 = 1;
1604 } else {
1605 regs->rdo_cfg.ltm_col = 0;
1606 regs->rdo_cfg.ltm_idx0l0 = 0;
1607 }
1608
1609 regs->rdo_cfg.chrm_klut_en = 1;
1610 regs->rdo_cfg.seq_scaling_matrix_present_flg = syn->pp.scaling_list_enabled_flag;
1611 regs->synt_nal.nal_unit_type = h265e_get_nal_type(&syn->sp, ctx->frame_type);
1612
1613 vepu54x_h265_set_hw_address(ctx, regs, task);
1614 vepu541_h265_set_pp_regs(fmt, ctx, task);
1615
1616 vepu541_h265_set_rc_regs(ctx, regs, task);
1617
1618 vepu541_h265_set_slice_regs(syn, regs);
1619
1620 vepu541_h265_set_ref_regs(syn, regs);
1621 if (ctx->is_vepu540) {
1622 vepu540_set_osd(&ctx->osd_cfg);
1623 } else {
1624 vepu541_set_osd(&ctx->osd_cfg);
1625 }
1626 /* ROI configure */
1627 vepu541_h265_set_roi_regs(ctx, regs);
1628
1629 if (frm_status->is_i_refresh)
1630 setup_vepu541_intra_refresh(regs, ctx, frm_status->seq_idx % ctx->cfg->rc.gop);
1631
1632 ctx->frame_num++;
1633
1634 hal_h265e_leave();
1635 return MPP_OK;
1636 }
hal_h265e_v540_set_uniform_tile(H265eV541RegSet * regs,H265eSyntax_new * syn,RK_U32 index,RK_S32 tile_start_x)1637 void hal_h265e_v540_set_uniform_tile(H265eV541RegSet *regs, H265eSyntax_new *syn,
1638 RK_U32 index, RK_S32 tile_start_x)
1639 {
1640 if (syn->pp.tiles_enabled_flag) {
1641 RK_S32 mb_h = MPP_ALIGN(syn->pp.pic_height, 64) / 64;
1642 RK_S32 tile_width = syn->pp.column_width_minus1[index] + 1;
1643
1644 regs->tile_cfg.tile_width_m1 = tile_width - 1;
1645 regs->tile_cfg.tile_height_m1 = mb_h - 1;
1646 regs->rc_cfg.rc_ctu_num = tile_width;
1647 regs->tile_cfg.tile_en = syn->pp.tiles_enabled_flag;
1648 regs->tile_pos.tile_x = tile_start_x;
1649 regs->tile_pos.tile_y = 0;
1650 if (index > 0) {
1651 RK_U32 tmp = regs->lpfr_addr_hevc;
1652 regs->lpfr_addr_hevc = regs->lpfw_addr_hevc;
1653 regs->lpfw_addr_hevc = tmp;
1654 }
1655
1656 hal_h265e_dbg_detail("tile_x %d, rc_ctu_num %d, tile_width_m1 %d",
1657 regs->tile_pos.tile_x, regs->rc_cfg.rc_ctu_num,
1658 regs->tile_cfg.tile_width_m1);
1659 }
1660 }
1661
hal_h265e_v540_start(void * hal,HalEncTask * enc_task)1662 MPP_RET hal_h265e_v540_start(void *hal, HalEncTask *enc_task)
1663 {
1664 MPP_RET ret = MPP_OK;
1665 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
1666 RK_U32 length = 0, k = 0;
1667 H265eV541IoctlOutputElem *reg_out = (H265eV541IoctlOutputElem *)ctx->reg_out;
1668 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
1669 RK_U32 title_num = (syn->pp.num_tile_columns_minus1 + 1) * (syn->pp.num_tile_rows_minus1 + 1);
1670 hal_h265e_enter();
1671 RK_U32 stream_len = 0;
1672 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
1673 RK_S32 tile_start_x = 0;
1674
1675 if (enc_task->flags.err) {
1676 hal_h265e_err("enc_task->flags.err %08x, return e arly",
1677 enc_task->flags.err);
1678 return MPP_NOK;
1679 }
1680
1681 for (k = 0; k < title_num; k++) { //v540 no support link list
1682 RK_U32 i;
1683 RK_U32 *regs = (RK_U32*)ctx->regs;
1684 H265eV541RegSet *hw_regs = ctx->regs;
1685 MppDevRegWrCfg cfg;
1686 MppDevRegRdCfg cfg1;
1687
1688 vepu540_h265_set_me_ram(syn, hw_regs, k, tile_start_x);
1689
1690 /* set input info */
1691 vepu541_h265_set_l2_regs(ctx, (H265eV54xL2RegSet*)ctx->l2_regs);
1692 vepu541_h265_set_patch_info(ctx->dev, syn, (VepuFmt)fmt->format, enc_task);
1693 if (title_num > 1)
1694 hal_h265e_v540_set_uniform_tile(hw_regs, syn, k, tile_start_x);
1695 if (k > 0) {
1696 RK_U32 offset = mpp_packet_get_length(enc_task->packet);
1697
1698 offset += stream_len;
1699 hw_regs->bsbb_addr_hevc = mpp_buffer_get_fd(enc_task->output);
1700 hw_regs->bsbw_addr_hevc = hw_regs->bsbb_addr_hevc;
1701 mpp_dev_set_reg_offset(ctx->dev, 86, offset);
1702 mpp_dev_set_reg_offset(ctx->dev, 75, ctx->fbc_header_len);
1703 mpp_dev_set_reg_offset(ctx->dev, 77, ctx->fbc_header_len);
1704 }
1705
1706 cfg.reg = ctx->regs;
1707 cfg.size = sizeof(H265eV541RegSet);
1708 cfg.offset = 0;
1709
1710 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
1711 if (ret) {
1712 mpp_err_f("set register write failed %d\n", ret);
1713 break;
1714 }
1715
1716
1717 cfg1.reg = ®_out->hw_status;
1718 cfg1.size = sizeof(RK_U32);
1719 cfg1.offset = VEPU541_REG_BASE_HW_STATUS;
1720
1721 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
1722 if (ret) {
1723 mpp_err_f("set register read failed %d\n", ret);
1724 break;
1725 }
1726
1727 cfg1.reg = ®_out->st_bsl;
1728 cfg1.size = sizeof(H265eV541IoctlOutputElem) - 4;
1729 cfg1.offset = VEPU541_REG_BASE_STATISTICS;
1730
1731 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
1732 if (ret) {
1733 mpp_err_f("set register read failed %d\n", ret);
1734 break;
1735 }
1736 for (i = 0; i < sizeof(H265eV541RegSet) / 4; i++) {
1737 hal_h265e_dbg_regs("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
1738 }
1739
1740 if (k < title_num - 1) {
1741 vepu541_h265_fbk *fb = &ctx->feedback;
1742 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
1743 if (ret) {
1744 mpp_err_f("send cmd failed %d\n", ret);
1745 break;
1746 }
1747 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
1748
1749 stream_len += reg_out->st_bsl.bs_lgth;
1750 fb->qp_sum += reg_out->st_sse_qp.qp_sum;
1751 fb->out_strm_size += reg_out->st_bsl.bs_lgth;
1752 fb->sse_sum += reg_out->st_sse_l32.sse_l32 +
1753 ((RK_S64)(reg_out->st_sse_qp.sse_h8 & 0xff) << 32);
1754 fb->st_madi += reg_out->st_madi;
1755 fb->st_madp += reg_out->st_madi;
1756 fb->st_mb_num += reg_out->st_mb_num;
1757 fb->st_ctu_num += reg_out->st_ctu_num;
1758
1759 if (ret) {
1760 mpp_err_f("poll cmd failed %d\n", ret);
1761 ret = MPP_ERR_VPUHW;
1762 }
1763
1764 }
1765 tile_start_x += (syn->pp.column_width_minus1[k] + 1);
1766 }
1767
1768 hal_h265e_dbg_detail("vpu client is sending %d regs", length);
1769 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
1770 if (ret) {
1771 mpp_err_f("send cmd failed %d\n", ret);
1772 }
1773 hal_h265e_leave();
1774 return ret;
1775 }
1776
hal_h265e_v541_start(void * hal,HalEncTask * task)1777 MPP_RET hal_h265e_v541_start(void *hal, HalEncTask *task)
1778 {
1779 MPP_RET ret = MPP_OK;
1780 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
1781 RK_U32 length = 0;
1782 HalEncTask *enc_task = task;
1783 H265eV541IoctlOutputElem *reg_out = (H265eV541IoctlOutputElem *)ctx->reg_out;
1784 RK_U32 i;
1785 RK_U32 *regs = (RK_U32*)ctx->regs;
1786 hal_h265e_enter();
1787
1788 if (enc_task->flags.err) {
1789 hal_h265e_err("enc_task->flags.err %08x, return early",
1790 enc_task->flags.err);
1791 return MPP_NOK;
1792 }
1793 vepu541_h265_set_l2_regs(ctx, (H265eV54xL2RegSet*)ctx->l2_regs);
1794
1795 do {
1796 MppDevRegWrCfg cfg;
1797
1798 cfg.reg = ctx->regs;
1799 cfg.size = sizeof(H265eV541RegSet);
1800 cfg.offset = 0;
1801
1802 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
1803 if (ret) {
1804 mpp_err_f("set register write failed %d\n", ret);
1805 break;
1806 }
1807
1808 MppDevRegRdCfg cfg1;
1809
1810 cfg1.reg = ®_out->hw_status;
1811 cfg1.size = sizeof(RK_U32);
1812 cfg1.offset = VEPU541_REG_BASE_HW_STATUS;
1813
1814 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
1815 if (ret) {
1816 mpp_err_f("set register read failed %d\n", ret);
1817 break;
1818 }
1819
1820 cfg1.reg = ®_out->st_bsl;
1821 cfg1.size = sizeof(H265eV541IoctlOutputElem) - 4;
1822 cfg1.offset = VEPU541_REG_BASE_STATISTICS;
1823
1824 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
1825 if (ret) {
1826 mpp_err_f("set register read failed %d\n", ret);
1827 break;
1828 }
1829
1830 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
1831 if (ret) {
1832 mpp_err_f("send cmd failed %d\n", ret);
1833 break;
1834 }
1835 } while (0);
1836
1837 for (i = 0; i < sizeof(H265eV541RegSet) / 4; i++) {
1838 hal_h265e_dbg_regs("set reg[%04d]: 0%08x\n", i, regs[i]);
1839 }
1840
1841 hal_h265e_dbg_detail("vpu client is sending %d regs", length);
1842 hal_h265e_leave();
1843 return ret;
1844 }
1845
hal_h265e_v54x_start(void * hal,HalEncTask * task)1846 MPP_RET hal_h265e_v54x_start(void *hal, HalEncTask *task)
1847 {
1848 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
1849 task->hw_length = 0;
1850 if (ctx->is_vepu540) {
1851 return hal_h265e_v540_start(hal, task);
1852 } else {
1853 return hal_h265e_v541_start(hal, task);
1854 }
1855 return MPP_OK;
1856 }
1857
vepu541_h265_set_feedback(H265eV541HalContext * ctx,HalEncTask * enc_task)1858 static MPP_RET vepu541_h265_set_feedback(H265eV541HalContext *ctx, HalEncTask *enc_task)
1859 {
1860 EncRcTaskInfo *hal_rc_ret = (EncRcTaskInfo *)&enc_task->rc_task->info;
1861 vepu541_h265_fbk *fb = &ctx->feedback;
1862 MppEncCfgSet *cfg = ctx->cfg;
1863 RK_S32 mb64_num = ((cfg->prep.width + 63) / 64) * ((cfg->prep.height + 63) / 64);
1864 RK_S32 mb8_num = (mb64_num << 6);
1865 RK_S32 mb4_num = (mb8_num << 2);
1866
1867 hal_h265e_enter();
1868 H265eV541IoctlOutputElem *elem = (H265eV541IoctlOutputElem *)ctx->reg_out;
1869 RK_U32 hw_status = elem->hw_status;
1870 fb->qp_sum += elem->st_sse_qp.qp_sum;
1871 fb->out_strm_size += elem->st_bsl.bs_lgth;
1872 fb->sse_sum += elem->st_sse_l32.sse_l32 +
1873 ((RK_S64)(elem->st_sse_qp.sse_h8 & 0xff) << 32);
1874
1875 fb->hw_status = hw_status;
1876 hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status);
1877 if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)
1878 hal_h265e_err("RKV_ENC_INT_LINKTABLE_FINISH");
1879
1880 if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH)
1881 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_FRAME_FINISH");
1882
1883 if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)
1884 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_SLICE_FINISH");
1885
1886 if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)
1887 hal_h265e_err("RKV_ENC_INT_SAFE_CLEAR_FINISH");
1888
1889 if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW)
1890 hal_h265e_err("RKV_ENC_INT_BIT_STREAM_OVERFLOW");
1891
1892 if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL)
1893 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_FULL");
1894
1895 if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR)
1896 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_ERROR");
1897
1898 if (hw_status & RKV_ENC_INT_BUS_READ_ERROR)
1899 hal_h265e_err("RKV_ENC_INT_BUS_READ_ERROR");
1900
1901 if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR)
1902 hal_h265e_err("RKV_ENC_INT_TIMEOUT_ERROR");
1903
1904 fb->st_madi += elem->st_madi;
1905 fb->st_madp += elem->st_madp;
1906 fb->st_mb_num += elem->st_mb_num;
1907 fb->st_ctu_num += elem->st_ctu_num;
1908
1909 if (fb->st_mb_num) {
1910 fb->st_madi = fb->st_madi / fb->st_mb_num;
1911 } else {
1912 fb->st_madi = 0;
1913 }
1914 if (fb->st_ctu_num) {
1915 fb->st_madp = fb->st_madp / fb->st_ctu_num;
1916 } else {
1917 fb->st_madp = 0;
1918 }
1919
1920 fb->st_lvl64_inter_num = elem->st_lvl64_inter_num;
1921 fb->st_lvl32_inter_num = elem->st_lvl32_inter_num;
1922 fb->st_lvl32_intra_num = elem->st_lvl32_intra_num;
1923 fb->st_lvl16_inter_num = elem->st_lvl16_inter_num;
1924 fb->st_lvl16_intra_num = elem->st_lvl16_intra_num;
1925 fb->st_lvl8_inter_num = elem->st_lvl8_inter_num;
1926 fb->st_lvl8_intra_num = elem->st_lvl8_intra_num;
1927 fb->st_lvl4_intra_num = elem->st_lvl4_intra_num;
1928 memcpy(&fb->st_cu_num_qp[0], &elem->st_cu_num_qp[0], sizeof(elem->st_cu_num_qp));
1929
1930 hal_rc_ret->madi = fb->st_madi;
1931 hal_rc_ret->madp = fb->st_madp;
1932 hal_rc_ret->bit_real = fb->out_strm_size * 8;
1933
1934 if (mb4_num > 0)
1935 hal_rc_ret->iblk4_prop = ((((fb->st_lvl4_intra_num + fb->st_lvl8_intra_num) << 2) +
1936 (fb->st_lvl16_intra_num << 4) +
1937 (fb->st_lvl32_intra_num << 6)) << 8) / mb4_num;
1938
1939 if (mb64_num > 0) {
1940 /*
1941 hal_cfg[k].inter_lv8_prop = ((fb->st_lvl8_inter_num + (fb->st_lvl16_inter_num << 2) +
1942 (fb->st_lvl32_inter_num << 4) +
1943 (fb->st_lvl64_inter_num << 6)) << 8) / mb8_num;*/
1944
1945 hal_rc_ret->quality_real = fb->qp_sum / mb8_num;
1946 // hal_cfg[k].sse = fb->sse_sum / mb64_num;
1947 }
1948
1949 hal_h265e_leave();
1950
1951 return MPP_OK;
1952 }
1953
1954
hal_h265e_v541_wait(void * hal,HalEncTask * task)1955 MPP_RET hal_h265e_v541_wait(void *hal, HalEncTask *task)
1956 {
1957 MPP_RET ret = MPP_OK;
1958 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
1959 HalEncTask *enc_task = task;
1960 H265eV541IoctlOutputElem *elem = (H265eV541IoctlOutputElem *)ctx->reg_out;
1961 hal_h265e_enter();
1962 if (enc_task->flags.err) {
1963 hal_h265e_err("enc_task->flags.err %08x, return early",
1964 enc_task->flags.err);
1965 return MPP_NOK;
1966 }
1967 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
1968 if (ret)
1969 mpp_err_f("poll cmd failed %d status %d \n", ret, elem->hw_status);
1970
1971 hal_h265e_leave();
1972 return ret;
1973 }
1974
hal_h265e_v541_get_task(void * hal,HalEncTask * task)1975 MPP_RET hal_h265e_v541_get_task(void *hal, HalEncTask *task)
1976 {
1977 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
1978 MppFrame frame = task->frame;
1979 EncFrmStatus *frm_status = &task->rc_task->frm;
1980
1981 hal_h265e_enter();
1982
1983 if (vepu54x_h265_setup_hal_bufs(ctx)) {
1984 hal_h265e_err("vepu541_h265_allocate_buffers failed, free buffers and return\n");
1985 task->flags.err |= HAL_ENC_TASK_ERR_ALLOC;
1986 return MPP_ERR_MALLOC;
1987 }
1988
1989 if (!frm_status->reencode)
1990 ctx->last_frame_type = ctx->frame_type;
1991
1992 if (frm_status->is_intra) {
1993 ctx->frame_type = INTRA_FRAME;
1994 } else {
1995 ctx->frame_type = INTER_P_FRAME;
1996 }
1997 if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
1998 MppMeta meta = mpp_frame_get_meta(frame);
1999
2000 mpp_meta_get_ptr_d(meta, KEY_ROI_DATA, (void **)&ctx->roi_data, NULL);
2001 mpp_meta_get_ptr_d(meta, KEY_ROI_DATA2, (void **)&ctx->roi_data2, NULL);
2002 mpp_meta_get_ptr_d(meta, KEY_OSD_DATA, (void **)&ctx->osd_cfg.osd_data, NULL);
2003 mpp_meta_get_ptr_d(meta, KEY_OSD_DATA2, (void **)&ctx->osd_cfg.osd_data2, NULL);
2004 mpp_meta_get_buffer_d(meta, KEY_QPMAP0, &ctx->qpmap, NULL);
2005 }
2006 memset(&ctx->feedback, 0, sizeof(vepu541_h265_fbk));
2007
2008 hal_h265e_leave();
2009 return MPP_OK;
2010 }
2011
hal_h265e_v541_ret_task(void * hal,HalEncTask * task)2012 MPP_RET hal_h265e_v541_ret_task(void *hal, HalEncTask *task)
2013 {
2014 H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
2015 HalEncTask *enc_task = task;
2016 vepu541_h265_fbk *fb = &ctx->feedback;
2017 EncRcTaskInfo *rc_info = &task->rc_task->info;
2018 RK_U32 offset = mpp_packet_get_length(enc_task->packet);
2019
2020 hal_h265e_enter();
2021
2022 vepu541_h265_set_feedback(ctx, enc_task);
2023 mpp_buffer_sync_partial_begin(enc_task->output, offset, fb->out_strm_size);
2024 hal_h265e_amend_temporal_id(task, fb->out_strm_size);
2025
2026 rc_info->sse = fb->sse_sum;
2027 rc_info->lvl64_inter_num = fb->st_lvl64_inter_num;
2028 rc_info->lvl32_inter_num = fb->st_lvl32_inter_num;
2029 rc_info->lvl16_inter_num = fb->st_lvl16_inter_num;
2030 rc_info->lvl8_inter_num = fb->st_lvl8_inter_num;
2031 rc_info->lvl32_intra_num = fb->st_lvl32_intra_num;
2032 rc_info->lvl16_intra_num = fb->st_lvl16_intra_num;
2033 rc_info->lvl8_intra_num = fb->st_lvl8_intra_num;
2034 rc_info->lvl4_intra_num = fb->st_lvl4_intra_num;
2035
2036 enc_task->hw_length = fb->out_strm_size;
2037 enc_task->length += fb->out_strm_size;
2038
2039 hal_h265e_dbg_detail("output stream size %d\n", fb->out_strm_size);
2040
2041 hal_h265e_leave();
2042 return MPP_OK;
2043 }
2044
2045 const MppEncHalApi hal_h265e_vepu541 = {
2046 "h265e_v541_v2",
2047 MPP_VIDEO_CodingHEVC,
2048 sizeof(H265eV541HalContext),
2049 0,
2050 hal_h265e_v541_init,
2051 hal_h265e_v541_deinit,
2052 hal_h265e_vepu54x_prepare,
2053 hal_h265e_v541_get_task,
2054 hal_h265e_v541_gen_regs,
2055 hal_h265e_v54x_start,
2056 hal_h265e_v541_wait,
2057 NULL,
2058 NULL,
2059 hal_h265e_v541_ret_task,
2060 };
2061
2062