1 /* SPDX-License-Identifier: Apache-2.0 */
2 /*
3 * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
4 */
5
6 #define MODULE_TAG "hal_h265e_v511"
7
8 #include <string.h>
9 #include <math.h>
10 #include <limits.h>
11
12 #include "mpp_env.h"
13 #include "mpp_mem.h"
14 #include "mpp_common.h"
15 #include "mpp_frame_impl.h"
16 #include "mpp_packet_impl.h"
17 #include "mpp_enc_cb_param.h"
18
19 #include "rkv_enc_def.h"
20 #include "h265e_syntax_new.h"
21 #include "h265e_dpb.h"
22 #include "hal_bufs.h"
23 #include "hal_h265e_debug.h"
24 #include "hal_h265e_vepu511.h"
25 #include "hal_h265e_vepu511_reg.h"
26 #include "hal_h265e_stream_amend.h"
27
28 #include "vepu5xx_common.h"
29 #include "vepu511_common.h"
30
31 #define MAX_FRAME_TASK_NUM 2
32 #define H265E_LAMBDA_TAB_SIZE (52 * sizeof(RK_U32))
33 #define H265E_SMEAR_STR_NUM (8)
34
35 #define hal_h265e_err(fmt, ...) \
36 do {\
37 mpp_err_f(fmt, ## __VA_ARGS__);\
38 } while (0)
39
40 typedef struct Vepu511H265Fbk_t {
41 RK_U32 hw_status; /* 0:corret, 1:error */
42 RK_U32 frame_type;
43 RK_U32 qp_sum;
44 RK_U32 out_strm_size;
45 RK_U32 out_hw_strm_size;
46 RK_S64 sse_sum;
47 RK_U32 st_lvl64_inter_num;
48 RK_U32 st_lvl32_inter_num;
49 RK_U32 st_lvl16_inter_num;
50 RK_U32 st_lvl8_inter_num;
51 RK_U32 st_lvl32_intra_num;
52 RK_U32 st_lvl16_intra_num;
53 RK_U32 st_lvl8_intra_num;
54 RK_U32 st_lvl4_intra_num;
55 RK_U32 st_cu_num_qp[52];
56 RK_U32 st_madp;
57 RK_U32 st_madi;
58 RK_U32 st_mb_num;
59 RK_U32 st_ctu_num;
60 RK_U32 st_smear_cnt[5];
61 RK_S32 reg_idx;
62 RK_U32 acc_cover16_num;
63 RK_U32 acc_bndry16_num;
64 RK_U32 acc_zero_mv;
65 RK_S8 tgt_sub_real_lvl[6];
66 } Vepu511H265Fbk;
67
68 typedef struct Vepu511H265eFrmCfg_t {
69 RK_S32 frame_count;
70 RK_S32 frame_type;
71
72 /* dchs cfg on frame parallel */
73 RK_S32 dchs_curr_idx;
74 RK_S32 dchs_prev_idx;
75
76 /* hal dpb management slot idx */
77 RK_S32 hal_curr_idx;
78 RK_S32 hal_refr_idx;
79
80 /* regs cfg */
81 H265eV511RegSet *regs_set;
82 H265eV511StatusElem *regs_ret;
83
84 /* hardware return info collection cfg */
85 Vepu511H265Fbk feedback;
86
87 void *roi_data;
88
89 /* roi buffer for qpmap or gdr */
90 MppBuffer roir_buf;
91 RK_S32 roir_buf_size;
92 void *roi_base_cfg_sw_buf;
93
94 /* variable length cfg */
95 MppDevRegOffCfgs *reg_cfg;
96 } Vepu511H265eFrmCfg;
97
98 typedef struct H265eV511HalContext_t {
99 MppEncHalApi api;
100 MppDev dev;
101 void *regs;
102 void *reg_out;
103 Vepu511H265eFrmCfg *frms[MAX_FRAME_TASK_NUM];
104
105 /* current used frame config */
106 Vepu511H265eFrmCfg *frm;
107
108 /* slice split poll cfg */
109 RK_S32 poll_slice_max;
110 RK_S32 poll_cfg_size;
111 MppDevPollCfg *poll_cfgs;
112 MppCbCtx *output_cb;
113
114 /* @frame_cnt starts from ZERO */
115 RK_S32 frame_count;
116
117 /* frame parallel info */
118 RK_S32 task_cnt;
119 RK_S32 task_idx;
120
121 /* dchs cfg */
122 RK_S32 curr_idx;
123 RK_S32 prev_idx;
124
125 Vepu511H265Fbk feedback;
126 Vepu511H265Fbk last_frame_fb;
127 void *dump_files;
128 RK_U32 frame_cnt_gen_ready;
129
130 RK_S32 frame_type;
131 RK_S32 last_frame_type;
132
133 MppBufferGroup roi_grp;
134 void *roi_data;
135 Vepu511OsdCfg osd_cfg;
136
137 MppEncCfgSet *cfg;
138 MppDevRegOffCfgs *reg_cfg;
139 H265eSyntax_new *syn;
140 H265eDpb *dpb;
141
142 RK_U32 enc_mode;
143 RK_U32 frame_size;
144 RK_S32 max_buf_cnt;
145 RK_S32 hdr_status;
146 void *input_fmt;
147 RK_U8 *src_buf;
148 RK_U8 *dst_buf;
149 RK_S32 buf_size;
150 RK_U32 frame_num;
151 HalBufs dpb_bufs;
152 RK_S32 fbc_header_len;
153 RK_U32 title_num;
154
155 RK_S32 qpmap_en;
156 RK_S32 smart_en;
157
158 /* external line buffer over 3K */
159 MppBufferGroup ext_line_buf_grp;
160 RK_S32 ext_line_buf_size;
161 MppBuffer ext_line_buf;
162 MppBuffer buf_pass1;
163 MppBuffer ext_line_bufs[MAX_FRAME_TASK_NUM];
164
165 void *tune;
166 } H265eV511HalContext;
167
168 static const RK_U32 lambda_tbl_pre_intra[52] = {
169 4206, 4945, 5814, 6835, 8035, 9446, 11105, 13056,
170 15348, 18044, 21213, 24938, 29318, 34467, 40521, 47637,
171 56003, 65839, 77402, 90996, 106977, 125765, 147852, 173819,
172 204346, 240234, 983, 1206, 1479, 1813, 2223, 2727,
173 3344, 4100, 5028, 6166, 7561, 9272, 11371, 13944,
174 17099, 20969, 25714, 31533, 38669, 47420, 58150, 71310,
175 87447, 107236, 131504, 161263,
176 };
177
178 static const RK_U32 lambda_tbl_pre_inter[52] = {
179 760, 959, 1210, 1526, 1925, 2428, 3063, 3864,
180 4874, 6147, 7754, 9781, 12337, 15562, 19629, 24760,
181 31231, 39394, 49691, 62678, 79061, 99725, 125790, 158668,
182 200140, 252451, 579, 730, 919, 1159, 1461, 1993,
183 2898, 3652, 4601, 5411, 6818, 7362, 9276, 11688,
184 14725, 18553, 25324, 31906, 40200, 50649, 68724, 74217,
185 101300, 127630, 148435, 187017,
186 };
187
188 static RK_U32 rdo_lambda_table_I[60] = {
189 0x00000012, 0x00000017,
190 0x0000001d, 0x00000024, 0x0000002e, 0x0000003a,
191 0x00000049, 0x0000005c, 0x00000074, 0x00000092,
192 0x000000b8, 0x000000e8, 0x00000124, 0x00000170,
193 0x000001cf, 0x00000248, 0x000002df, 0x0000039f,
194 0x0000048f, 0x000005bf, 0x0000073d, 0x0000091f,
195 0x00000b7e, 0x00000e7a, 0x0000123d, 0x000016fb,
196 0x00001cf4, 0x0000247b, 0x00002df6, 0x000039e9,
197 0x000048f6, 0x00005bed, 0x000073d1, 0x000091ec,
198 0x0000b7d9, 0x0000e7a2, 0x000123d7, 0x00016fb2,
199 0x0001cf44, 0x000247ae, 0x0002df64, 0x00039e89,
200 0x00048f5c, 0x0005bec8, 0x00073d12, 0x00091eb8,
201 0x000b7d90, 0x000e7a23, 0x00123d71, 0x0016fb20,
202 0x001cf446, 0x00247ae1, 0x002df640, 0x0039e88c,
203 0x0048f5c3, 0x005bec81, 0x0073d119, 0x0091eb85,
204 0x00b7d902, 0x00e7a232
205 };
206
207 static RK_U32 rdo_lambda_table_P[60] = {
208 0x0000002c, 0x00000038, 0x00000044, 0x00000058,
209 0x00000070, 0x00000089, 0x000000b0, 0x000000e0,
210 0x00000112, 0x00000160, 0x000001c0, 0x00000224,
211 0x000002c0, 0x00000380, 0x00000448, 0x00000580,
212 0x00000700, 0x00000890, 0x00000b00, 0x00000e00,
213 0x00001120, 0x00001600, 0x00001c00, 0x00002240,
214 0x00002c00, 0x00003800, 0x00004480, 0x00005800,
215 0x00007000, 0x00008900, 0x0000b000, 0x0000e000,
216 0x00011200, 0x00016000, 0x0001c000, 0x00022400,
217 0x0002c000, 0x00038000, 0x00044800, 0x00058000,
218 0x00070000, 0x00089000, 0x000b0000, 0x000e0000,
219 0x00112000, 0x00160000, 0x001c0000, 0x00224000,
220 0x002c0000, 0x00380000, 0x00448000, 0x00580000,
221 0x00700000, 0x00890000, 0x00b00000, 0x00e00000,
222 0x01120000, 0x01600000, 0x01c00000, 0x02240000,
223 };
224
225 static RK_U8 vepu511_h265_cqm_intra8[64] = {
226 16, 16, 16, 16, 17, 18, 21, 24,
227 16, 16, 16, 16, 17, 19, 22, 25,
228 16, 16, 17, 18, 20, 22, 25, 29,
229 16, 16, 18, 21, 24, 27, 31, 36,
230 17, 17, 20, 24, 30, 35, 41, 47,
231 18, 19, 22, 27, 35, 44, 54, 65,
232 21, 22, 25, 31, 41, 54, 70, 88,
233 24, 25, 29, 36, 47, 65, 88, 115
234 };
235
236 static RK_U8 vepu511_h265_cqm_inter8[64] = {
237 16, 16, 16, 16, 17, 18, 20, 24,
238 16, 16, 16, 17, 18, 20, 24, 25,
239 16, 16, 17, 18, 20, 24, 25, 28,
240 16, 17, 18, 20, 24, 25, 28, 33,
241 17, 18, 20, 24, 25, 28, 33, 41,
242 18, 20, 24, 25, 28, 33, 41, 54,
243 20, 24, 25, 28, 33, 41, 54, 71,
244 24, 25, 28, 33, 41, 54, 71, 91
245 };
246
save_to_file_511(char * name,void * ptr,size_t size)247 void save_to_file_511(char *name, void *ptr, size_t size)
248 {
249 FILE *fp = fopen(name, "w+b");
250 if (fp) {
251 fwrite(ptr, 1, size, fp);
252 fclose(fp);
253 } else
254 mpp_err("create file %s failed\n", name);
255 }
256
vepu511_h265e_dump(H265eV511HalContext * ctx,HalEncTask * enc_task)257 void vepu511_h265e_dump(H265eV511HalContext *ctx, HalEncTask *enc_task)
258 {
259 H265eSyntax_new *syn = ctx->syn;
260 HalBuf *hal_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.ref_pic.slot_idx);
261 size_t buf_size = mpp_buffer_get_size(hal_buf->buf[0]);
262 size_t dws_size = mpp_buffer_get_size(hal_buf->buf[1]);
263 void *ptr = mpp_buffer_get_ptr(hal_buf->buf[0]);
264 void *dws_ptr = mpp_buffer_get_ptr(hal_buf->buf[1]);
265 RK_U32 frm_num = ctx->frms[enc_task->flags.reg_idx]->frame_count;
266 RK_S32 pid = getpid();
267 char name[128];
268 size_t name_len = sizeof(name) - 1;
269
270 snprintf(name, name_len, "/mnt/sdcard/dump/refr_fbd_%d_frm%d.bin", pid, frm_num);
271 save_to_file_511(name, ptr + ctx->fbc_header_len, buf_size - ctx->fbc_header_len);
272
273 snprintf(name, name_len, "/mnt/sdcard/dump/refr_fbh_%d_frm%d.bin", pid, frm_num);
274 save_to_file_511(name, ptr, ctx->fbc_header_len);
275
276 snprintf(name, name_len, "/mnt/sdcard/dump/refr_dsp_%d_frm%d.bin", pid, frm_num);
277 save_to_file_511(name, dws_ptr, dws_size);
278
279 hal_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx);
280 buf_size = mpp_buffer_get_size(hal_buf->buf[0]);
281 dws_size = mpp_buffer_get_size(hal_buf->buf[1]);
282 ptr = mpp_buffer_get_ptr(hal_buf->buf[0]);
283 dws_ptr = mpp_buffer_get_ptr(hal_buf->buf[1]);
284
285 snprintf(name, name_len, "/mnt/sdcard/dump/recn_fbd_%d_frm%d_slot%d.bin", pid, frm_num, syn->sp.recon_pic.slot_idx);
286 save_to_file_511(name, ptr + ctx->fbc_header_len, buf_size - ctx->fbc_header_len);
287
288 snprintf(name, name_len, "/mnt/sdcard/dump/recn_fbh_%d_frm%d_slot%d.bin", pid, frm_num, syn->sp.recon_pic.slot_idx);
289 save_to_file_511(name, ptr, ctx->fbc_header_len);
290
291 snprintf(name, name_len, "/mnt/sdcard/dump/recn_dsp_%d_frm%d_slot%d.bin", pid, frm_num, syn->sp.recon_pic.slot_idx);
292 save_to_file_511(name, dws_ptr, dws_size);
293
294 }
295
setup_ext_line_bufs(H265eV511HalContext * ctx)296 static void setup_ext_line_bufs(H265eV511HalContext *ctx)
297 {
298 RK_S32 i;
299
300 for (i = 0; i < ctx->task_cnt; i++) {
301 if (ctx->ext_line_bufs[i])
302 continue;
303
304 mpp_buffer_get(ctx->ext_line_buf_grp, &ctx->ext_line_bufs[i],
305 ctx->ext_line_buf_size);
306 }
307 }
308
clear_ext_line_bufs(H265eV511HalContext * ctx)309 static void clear_ext_line_bufs(H265eV511HalContext *ctx)
310 {
311 RK_S32 i;
312
313 for (i = 0; i < ctx->task_cnt; i++) {
314 if (ctx->ext_line_bufs[i]) {
315 mpp_buffer_put(ctx->ext_line_bufs[i]);
316 ctx->ext_line_bufs[i] = NULL;
317 }
318 }
319 }
320
vepu511_h265_setup_hal_bufs(H265eV511HalContext * ctx)321 static MPP_RET vepu511_h265_setup_hal_bufs(H265eV511HalContext *ctx)
322 {
323 MPP_RET ret = MPP_OK;
324 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
325 RK_U32 frame_size;
326 VepuFmt input_fmt = VEPU5xx_FMT_YUV420P;
327 RK_S32 mb_wd64, mb_h64;
328 MppEncRefCfg ref_cfg = ctx->cfg->ref_cfg;
329 MppEncPrepCfg *prep = &ctx->cfg->prep;
330 RK_S32 old_max_cnt = ctx->max_buf_cnt;
331 RK_S32 new_max_cnt = 4;
332 RK_S32 alignment = 32;
333 RK_S32 aligned_w = MPP_ALIGN(prep->width, alignment);
334
335 hal_h265e_enter();
336
337 mb_wd64 = (prep->width + 63) / 64;
338 mb_h64 = (prep->height + 63) / 64 + 1;
339
340 frame_size = MPP_ALIGN(prep->width, 16) * MPP_ALIGN(prep->height, 16);
341 vepu5xx_set_fmt(fmt, ctx->cfg->prep.format);
342 input_fmt = (VepuFmt)fmt->format;
343 switch (input_fmt) {
344 case VEPU5xx_FMT_YUV400:
345 break;
346 case VEPU5xx_FMT_YUV420P:
347 case VEPU5xx_FMT_YUV420SP: {
348 frame_size = frame_size * 3 / 2;
349 } break;
350 case VEPU5xx_FMT_YUV422P:
351 case VEPU5xx_FMT_YUV422SP:
352 case VEPU5xx_FMT_YUYV422:
353 case VEPU5xx_FMT_UYVY422:
354 case VEPU5xx_FMT_BGR565: {
355 frame_size *= 2;
356 } break;
357 case VEPU5xx_FMT_BGR888:
358 case VEPU5xx_FMT_YUV444SP:
359 case VEPU5xx_FMT_YUV444P: {
360 frame_size *= 3;
361 } break;
362 case VEPU5xx_FMT_BGRA8888: {
363 frame_size *= 4;
364 } break;
365 default: {
366 hal_h265e_err("invalid src color space: %d\n", input_fmt);
367 return MPP_NOK;
368 }
369 }
370
371 if (ref_cfg) {
372 MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
373 new_max_cnt = MPP_MAX(new_max_cnt, info->dpb_size + 1);
374 }
375
376 if (aligned_w > SZ_4K) {
377 RK_S32 ctu_w = (aligned_w + 31) / 32;
378 RK_S32 ext_line_buf_size = ((ctu_w - 113) * 27 + 15) / 16 * 16 * 16;
379
380 if (NULL == ctx->ext_line_buf_grp)
381 mpp_buffer_group_get_internal(&ctx->ext_line_buf_grp, MPP_BUFFER_TYPE_ION);
382 else if (ext_line_buf_size != ctx->ext_line_buf_size) {
383 clear_ext_line_bufs(ctx);
384 mpp_buffer_group_clear(ctx->ext_line_buf_grp);
385 }
386
387 mpp_assert(ctx->ext_line_buf_grp);
388 setup_ext_line_bufs(ctx);
389 ctx->ext_line_buf_size = ext_line_buf_size;
390 } else {
391 clear_ext_line_bufs(ctx);
392
393 if (ctx->ext_line_buf_grp) {
394 mpp_buffer_group_clear(ctx->ext_line_buf_grp);
395 mpp_buffer_group_put(ctx->ext_line_buf_grp);
396 ctx->ext_line_buf_grp = NULL;
397 }
398 ctx->ext_line_buf_size = 0;
399 }
400
401 if (frame_size > ctx->frame_size || new_max_cnt > old_max_cnt) {
402 size_t size[4] = {0};
403 RK_S32 ctu_w = (prep->width + 31) / 32;
404 RK_S32 ctu_h = (prep->height + 31) / 32;
405
406 hal_bufs_deinit(ctx->dpb_bufs);
407 hal_bufs_init(&ctx->dpb_bufs);
408
409 ctx->fbc_header_len = MPP_ALIGN(((mb_wd64 * mb_h64) << 6), SZ_8K);
410 size[0] = ctx->fbc_header_len + ((mb_wd64 * mb_h64) << 12) * 3 / 2; //fbc_h + fbc_b
411 size[1] = (mb_wd64 * mb_h64 << 8);
412 size[2] = MPP_ALIGN(mb_wd64 * mb_h64 * 16 * 4, 256) * 16;
413 /* smear bufs */
414 size[3] = MPP_ALIGN(ctu_w, 16) * MPP_ALIGN(ctu_h, 16);
415 new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
416
417 hal_h265e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
418 ctx->frame_size, frame_size, old_max_cnt, new_max_cnt);
419
420 hal_bufs_setup(ctx->dpb_bufs, new_max_cnt, MPP_ARRAY_ELEMS(size), size);
421
422 ctx->frame_size = frame_size;
423 ctx->max_buf_cnt = new_max_cnt;
424 }
425 hal_h265e_leave();
426 return ret;
427 }
428
hal_h265e_vepu511_deinit(void * hal)429 MPP_RET hal_h265e_vepu511_deinit(void *hal)
430 {
431 H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
432 RK_S32 i = 0;
433
434 hal_h265e_enter();
435 MPP_FREE(ctx->poll_cfgs);
436 MPP_FREE(ctx->input_fmt);
437 hal_bufs_deinit(ctx->dpb_bufs);
438
439 for (i = 0; i < ctx->task_cnt; i++) {
440 Vepu511H265eFrmCfg *frm = ctx->frms[i];
441
442 if (!frm)
443 continue;
444
445 if (frm->roir_buf) {
446 mpp_buffer_put(frm->roir_buf);
447 frm->roir_buf = NULL;
448 frm->roir_buf_size = 0;
449 }
450
451 MPP_FREE(frm->roi_base_cfg_sw_buf);
452
453 if (frm->reg_cfg) {
454 mpp_dev_multi_offset_deinit(frm->reg_cfg);
455 frm->reg_cfg = NULL;
456 }
457
458 MPP_FREE(frm->regs_set);
459 MPP_FREE(frm->regs_ret);
460 MPP_FREE(ctx->frms[i]);
461 }
462
463 clear_ext_line_bufs(ctx);
464
465 if (ctx->ext_line_buf_grp) {
466 mpp_buffer_group_put(ctx->ext_line_buf_grp);
467 ctx->ext_line_buf_grp = NULL;
468 }
469
470 if (ctx->buf_pass1) {
471 mpp_buffer_put(ctx->buf_pass1);
472 ctx->buf_pass1 = NULL;
473 }
474
475 if (ctx->dev) {
476 mpp_dev_deinit(ctx->dev);
477 ctx->dev = NULL;
478 }
479
480 if (ctx->reg_cfg) {
481 mpp_dev_multi_offset_deinit(ctx->reg_cfg);
482 ctx->reg_cfg = NULL;
483 }
484
485 if (ctx->roi_grp) {
486 mpp_buffer_group_put(ctx->roi_grp);
487 ctx->roi_grp = NULL;
488 }
489
490 if (ctx->tune) {
491 // vepu511_h265e_tune_deinit(ctx->tune);
492 ctx->tune = NULL;
493 }
494
495 hal_h265e_leave();
496 return MPP_OK;
497 }
498
hal_h265e_vepu511_init(void * hal,MppEncHalCfg * cfg)499 MPP_RET hal_h265e_vepu511_init(void *hal, MppEncHalCfg *cfg)
500 {
501 MPP_RET ret = MPP_OK;
502 H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
503 RK_S32 i = 0;
504
505 mpp_env_get_u32("hal_h265e_debug", &hal_h265e_debug, 0);
506 hal_h265e_enter();
507
508 ctx->task_cnt = cfg->task_cnt;
509 mpp_assert(ctx->task_cnt && ctx->task_cnt <= MAX_FRAME_TASK_NUM);
510 if (ctx->task_cnt > MAX_FRAME_TASK_NUM)
511 ctx->task_cnt = MAX_FRAME_TASK_NUM;
512
513 for (i = 0; i < ctx->task_cnt; i++) {
514 Vepu511H265eFrmCfg *frm_cfg = mpp_calloc(Vepu511H265eFrmCfg, 1);
515
516 frm_cfg->regs_set = mpp_calloc(H265eV511RegSet, 1);
517 frm_cfg->regs_ret = mpp_calloc(H265eV511StatusElem, 1);
518 frm_cfg->frame_type = INTRA_FRAME;
519 ctx->frms[i] = frm_cfg;
520 }
521
522 ctx->input_fmt = mpp_calloc(VepuFmtCfg, 1);
523 ctx->cfg = cfg->cfg;
524 hal_bufs_init(&ctx->dpb_bufs);
525
526 ctx->frame_count = -1;
527 ctx->frame_cnt_gen_ready = 0;
528 ctx->enc_mode = 1;
529 cfg->cap_recn_out = 1;
530 cfg->type = VPU_CLIENT_RKVENC;
531 ret = mpp_dev_init(&cfg->dev, cfg->type);
532 if (ret) {
533 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
534 return ret;
535 }
536 mpp_dev_multi_offset_init(&ctx->reg_cfg, 24);
537 ctx->dev = cfg->dev;
538 ctx->frame_type = INTRA_FRAME;
539
540 { /* setup default hardware config */
541 MppEncHwCfg *hw = &cfg->cfg->hw;
542 RK_U32 j;
543
544 hw->qp_delta_row_i = 2;
545 hw->qp_delta_row = 2;
546 hw->qbias_i = 171;
547 hw->qbias_p = 85;
548 hw->qbias_en = 0;
549
550 for (j = 0; j < MPP_ARRAY_ELEMS(hw->mode_bias); j++)
551 hw->mode_bias[j] = 8;
552 }
553
554 ctx->poll_slice_max = 8;
555 ctx->poll_cfg_size = (sizeof(ctx->poll_cfgs) + sizeof(RK_S32) * ctx->poll_slice_max) * 2;
556 ctx->poll_cfgs = mpp_malloc_size(MppDevPollCfg, ctx->poll_cfg_size);
557
558 if (NULL == ctx->poll_cfgs) {
559 ret = MPP_ERR_MALLOC;
560 mpp_err_f("init poll cfg buffer failed\n");
561 goto DONE;
562 }
563
564 ctx->output_cb = cfg->output_cb;
565 cfg->cap_recn_out = 1;
566
567 // ctx->tune = vepu511_h265e_tune_init(ctx);
568
569 DONE:
570 if (ret)
571 hal_h265e_vepu511_deinit(hal);
572
573 hal_h265e_leave();
574 return ret;
575 }
576
hal_h265e_vepu511_prepare(void * hal)577 static MPP_RET hal_h265e_vepu511_prepare(void *hal)
578 {
579 H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
580 MppEncPrepCfg *prep = &ctx->cfg->prep;
581
582 hal_h265e_dbg_func("enter %p\n", hal);
583
584 if (prep->change_res) {
585 RK_S32 i;
586
587 // pre-alloc required buffers to reduce first frame delay
588 vepu511_h265_setup_hal_bufs(ctx);
589 for (i = 0; i < ctx->max_buf_cnt; i++)
590 hal_bufs_get_buf(ctx->dpb_bufs, i);
591
592 prep->change_res = 0;
593 }
594
595 hal_h265e_dbg_func("leave %p\n", hal);
596
597 return MPP_OK;
598 }
599
600 static MPP_RET
vepu511_h265_set_patch_info(H265eSyntax_new * syn,VepuFmt input_fmt,MppDevRegOffCfgs * offsets,HalEncTask * task)601 vepu511_h265_set_patch_info(H265eSyntax_new *syn, VepuFmt input_fmt, MppDevRegOffCfgs *offsets, HalEncTask *task)
602 {
603 RK_U32 hor_stride = syn->pp.hor_stride;
604 RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height;
605 RK_U32 frame_size = hor_stride * ver_stride;
606 RK_U32 u_offset = 0, v_offset = 0;
607 MPP_RET ret = MPP_OK;
608
609 if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) {
610 u_offset = mpp_frame_get_fbc_offset(task->frame);
611 v_offset = u_offset;
612 } else {
613 switch (input_fmt) {
614 case VEPU5xx_FMT_YUV420P: {
615 u_offset = frame_size;
616 v_offset = frame_size * 5 / 4;
617 } break;
618 case VEPU5xx_FMT_YUV420SP:
619 case VEPU5xx_FMT_YUV422SP: {
620 u_offset = frame_size;
621 v_offset = frame_size;
622 } break;
623 case VEPU5xx_FMT_YUV422P: {
624 u_offset = frame_size;
625 v_offset = frame_size * 3 / 2;
626 } break;
627 case VEPU5xx_FMT_YUV400:
628 case VEPU5xx_FMT_YUYV422:
629 case VEPU5xx_FMT_UYVY422: {
630 u_offset = 0;
631 v_offset = 0;
632 } break;
633 case VEPU5xx_FMT_BGR565:
634 case VEPU5xx_FMT_BGR888:
635 case VEPU5xx_FMT_BGRA8888: {
636 u_offset = 0;
637 v_offset = 0;
638 } break;
639 case VEPU5xx_FMT_YUV444SP : {
640 u_offset = hor_stride * ver_stride;
641 v_offset = hor_stride * ver_stride;
642 } break;
643 case VEPU5xx_FMT_YUV444P : {
644 u_offset = hor_stride * ver_stride;
645 v_offset = hor_stride * ver_stride * 2;
646 } break;
647 default: {
648 hal_h265e_err("unknown color space: %d\n", input_fmt);
649 u_offset = frame_size;
650 v_offset = frame_size * 5 / 4;
651 }
652 }
653 }
654 mpp_dev_multi_offset_update(offsets, 161, u_offset);
655 mpp_dev_multi_offset_update(offsets, 162, v_offset);
656
657 return ret;
658 }
659
vepu511_h265e_save_pass1_patch(H265eV511RegSet * regs,H265eV511HalContext * ctx,RK_S32 tiles_enabled_flag)660 static MPP_RET vepu511_h265e_save_pass1_patch(H265eV511RegSet *regs, H265eV511HalContext *ctx,
661 RK_S32 tiles_enabled_flag)
662 {
663 H265eVepu511Frame *reg_frm = ®s->reg_frm;
664 RK_S32 width = ctx->cfg->prep.width;
665 RK_S32 height = ctx->cfg->prep.height;
666 RK_S32 width_align = MPP_ALIGN(width, 16);
667 RK_S32 height_align = MPP_ALIGN(height, 16);
668
669 if (NULL == ctx->buf_pass1) {
670 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2);
671 if (!ctx->buf_pass1) {
672 mpp_err("buf_pass1 malloc fail, debreath invaild");
673 return MPP_NOK;
674 }
675 }
676
677 reg_frm->common.enc_pic.cur_frm_ref = 1;
678 reg_frm->common.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1);
679 reg_frm->common.rfpw_b_addr = reg_frm->common.rfpw_h_addr;
680 reg_frm->common.enc_pic.rec_fbc_dis = 1;
681
682 if (tiles_enabled_flag)
683 reg_frm->synt_pps.lpf_fltr_acrs_til = 0;
684
685 mpp_dev_multi_offset_update(ctx->reg_cfg, 164, width_align * height_align);
686
687 /* NOTE: disable split to avoid lowdelay slice output */
688 reg_frm->common.sli_splt.sli_splt = 0;
689 reg_frm->common.enc_pic.slen_fifo = 0;
690
691 return MPP_OK;
692 }
693
vepu511_h265e_use_pass1_patch(H265eV511RegSet * regs,H265eV511HalContext * ctx)694 static MPP_RET vepu511_h265e_use_pass1_patch(H265eV511RegSet *regs, H265eV511HalContext *ctx)
695 {
696 Vepu511ControlCfg *reg_ctl = ®s->reg_ctl;
697 H265eVepu511Frame *reg_frm = ®s->reg_frm;
698 RK_S32 width_align = MPP_ALIGN(ctx->cfg->prep.width, 16);
699 RK_S32 height_align = MPP_ALIGN(ctx->cfg->prep.height, 16);
700 RK_S32 y_stride = width_align;
701 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
702 MPP_RET ret = MPP_OK;
703
704 hal_h265e_dbg_func("enter\n");
705
706 reg_frm->common.enc_pic.rfpr_compress_mode = 1;
707 reg_ctl->dtrns_map.src_bus_edin = fmt->src_endian;
708 reg_frm->common.src_fmt.src_cfmt = VEPU5xx_FMT_YUV420SP;
709 reg_frm->common.src_fmt.alpha_swap = 0;
710 reg_frm->common.src_fmt.rbuv_swap = 0;
711 reg_frm->common.src_fmt.out_fmt = 1;
712
713 reg_frm->common.src_strd0.src_strd0 = y_stride;
714 reg_frm->common.src_strd1.src_strd1 = y_stride;
715
716 reg_frm->common.src_proc.src_mirr = 0;
717 reg_frm->common.src_proc.src_rot = 0;
718
719 reg_frm->common.adr_src0 = mpp_buffer_get_fd(ctx->buf_pass1);
720 reg_frm->common.adr_src1 = reg_frm->common.adr_src0;
721
722 /* input cb addr */
723 ret = mpp_dev_multi_offset_update(ctx->reg_cfg, 161, width_align * height_align);
724 if (ret)
725 mpp_err_f("set input cb addr offset failed %d\n", ret);
726
727 return MPP_OK;
728 }
729
setup_vepu511_ext_line_buf(H265eV511HalContext * ctx,H265eV511RegSet * regs)730 static void setup_vepu511_ext_line_buf(H265eV511HalContext *ctx, H265eV511RegSet *regs)
731 {
732 H265eVepu511Frame *reg_frm = ®s->reg_frm;
733 RK_S32 fd;
734
735 if (ctx->ext_line_buf) {
736 fd = mpp_buffer_get_fd(ctx->ext_line_buf);
737
738 reg_frm->common.ebufb_addr = fd;
739 reg_frm->common.ebuft_addr = fd;
740 mpp_dev_multi_offset_update(ctx->reg_cfg, 178, ctx->ext_line_buf_size);
741 } else {
742 reg_frm->common.ebufb_addr = 0;
743 reg_frm->common.ebuft_addr = 0;
744 }
745 }
746
vepu511_h265_set_scaling_list(H265eV511RegSet * regs)747 static void vepu511_h265_set_scaling_list(H265eV511RegSet *regs)
748 {
749 H265eVepu511SclCfg *s = ®s->reg_scl;
750 RK_U8 *p = (RK_U8 *)&s->tu8_intra_y[0];
751 RK_U32 scl_lst_sel = regs->reg_frm.rdo_cfg.scl_lst_sel;
752 RK_U8 idx;
753
754 hal_h265e_dbg_func("enter\n");
755
756 if (scl_lst_sel == 1) {
757 for (idx = 0; idx < 64; idx++) {
758 /* TU8 intra Y/U/V */
759 p[idx + 64 * 0] = vepu511_h265_cqm_intra8[63 - idx];
760
761 p[idx + 64 * 1] = vepu511_h265_cqm_intra8[63 - idx];
762 p[idx + 64 * 2] = vepu511_h265_cqm_intra8[63 - idx];
763
764 /* TU8 inter Y/U/V */
765 p[idx + 64 * 3] = vepu511_h265_cqm_inter8[63 - idx];
766 p[idx + 64 * 4] = vepu511_h265_cqm_inter8[63 - idx];
767 p[idx + 64 * 5] = vepu511_h265_cqm_inter8[63 - idx];
768
769 /* TU16 intra Y/U/V AC */
770 p[idx + 64 * 6] = vepu511_h265_cqm_intra8[63 - idx];
771 p[idx + 64 * 7] = vepu511_h265_cqm_intra8[63 - idx];
772 p[idx + 64 * 8] = vepu511_h265_cqm_intra8[63 - idx];
773
774 /* TU16 inter Y/U/V AC */
775 p[idx + 64 * 9] = vepu511_h265_cqm_inter8[63 - idx];
776 p[idx + 64 * 10] = vepu511_h265_cqm_inter8[63 - idx];
777 p[idx + 64 * 11] = vepu511_h265_cqm_inter8[63 - idx];
778
779 /* TU32 intra/inter Y AC */
780 p[idx + 64 * 12] = vepu511_h265_cqm_intra8[63 - idx];
781 p[idx + 64 * 13] = vepu511_h265_cqm_inter8[63 - idx];
782 }
783
784 s->tu_dc0.tu16_intra_y_dc = 16;
785 s->tu_dc0.tu16_intra_u_dc = 16;
786 s->tu_dc0.tu16_intra_v_dc = 16;
787 s->tu_dc0.tu16_inter_y_dc = 16;
788 s->tu_dc1.tu16_inter_u_dc = 16;
789 s->tu_dc1.tu16_inter_v_dc = 16;
790 s->tu_dc1.tu32_intra_y_dc = 16;
791 s->tu_dc1.tu32_inter_y_dc = 16;
792 } else if (scl_lst_sel == 2) {
793 mpp_log_f("scaling_list_mode 2 is not supported yet\n");
794 }
795
796 hal_h265e_dbg_func("leave\n");
797 }
798
vepu511_h265_set_normal(H265eV511HalContext * ctx,H265eV511RegSet * regs)799 static void vepu511_h265_set_normal(H265eV511HalContext *ctx, H265eV511RegSet *regs)
800 {
801 Vepu511ControlCfg *reg_ctl = ®s->reg_ctl;
802
803 reg_ctl->enc_strt.lkt_num = 0;
804 reg_ctl->enc_strt.vepu_cmd = ctx->enc_mode;
805 reg_ctl->enc_clr.safe_clr = 0;
806 reg_ctl->enc_clr.force_clr = 0;
807
808 reg_ctl->int_en.enc_done_en = 1;
809 reg_ctl->int_en.lkt_node_done_en = 1;
810 reg_ctl->int_en.sclr_done_en = 1;
811 reg_ctl->int_en.vslc_done_en = 1;
812 reg_ctl->int_en.vbsf_oflw_en = 1;
813 reg_ctl->int_en.vbuf_lens_en = 1;
814 reg_ctl->int_en.enc_err_en = 1;
815 reg_ctl->int_en.vsrc_err_en = 1;
816 reg_ctl->int_en.wdg_en = 1;
817 reg_ctl->int_en.lkt_err_int_en = 1;
818 reg_ctl->int_en.lkt_err_int_en = 1;
819 reg_ctl->int_en.lkt_err_stop_en = 1;
820 reg_ctl->int_en.lkt_force_stop_en = 1;
821 reg_ctl->int_en.jslc_done_en = 1;
822 reg_ctl->int_en.jbsf_oflw_en = 1;
823 reg_ctl->int_en.jbuf_lens_en = 1;
824 reg_ctl->int_en.dvbm_err_en = 0;
825
826 reg_ctl->int_clr.enc_done_clr = 1;
827
828 reg_ctl->dtrns_map.jpeg_bus_edin = 0x7;
829 reg_ctl->int_clr.enc_done_clr = 1;
830
831 reg_ctl->dtrns_map.jpeg_bus_edin = 0x7;
832 reg_ctl->dtrns_map.src_bus_edin = 0x0;
833 reg_ctl->dtrns_map.meiw_bus_edin = 0x0;
834 reg_ctl->dtrns_map.bsw_bus_edin = 0x7;
835 reg_ctl->dtrns_map.lktr_bus_edin = 0x0;
836 reg_ctl->dtrns_map.roir_bus_edin = 0x0;
837 reg_ctl->dtrns_map.lktw_bus_edin = 0x0;
838 reg_ctl->dtrns_map.rec_nfbc_bus_edin = 0x0;
839
840 reg_ctl->dtrns_cfg.axi_brsp_cke = 0x3ff;
841 reg_ctl->dtrns_cfg.axi_brsp_cke = 0x3ff;
842 reg_ctl->enc_wdg.vs_load_thd = 0;
843 reg_ctl->opt_strg.cke = 1;
844 reg_ctl->opt_strg.resetn_hw_en = 0;
845 reg_ctl->opt_strg.rfpr_err_e = 1;
846 reg_ctl->opt_strg.sram_ckg_en = 0;
847
848 /* enable rdo clk gating */
849 {
850 RK_U32 *rdo_ckg = (RK_U32*)®s->reg_ctl.reg0022.rdo_ckg_hevc;
851
852 *rdo_ckg = 0x0;
853 }
854
855 }
856
vepu511_h265_set_prep(void * hal,HalEncTask * task,H265eV511RegSet * regs)857 static void vepu511_h265_set_prep(void *hal, HalEncTask *task, H265eV511RegSet *regs)
858 {
859 H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
860 H265eVepu511Frame *reg_frm = ®s->reg_frm;
861 Vepu511RcRoi *reg_klut = ®s->reg_rc_roi;
862 H265eSyntax_new *syn = (H265eSyntax_new *)task->syntax.data;
863 RK_U32 pic_width_align8, pic_height_align8;
864 RK_S32 pic_wd32, pic_h32;
865 MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
866
867 hal_h265e_enter();
868
869 pic_width_align8 = (syn->pp.pic_width + 7) & (~7);
870 pic_height_align8 = (syn->pp.pic_height + 7) & (~7);
871 pic_wd32 = (syn->pp.pic_width + 31) / 32;
872 pic_h32 = (syn->pp.pic_height + 31) / 32;
873
874 reg_frm->common.enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1;
875 reg_frm->common.enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1;
876 reg_frm->common.src_fill.pic_wfill = (syn->pp.pic_width & 0x7)
877 ? (8 - (syn->pp.pic_width & 0x7)) : 0;
878 reg_frm->common.src_fill.pic_hfill = (syn->pp.pic_height & 0x7)
879 ? (8 - (syn->pp.pic_height & 0x7)) : 0;
880
881 /* H.265 mode */
882 reg_frm->common.enc_pic.enc_stnd = 1;
883 /* current frame will be refered */
884 reg_frm->common.enc_pic.cur_frm_ref = !syn->sp.non_reference_flag;
885
886 reg_frm->common.enc_pic.bs_scp = 1;
887 reg_frm->common.enc_pic.log2_ctu_num_hevc = mpp_ceil_log2(pic_wd32 * pic_h32);
888
889 reg_klut->klut_ofst.chrm_klut_ofst = (ctx->frame_type == INTRA_FRAME) ? 6 :
890 (sm == MPP_ENC_SCENE_MODE_IPC ? 9 : 6);
891
892 reg_frm->common.enc_pic.rfpr_compress_mode = 0;
893 reg_frm->common.enc_pic.rec_fbc_dis = 0;
894
895 reg_frm->rdo_cfg.chrm_spcl = 0;
896
897 /*
898 * H265 Max Inter/Intra cu prediction Mode.
899 * More prediction modes lead to better compression performance but increase computational cycles.
900 *
901 * Default speed preset configuration to 0.67 PPC, ~40 FPS for 4K resolution at 500MHz:
902 * - Set Inter prediction 32/16/8 CUs at 1/3/2 and Intra 32/16/8/4 CUs at 1,
903 * Maximize the number of modes while ensuring the prediction hierarchy remains unchanged.
904 * - Set cime_fuse = 1, disable dual-window search for higher real-time performance.
905 * - Set fme_lvl_mrg = 1, enable FME's depth1 and depth2 joint search,
906 * improves real-time performance but will reduce the compression ratio.
907 * - Set cime_srch_lftw/rgtw/uph/dwnh = 12/12/15/15, expand CIME search range degraded real-time performance.
908 * - Set rime_prelvl_en = 0, disable RIME pre-level to improve real-time performance.
909 * - Set fmdc_adju_split32 = 0, enable CU32 block prediction.
910 * Setting fmdc_adju_split32 = 1 restricts prediction to CU16/8 only, improving real-time performance.
911 */
912 reg_frm->rdo_cfg.cu_inter_e = 0x5a;
913 reg_frm->rdo_intra_mode.intra_pu4_mode_num = 1;
914 reg_frm->rdo_intra_mode.intra_pu8_mode_num = 1;
915 reg_frm->rdo_intra_mode.intra_pu16_mode_num = 1;
916 reg_frm->rdo_intra_mode.intra_pu32_mode_num = 1;
917
918 if (syn->pp.num_long_term_ref_pics_sps) {
919 reg_frm->rdo_cfg.ltm_col = 0;
920 reg_frm->rdo_cfg.ltm_idx0l0 = 1;
921 } else {
922 reg_frm->rdo_cfg.ltm_col = 0;
923 reg_frm->rdo_cfg.ltm_idx0l0 = 0;
924 }
925
926 reg_frm->rdo_cfg.ccwa_e = 1;
927 reg_frm->rdo_cfg.scl_lst_sel = syn->pp.scaling_list_enabled_flag;
928
929 {
930 RK_U32 i_nal_type = 0;
931
932 if (ctx->frame_type == INTRA_FRAME)
933 i_nal_type = NAL_IDR_W_RADL;
934 else if (ctx->frame_type == INTER_P_FRAME )
935 i_nal_type = NAL_TRAIL_R;
936 else
937 i_nal_type = NAL_TRAIL_R;
938
939 reg_frm->synt_nal.nal_unit_type = i_nal_type;
940 }
941 }
942
vepu511_h265_set_split(H265eV511RegSet * regs,MppEncCfgSet * enc_cfg)943 static void vepu511_h265_set_split(H265eV511RegSet *regs, MppEncCfgSet *enc_cfg)
944 {
945 MppEncSliceSplit *cfg = &enc_cfg->split;
946
947 hal_h265e_dbg_func("enter\n");
948
949 switch (cfg->split_mode) {
950 case MPP_ENC_SPLIT_NONE : {
951 regs->reg_frm.common.sli_splt.sli_splt = 0;
952 regs->reg_frm.common.sli_splt.sli_splt_mode = 0;
953 regs->reg_frm.common.sli_splt.sli_splt_cpst = 0;
954 regs->reg_frm.common.sli_splt.sli_max_num_m1 = 0;
955 regs->reg_frm.common.sli_splt.sli_flsh = 0;
956 regs->reg_frm.common.sli_cnum.sli_splt_cnum_m1 = 0;
957
958 regs->reg_frm.common.sli_byte.sli_splt_byte = 0;
959 regs->reg_frm.common.enc_pic.slen_fifo = 0;
960 } break;
961 case MPP_ENC_SPLIT_BY_BYTE : {
962 regs->reg_frm.common.sli_splt.sli_splt = 1;
963 regs->reg_frm.common.sli_splt.sli_splt_mode = 0;
964 regs->reg_frm.common.sli_splt.sli_splt_cpst = 0;
965 regs->reg_frm.common.sli_splt.sli_max_num_m1 = 500;
966 regs->reg_frm.common.sli_splt.sli_flsh = 1;
967 regs->reg_frm.common.sli_cnum.sli_splt_cnum_m1 = 0;
968
969 regs->reg_frm.common.sli_byte.sli_splt_byte = cfg->split_arg;
970 regs->reg_frm.common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
971 regs->reg_ctl.int_en.vslc_done_en = cfg->split_out ? 1 : 0;
972 } break;
973 case MPP_ENC_SPLIT_BY_CTU : {
974 regs->reg_frm.common.sli_splt.sli_splt = 1;
975 regs->reg_frm.common.sli_splt.sli_splt_mode = 1;
976 regs->reg_frm.common.sli_splt.sli_splt_cpst = 0;
977 regs->reg_frm.common.sli_splt.sli_max_num_m1 = 500;
978 regs->reg_frm.common.sli_splt.sli_flsh = 1;
979 regs->reg_frm.common.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1;
980
981 regs->reg_frm.common.sli_byte.sli_splt_byte = 0;
982 regs->reg_frm.common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
983 regs->reg_ctl.int_en.vslc_done_en = cfg->split_out ? 1 : 0;
984 } break;
985 default : {
986 mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
987 } break;
988 }
989
990 hal_h265e_dbg_func("leave\n");
991 }
992
vepu511_h265_set_me_regs(H265eV511HalContext * ctx,H265eSyntax_new * syn,H265eV511RegSet * regs)993 static void vepu511_h265_set_me_regs(H265eV511HalContext *ctx, H265eSyntax_new *syn, H265eV511RegSet *regs)
994 {
995 H265eVepu511Param *s = ®s->reg_param;
996 H265eVepu511Frame *reg_frm = ®s->reg_frm;
997
998 reg_frm->common.me_rnge.cime_srch_dwnh = 15;
999 reg_frm->common.me_rnge.cime_srch_uph = 15;
1000 reg_frm->common.me_rnge.cime_srch_rgtw = 12;
1001 reg_frm->common.me_rnge.cime_srch_lftw = 12;
1002 reg_frm->common.me_cfg.rme_srch_h = 3;
1003 reg_frm->common.me_cfg.rme_srch_v = 3;
1004
1005 reg_frm->common.me_cfg.srgn_max_num = 72;
1006 reg_frm->common.me_cfg.cime_dist_thre = 1024;
1007 reg_frm->common.me_cfg.rme_dis = 0;
1008 reg_frm->common.me_cfg.fme_dis = 0;
1009 reg_frm->common.me_rnge.dlt_frm_num = 0x1;
1010
1011 if (syn->pp.sps_temporal_mvp_enabled_flag && (ctx->frame_type != INTRA_FRAME)) {
1012 if (ctx->last_frame_fb.frame_type == INTRA_FRAME)
1013 reg_frm->common.me_cach.colmv_load_hevc = 0;
1014 else
1015 reg_frm->common.me_cach.colmv_load_hevc = 1;
1016
1017 reg_frm->common.me_cach.colmv_stor_hevc = 1;
1018 }
1019
1020 reg_frm->common.me_cach.cime_zero_thre = 64;
1021 reg_frm->common.me_cach.fme_prefsu_en = 0;
1022
1023 /* CIME: 0x1760 - 0x176C */
1024 s->me_sqi_comb.cime_pmv_num = 1;
1025 s->me_sqi_comb.cime_fuse = 1;
1026 s->me_sqi_comb.move_lambda = 2;
1027 s->me_sqi_comb.rime_lvl_mrg = 0;
1028 s->me_sqi_comb.rime_prelvl_en = 0;
1029 s->me_sqi_comb.rime_prersu_en = 0;
1030 s->me_sqi_comb.fme_lvl_mrg = 1;
1031
1032 s->cime_mvd_th_comb.cime_mvd_th0 = 8;
1033 s->cime_mvd_th_comb.cime_mvd_th1 = 20;
1034 s->cime_mvd_th_comb.cime_mvd_th2 = 32;
1035 s->cime_madp_th_comb.cime_madp_th = 16;
1036 s->cime_madp_th_comb.ratio_consi_cfg = 8;
1037 s->cime_madp_th_comb.ratio_bmv_dist = 8;
1038 s->cime_multi_comb.cime_multi0 = 8;
1039 s->cime_multi_comb.cime_multi1 = 12;
1040 s->cime_multi_comb.cime_multi2 = 16;
1041 s->cime_multi_comb.cime_multi3 = 20;
1042
1043 /* RFME: 0x1770 - 0x177C */
1044 s->rime_mvd_th_comb.rime_mvd_th0 = 1;
1045 s->rime_mvd_th_comb.rime_mvd_th1 = 2;
1046 s->rime_mvd_th_comb.fme_madp_th = 0;
1047 s->rime_madp_th_comb.rime_madp_th0 = 8;
1048 s->rime_madp_th_comb.rime_madp_th1 = 16;
1049 s->rime_multi_comb.rime_multi0 = 4;
1050 s->rime_multi_comb.rime_multi1 = 8;
1051 s->rime_multi_comb.rime_multi2 = 12;
1052 s->cmv_st_th_comb.cmv_th0 = 64;
1053 s->cmv_st_th_comb.cmv_th1 = 96;
1054 s->cmv_st_th_comb.cmv_th2 = 128;
1055
1056 if (ctx->cfg->tune.scene_mode != MPP_ENC_SCENE_MODE_IPC) {
1057 s->cime_madp_th_comb.cime_madp_th = 0;
1058 s->rime_madp_th_comb.rime_madp_th0 = 0;
1059 s->rime_madp_th_comb.rime_madp_th1 = 0;
1060 s->cime_multi_comb.cime_multi0 = 4;
1061 s->cime_multi_comb.cime_multi1 = 4;
1062 s->cime_multi_comb.cime_multi2 = 4;
1063 s->cime_multi_comb.cime_multi3 = 4;
1064 s->rime_multi_comb.rime_multi0 = 4;
1065 s->rime_multi_comb.rime_multi1 = 4;
1066 s->rime_multi_comb.rime_multi2 = 4;
1067 } else if (ctx->smart_en) {
1068 s->cime_multi_comb.cime_multi0 = 4;
1069 s->cime_multi_comb.cime_multi1 = 6;
1070 s->cime_multi_comb.cime_multi2 = 8;
1071 s->cime_multi_comb.cime_multi3 = 12;
1072 s->rime_multi_comb.rime_multi0 = 4;
1073 s->rime_multi_comb.rime_multi1 = 6;
1074 s->rime_multi_comb.rime_multi2 = 8;
1075 }
1076
1077 s->rime_mvd_th_comb.fme_madp_th = 0;
1078 s->rime_multi_comb.rime_multi0 = 0;
1079 s->rime_multi_comb.rime_multi1 = 0;
1080 s->rime_multi_comb.rime_multi2 = 0;
1081 }
1082
vepu511_h265_set_hw_address(H265eV511HalContext * ctx,H265eVepu511Frame * regs,HalEncTask * task)1083 static void vepu511_h265_set_hw_address(H265eV511HalContext *ctx, H265eVepu511Frame *regs,
1084 HalEncTask *task)
1085 {
1086 HalEncTask *enc_task = task;
1087 HalBuf *recon_buf, *ref_buf;
1088 MppBuffer md_info_buf = enc_task->md_info;
1089 Vepu511H265eFrmCfg *frm = ctx->frm;
1090 H265eSyntax_new *syn = ctx->syn;
1091
1092 hal_h265e_enter();
1093
1094 regs->common.adr_src0 = mpp_buffer_get_fd(enc_task->input);
1095 regs->common.adr_src1 = regs->common.adr_src0;
1096 regs->common.adr_src2 = regs->common.adr_src0;
1097
1098 recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, frm->hal_curr_idx);
1099 ref_buf = hal_bufs_get_buf(ctx->dpb_bufs, frm->hal_refr_idx);
1100
1101 if (!syn->sp.non_reference_flag) {
1102 regs->common.rfpw_h_addr = mpp_buffer_get_fd(recon_buf->buf[0]);
1103 regs->common.rfpw_b_addr = regs->common.rfpw_h_addr;
1104 mpp_dev_multi_offset_update(ctx->reg_cfg, 164, ctx->fbc_header_len);
1105 }
1106 regs->common.rfpr_h_addr = mpp_buffer_get_fd(ref_buf->buf[0]);
1107 regs->common.rfpr_b_addr = regs->common.rfpr_h_addr;
1108 regs->common.colmvw_addr = mpp_buffer_get_fd(recon_buf->buf[2]);
1109 regs->common.colmvr_addr = mpp_buffer_get_fd(ref_buf->buf[2]);
1110 regs->common.dspw_addr = mpp_buffer_get_fd(recon_buf->buf[1]);
1111 regs->common.dspr_addr = mpp_buffer_get_fd(ref_buf->buf[1]);
1112
1113 mpp_dev_multi_offset_update(ctx->reg_cfg, 166, ctx->fbc_header_len);
1114
1115 if (md_info_buf) {
1116 regs->common.enc_pic.mei_stor = 1;
1117 regs->common.meiw_addr = mpp_buffer_get_fd(md_info_buf);
1118 } else {
1119 regs->common.enc_pic.mei_stor = 0;
1120 regs->common.meiw_addr = 0;
1121 }
1122
1123 regs->common.bsbt_addr = mpp_buffer_get_fd(enc_task->output);
1124 /* TODO: stream size relative with syntax */
1125 regs->common.bsbb_addr = regs->common.bsbt_addr;
1126 regs->common.bsbr_addr = regs->common.bsbt_addr;
1127 regs->common.adr_bsbs = regs->common.bsbt_addr;
1128
1129 regs->common.rfpt_h_addr = 0xffffffff;
1130 regs->common.rfpb_h_addr = 0;
1131 regs->common.rfpt_b_addr = 0xffffffff;
1132 regs->common.adr_rfpb_b = 0;
1133 regs->common.adr_roir = 0;
1134
1135 mpp_dev_multi_offset_update(ctx->reg_cfg, 174, mpp_packet_get_length(task->packet));
1136 mpp_dev_multi_offset_update(ctx->reg_cfg, 172, mpp_buffer_get_size(enc_task->output));
1137
1138 regs->common.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
1139 regs->common.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
1140
1141 /* smear bufs */
1142 regs->common.adr_smear_rd = mpp_buffer_get_fd(ref_buf->buf[3]);
1143 regs->common.adr_smear_wr = mpp_buffer_get_fd(recon_buf->buf[3]);
1144 }
1145
vepu511_h265_set_pp_regs(H265eV511RegSet * regs,VepuFmtCfg * fmt,MppEncPrepCfg * prep_cfg,HalEncTask * task)1146 static void vepu511_h265_set_pp_regs(H265eV511RegSet *regs, VepuFmtCfg *fmt,
1147 MppEncPrepCfg *prep_cfg, HalEncTask *task)
1148 {
1149 Vepu511ControlCfg *reg_ctl = ®s->reg_ctl;
1150 H265eVepu511Frame *reg_frm = ®s->reg_frm;
1151 RK_S32 stridey = 0;
1152 RK_S32 stridec = 0;
1153
1154 reg_ctl->dtrns_map.src_bus_edin = fmt->src_endian;
1155 reg_frm->common.src_fmt.src_cfmt = fmt->format;
1156 reg_frm->common.src_fmt.alpha_swap = fmt->alpha_swap;
1157 reg_frm->common.src_fmt.rbuv_swap = fmt->rbuv_swap;
1158
1159 reg_frm->common.src_fmt.out_fmt = (prep_cfg->format == MPP_FMT_YUV400) ? 0 : 1;
1160
1161 reg_frm->common.src_proc.src_mirr = prep_cfg->mirroring > 0;
1162 reg_frm->common.src_proc.src_rot = prep_cfg->rotation;
1163
1164 if (MPP_FRAME_FMT_IS_FBC(prep_cfg->format)) {
1165 reg_frm->common.src_proc.rkfbcd_en = 1;
1166
1167 stridey = mpp_frame_get_fbc_hdr_stride(task->frame);
1168 if (!stridey)
1169 stridey = MPP_ALIGN(prep_cfg->hor_stride, 64) >> 2;
1170 } else if (prep_cfg->hor_stride)
1171 stridey = prep_cfg->hor_stride;
1172 else {
1173 if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_BGRA8888)
1174 stridey = prep_cfg->width * 4;
1175 else if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_BGR888)
1176 stridey = prep_cfg->width * 3;
1177 else if (reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_BGR565 ||
1178 reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_YUYV422 ||
1179 reg_frm->common.src_fmt.src_cfmt == VEPU5xx_FMT_UYVY422)
1180 stridey = prep_cfg->width * 2;
1181 }
1182
1183 switch (fmt->format) {
1184 case VEPU5xx_FMT_YUV444SP : {
1185 stridec = stridey * 2;
1186 } break;
1187 case VEPU5xx_FMT_YUV422SP :
1188 case VEPU5xx_FMT_YUV420SP :
1189 case VEPU5xx_FMT_YUV444P : {
1190 stridec = stridey;
1191 } break;
1192 default : {
1193 stridec = stridey / 2;
1194 } break;
1195 }
1196
1197 if (reg_frm->common.src_fmt.src_cfmt < VEPU5xx_FMT_ARGB1555) {
1198 reg_frm->common.src_udfy.csc_wgt_r2y = 77;
1199 reg_frm->common.src_udfy.csc_wgt_g2y = 150;
1200 reg_frm->common.src_udfy.csc_wgt_b2y = 29;
1201
1202 reg_frm->common.src_udfu.csc_wgt_r2u = -43;
1203 reg_frm->common.src_udfu.csc_wgt_g2u = -85;
1204 reg_frm->common.src_udfu.csc_wgt_b2u = 128;
1205
1206 reg_frm->common.src_udfv.csc_wgt_r2v = 128;
1207 reg_frm->common.src_udfv.csc_wgt_g2v = -107;
1208 reg_frm->common.src_udfv.csc_wgt_b2v = -21;
1209
1210 reg_frm->common.src_udfo.csc_ofst_y = 0;
1211 reg_frm->common.src_udfo.csc_ofst_u = 128;
1212 reg_frm->common.src_udfo.csc_ofst_v = 128;
1213 }
1214
1215 reg_frm->common.src_strd0.src_strd0 = stridey;
1216 reg_frm->common.src_strd1.src_strd1 = stridec;
1217 }
1218
vepu511_h265_set_vsp_filtering(H265eV511HalContext * ctx,H265eV511RegSet * regs)1219 static void vepu511_h265_set_vsp_filtering(H265eV511HalContext *ctx, H265eV511RegSet *regs)
1220 {
1221 // H265eV511RegSet *regs = ctx->regs;
1222 H265eVepu511Frame *s = ®s->reg_frm;
1223 MppEncCfgSet *cfg = ctx->cfg;
1224 MppEncHwCfg *hw = &cfg->hw;
1225 RK_U8 bit_chg_lvl = ctx->last_frame_fb.tgt_sub_real_lvl[5]; /* [0, 2] */
1226 RK_U8 corner_str = 0, edge_str = 0, internal_str = 0; /* [0, 3] */
1227
1228 if (cfg->tune.deblur_en && (cfg->tune.deblur_str % 2 == 0) &&
1229 (hw->flt_str_i == 0) && (hw->flt_str_p == 0)) {
1230 if (bit_chg_lvl == 2 && ctx->frame_type != INTRA_FRAME) {
1231 corner_str = 3;
1232 edge_str = 3;
1233 internal_str = 3;
1234 } else if (bit_chg_lvl > 0) {
1235 corner_str = 2;
1236 edge_str = 2;
1237 internal_str = 2;
1238 }
1239 } else {
1240 if (ctx->frame_type == INTRA_FRAME) {
1241 corner_str = hw->flt_str_i;
1242 edge_str = hw->flt_str_i;
1243 internal_str = hw->flt_str_i;
1244 } else {
1245 corner_str = hw->flt_str_p;
1246 edge_str = hw->flt_str_p;
1247 internal_str = hw->flt_str_p;
1248 }
1249 }
1250
1251 s->common.src_flt_cfg.pp_corner_filter_strength = corner_str;
1252 s->common.src_flt_cfg.pp_edge_filter_strength = edge_str;
1253 s->common.src_flt_cfg.pp_internal_filter_strength = internal_str;
1254 }
1255
vepu511_h265_set_rc_regs(H265eV511HalContext * ctx,H265eV511RegSet * regs,HalEncTask * task)1256 static void vepu511_h265_set_rc_regs(H265eV511HalContext *ctx, H265eV511RegSet *regs,
1257 HalEncTask *task)
1258 {
1259 H265eSyntax_new *syn = (H265eSyntax_new *)task->syntax.data;
1260 EncRcTaskInfo *rc_cfg = &task->rc_task->info;
1261 H265eVepu511Frame *reg_frm = ®s->reg_frm;
1262 Vepu511RcRoi *reg_rc = ®s->reg_rc_roi;
1263 MppEncCfgSet *cfg = ctx->cfg;
1264 MppEncRcCfg *rc = &cfg->rc;
1265 MppEncHwCfg *hw = &cfg->hw;
1266 MppEncH265Cfg *h265 = &cfg->h265;
1267 RK_S32 mb_wd32 = (syn->pp.pic_width + 31) / 32;
1268 RK_S32 mb_h32 = (syn->pp.pic_height + 31) / 32;
1269
1270 RK_U32 ctu_target_bits_mul_16 = (rc_cfg->bit_target << 4) / (mb_wd32 * mb_h32);
1271 RK_U32 ctu_target_bits;
1272 RK_S32 negative_bits_thd, positive_bits_thd;
1273
1274 if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) {
1275 reg_frm->common.enc_pic.pic_qp = rc_cfg->quality_target;
1276 reg_frm->synt_sli1.sli_qp = rc_cfg->quality_target;
1277 reg_frm->common.rc_qp.rc_max_qp = rc_cfg->quality_target;
1278 reg_frm->common.rc_qp.rc_min_qp = rc_cfg->quality_target;
1279 reg_frm->common.rc_cfg.rc_ctu_num = 1;
1280 } else {
1281 if (ctu_target_bits_mul_16 >= 0x100000) {
1282 ctu_target_bits_mul_16 = 0x50000;
1283 }
1284 ctu_target_bits = (ctu_target_bits_mul_16 * mb_wd32) >> 4;
1285 negative_bits_thd = 0 - 5 * ctu_target_bits / 16;
1286 positive_bits_thd = 5 * ctu_target_bits / 16;
1287
1288 reg_frm->common.enc_pic.pic_qp = rc_cfg->quality_target;
1289 reg_frm->synt_sli1.sli_qp = rc_cfg->quality_target;
1290 reg_frm->common.rc_cfg.rc_en = 1;
1291 reg_frm->common.rc_cfg.aq_en = 1;
1292 reg_frm->common.rc_cfg.rc_ctu_num = mb_wd32;
1293
1294 reg_frm->common.rc_qp.rc_max_qp = rc_cfg->quality_max;
1295 reg_frm->common.rc_qp.rc_min_qp = rc_cfg->quality_min;
1296 reg_frm->common.rc_tgt.ctu_ebit = ctu_target_bits_mul_16;
1297
1298 if (ctx->smart_en) {
1299 reg_frm->common.rc_qp.rc_qp_range = 0;
1300 } else {
1301 reg_frm->common.rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ?
1302 hw->qp_delta_row_i : hw->qp_delta_row;
1303 }
1304
1305 {
1306 /* fixed frame qp */
1307 RK_S32 fqp_min, fqp_max;
1308
1309 if (ctx->frame_type == INTRA_FRAME) {
1310 fqp_min = rc->fqp_min_i;
1311 fqp_max = rc->fqp_max_i;
1312 } else {
1313 fqp_min = rc->fqp_min_p;
1314 fqp_max = rc->fqp_max_p;
1315 }
1316
1317 if ((fqp_min == fqp_max) && (fqp_min >= 0) && (fqp_max <= 51)) {
1318 reg_frm->common.enc_pic.pic_qp = fqp_min;
1319 reg_frm->synt_sli1.sli_qp = fqp_min;
1320 reg_frm->common.rc_qp.rc_qp_range = 0;
1321 }
1322 }
1323
1324 reg_rc->rc_dthd_0_8[0] = 2 * negative_bits_thd;
1325 reg_rc->rc_dthd_0_8[1] = negative_bits_thd;
1326 reg_rc->rc_dthd_0_8[2] = positive_bits_thd;
1327 reg_rc->rc_dthd_0_8[3] = 2 * positive_bits_thd;
1328 reg_rc->rc_dthd_0_8[4] = 0x7FFFFFFF;
1329 reg_rc->rc_dthd_0_8[5] = 0x7FFFFFFF;
1330 reg_rc->rc_dthd_0_8[6] = 0x7FFFFFFF;
1331 reg_rc->rc_dthd_0_8[7] = 0x7FFFFFFF;
1332 reg_rc->rc_dthd_0_8[8] = 0x7FFFFFFF;
1333
1334 reg_rc->rc_adj0.qp_adj0 = -2;
1335 reg_rc->rc_adj0.qp_adj1 = -1;
1336 reg_rc->rc_adj0.qp_adj2 = 0;
1337 reg_rc->rc_adj0.qp_adj3 = 1;
1338 reg_rc->rc_adj0.qp_adj4 = 2;
1339 reg_rc->rc_adj1.qp_adj5 = 0;
1340 reg_rc->rc_adj1.qp_adj6 = 0;
1341 reg_rc->rc_adj1.qp_adj7 = 0;
1342 reg_rc->rc_adj1.qp_adj8 = 0;
1343 }
1344
1345 reg_rc->roi_qthd0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min;
1346 reg_rc->roi_qthd0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max;
1347 reg_rc->roi_qthd0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min;
1348 reg_rc->roi_qthd0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max;
1349 reg_rc->roi_qthd0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;
1350 reg_rc->roi_qthd1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max;
1351 reg_rc->roi_qthd1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;
1352 reg_rc->roi_qthd1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max;
1353 reg_rc->roi_qthd1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;
1354 reg_rc->roi_qthd1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max;
1355 reg_rc->roi_qthd2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;
1356 reg_rc->roi_qthd2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max;
1357 reg_rc->roi_qthd2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;
1358 reg_rc->roi_qthd2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max;
1359 reg_rc->roi_qthd2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;
1360 reg_rc->roi_qthd3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max;
1361 reg_rc->roi_cfg.fmdc_adj1_hevc.fmdc_adju_split32 = 0;
1362 }
1363
vepu511_h265_set_quant_regs(H265eV511HalContext * ctx,H265eV511RegSet * regs)1364 static void vepu511_h265_set_quant_regs(H265eV511HalContext *ctx, H265eV511RegSet *regs)
1365 {
1366 MppEncHwCfg *hw = &ctx->cfg->hw;
1367 // H265eV511RegSet *regs = ctx->regs;
1368 H265eVepu511Param *s = ®s->reg_param;
1369 RK_U8 th0 = 3, th1 = 6, th2 = 13;
1370 RK_U16 bias_i0 = 171, bias_i1 = 171, bias_i2 = 171, bias_i3 = 171;
1371 RK_U16 bias_p0 = 85, bias_p1 = 85, bias_p2 = 85, bias_p3 = 85;
1372 RK_U32 frm_type = ctx->frame_type;
1373
1374 if (!hw->qbias_en) {
1375 if (ctx->smart_en) {
1376 bias_i0 = bias_i1 = bias_i3 = 144;
1377 bias_i2 = (frm_type == INTRA_FRAME) ? 144 : 171;
1378 } else {
1379 bias_i0 = bias_i1 = bias_i3 = 171;
1380 bias_i2 = (frm_type == INTRA_FRAME) ? 171 : 220;
1381 }
1382
1383 /* used for venc_info log */
1384 hw->qbias_arr[IFRAME_THD0] = hw->qbias_arr[PFRAME_THD0] = th0;
1385 hw->qbias_arr[IFRAME_THD1] = hw->qbias_arr[PFRAME_THD1] = th1;
1386 hw->qbias_arr[IFRAME_THD2] = hw->qbias_arr[PFRAME_THD2] = th2;
1387 hw->qbias_arr[IFRAME_BIAS0] = hw->qbias_arr[PFRAME_IBLK_BIAS0] = bias_i0;
1388 hw->qbias_arr[IFRAME_BIAS1] = hw->qbias_arr[PFRAME_IBLK_BIAS1] = bias_i1;
1389 hw->qbias_arr[IFRAME_BIAS2] = hw->qbias_arr[PFRAME_IBLK_BIAS2] = bias_i2;
1390 hw->qbias_arr[IFRAME_BIAS3] = hw->qbias_arr[PFRAME_IBLK_BIAS3] = bias_i3;
1391 hw->qbias_arr[PFRAME_PBLK_BIAS0] = bias_p0;
1392 hw->qbias_arr[PFRAME_PBLK_BIAS1] = bias_p1;
1393 hw->qbias_arr[PFRAME_PBLK_BIAS2] = bias_p2;
1394 hw->qbias_arr[PFRAME_PBLK_BIAS3] = bias_p3;
1395 } else {
1396 if (frm_type == INTRA_FRAME) {
1397 th0 = hw->qbias_arr[IFRAME_THD0];
1398 th1 = hw->qbias_arr[IFRAME_THD1];
1399 th2 = hw->qbias_arr[IFRAME_THD2];
1400 bias_i0 = hw->qbias_arr[IFRAME_BIAS0];
1401 bias_i1 = hw->qbias_arr[IFRAME_BIAS1];
1402 bias_i2 = hw->qbias_arr[IFRAME_BIAS2];
1403 bias_i3 = hw->qbias_arr[IFRAME_BIAS3];
1404 } else {
1405 th0 = hw->qbias_arr[PFRAME_THD0];
1406 th1 = hw->qbias_arr[PFRAME_THD1];
1407 th2 = hw->qbias_arr[PFRAME_THD2];
1408 bias_i0 = hw->qbias_arr[PFRAME_IBLK_BIAS0];
1409 bias_i1 = hw->qbias_arr[PFRAME_IBLK_BIAS1];
1410 bias_i2 = hw->qbias_arr[PFRAME_IBLK_BIAS2];
1411 bias_i3 = hw->qbias_arr[PFRAME_IBLK_BIAS3];
1412 bias_p0 = hw->qbias_arr[PFRAME_PBLK_BIAS0];
1413 bias_p1 = hw->qbias_arr[PFRAME_PBLK_BIAS1];
1414 bias_p2 = hw->qbias_arr[PFRAME_PBLK_BIAS2];
1415 bias_p3 = hw->qbias_arr[PFRAME_PBLK_BIAS3];
1416 }
1417 }
1418
1419 s->bias_madi_thd_comb.bias_madi_th0 = th0;
1420 s->bias_madi_thd_comb.bias_madi_th1 = th1;
1421 s->bias_madi_thd_comb.bias_madi_th2 = th2;
1422 s->qnt0_i_bias_comb.bias_i_val0 = bias_i0;
1423 s->qnt0_i_bias_comb.bias_i_val1 = bias_i1;
1424 s->qnt0_i_bias_comb.bias_i_val2 = bias_i2;
1425 s->qnt1_i_bias_comb.bias_i_val3 = bias_i3;
1426 s->qnt0_p_bias_comb.bias_p_val0 = bias_p0;
1427 s->qnt0_p_bias_comb.bias_p_val1 = bias_p1;
1428 s->qnt0_p_bias_comb.bias_p_val2 = bias_p2;
1429 s->qnt1_p_bias_comb.bias_p_val3 = bias_p3;
1430 }
1431
vepu511_h265_set_atr_regs(H265eV511RegSet * regs)1432 static void vepu511_h265_set_atr_regs(H265eV511RegSet *regs)
1433 {
1434 H265eVepu511Sqi *s = ®s->reg_sqi;
1435 RK_U32 str = 0;
1436
1437 /* 0 - disable; 1 - weak; 2 - medium; 3 - strong */
1438 if (str == 0) {
1439 s->block_opt_cfg.block_en = 0; /* block_en and cmplx_en are not used so far(20240708) */
1440 s->cmplx_opt_cfg.cmplx_en = 0;
1441 s->line_opt_cfg.line_en = 0;
1442 } else {
1443 s->block_opt_cfg.block_en = 0;
1444 s->cmplx_opt_cfg.cmplx_en = 0;
1445 s->line_opt_cfg.line_en = 1;
1446 }
1447
1448 s->subj_opt_cfg.subj_opt_en = 0;
1449 s->subj_opt_cfg.subj_opt_strength = 3;
1450 s->subj_opt_cfg.aq_subj_en = 0;
1451 s->subj_opt_cfg.aq_subj_strength = 4;
1452 s->subj_opt_cfg.bndry_cmplx_static_choose_en = 0;
1453 s->subj_opt_cfg.feature_cal_en = 0;
1454 s->subj_opt_dpth_thd.common_thre_num_grdn_point_dep0 = 64;
1455 s->subj_opt_dpth_thd.common_thre_num_grdn_point_dep1 = 32;
1456 s->subj_opt_dpth_thd.common_thre_num_grdn_point_dep2 = 16;
1457
1458 if (str == 3) {
1459 s->block_opt_cfg.block_thre_cst_best_mad = 1000;
1460 s->block_opt_cfg.block_thre_cst_best_grdn_blk = 39;
1461 s->block_opt_cfg.thre_num_grdnt_point_cmplx = 3;
1462 s->block_opt_cfg.block_delta_qp_flag = 3;
1463
1464 s->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 4000;
1465 s->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000;
1466
1467 s->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2 = 200;
1468 s->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0 = 977;
1469
1470 s->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0;
1471 s->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 488;
1472
1473 s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 4;
1474 s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 30;
1475 s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 30;
1476 s->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0 = 7;
1477 s->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1 = 6;
1478
1479 s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1;
1480 s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 50;
1481 s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 50;
1482
1483 s->subj_opt_dqp0.line_thre_qp = 20;
1484 s->subj_opt_dqp0.block_strength = 4;
1485 s->subj_opt_dqp0.block_thre_qp = 30;
1486 s->subj_opt_dqp0.cmplx_strength = 4;
1487 s->subj_opt_dqp0.cmplx_thre_qp = 34;
1488 s->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32;
1489 } else if (str == 2) {
1490 s->block_opt_cfg.block_thre_cst_best_mad = 1000;
1491 s->block_opt_cfg.block_thre_cst_best_grdn_blk = 39;
1492 s->block_opt_cfg.thre_num_grdnt_point_cmplx = 3;
1493 s->block_opt_cfg.block_delta_qp_flag = 3;
1494
1495 s->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 4000;
1496 s->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000;
1497
1498 s->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2 = 200;
1499 s->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0 = 977;
1500
1501 s->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0;
1502 s->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 488;
1503
1504 s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 3;
1505 s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 20;
1506 s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 20;
1507 s->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0 = 7;
1508 s->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1 = 8;
1509
1510 s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1;
1511 s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 60;
1512 s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 60;
1513
1514 s->subj_opt_dqp0.line_thre_qp = 25;
1515 s->subj_opt_dqp0.block_strength = 4;
1516 s->subj_opt_dqp0.block_thre_qp = 30;
1517 s->subj_opt_dqp0.cmplx_strength = 4;
1518 s->subj_opt_dqp0.cmplx_thre_qp = 34;
1519 s->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32;
1520 } else {
1521 s->block_opt_cfg.block_thre_cst_best_mad = 1000;
1522 s->block_opt_cfg.block_thre_cst_best_grdn_blk = 39;
1523 s->block_opt_cfg.thre_num_grdnt_point_cmplx = 3;
1524 s->block_opt_cfg.block_delta_qp_flag = 3;
1525
1526 s->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 6000;
1527 s->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000;
1528
1529 s->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2 = 300;
1530 s->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0 = 1280;
1531
1532 s->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0;
1533 s->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 512;
1534
1535 s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 3;
1536 s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 20;
1537 s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 20;
1538 s->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0 = 7;
1539 s->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1 = 8;
1540
1541 s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1;
1542 s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 70;
1543 s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 70;
1544
1545 s->subj_opt_dqp0.line_thre_qp = 30;
1546 s->subj_opt_dqp0.block_strength = 4;
1547 s->subj_opt_dqp0.block_thre_qp = 30;
1548 s->subj_opt_dqp0.cmplx_strength = 4;
1549 s->subj_opt_dqp0.cmplx_thre_qp = 34;
1550 s->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32;
1551 }
1552 }
1553
vepu511_h265_set_smear_regs(H265eV511HalContext * ctx,H265eV511RegSet * regs)1554 static void vepu511_h265_set_smear_regs(H265eV511HalContext *ctx, H265eV511RegSet *regs)
1555 {
1556 H265eVepu511Sqi *s = ®s->reg_sqi;
1557 RK_S32 frm_num = ctx->frame_num;
1558 RK_S32 gop = (ctx->cfg->rc.gop > 0) ? ctx->cfg->rc.gop : 0x7FFFFFFF;
1559 RK_U32 cover_num = ctx->last_frame_fb.acc_cover16_num;
1560 RK_U32 bndry_num = ctx->last_frame_fb.acc_bndry16_num;
1561 RK_U32 st_ctu_num = ctx->last_frame_fb.st_ctu_num;
1562 RK_S32 str = ctx->cfg->tune.deblur_str;
1563 RK_S16 flag_cover = 0;
1564 RK_S16 flag_bndry = 0;
1565
1566 static RK_U8 qp_strength[H265E_SMEAR_STR_NUM] = { 4, 6, 7, 7, 3, 5, 7, 7 };
1567 static RK_U8 smear_strength[H265E_SMEAR_STR_NUM] = { 1, 1, 1, 1, 1, 1, 1, 1 };
1568 static RK_U8 bndry_intra_r_dep0[H265E_SMEAR_STR_NUM] = { 240, 240, 240, 240, 240, 240, 240, 240 };
1569 static RK_U8 bndry_intra_r_dep1[H265E_SMEAR_STR_NUM] = { 240, 240, 240, 240, 240, 240, 240, 240 };
1570 static RK_U8 thre_madp_stc_cover0[H265E_SMEAR_STR_NUM] = { 20, 22, 22, 22, 20, 22, 22, 30 };
1571 static RK_U8 thre_madp_stc_cover1[H265E_SMEAR_STR_NUM] = { 20, 22, 22, 22, 20, 22, 22, 30 };
1572 static RK_U8 thre_madp_mov_cover0[H265E_SMEAR_STR_NUM] = { 10, 9, 9, 9, 10, 9, 9, 6 };
1573 static RK_U8 thre_madp_mov_cover1[H265E_SMEAR_STR_NUM] = { 10, 9, 9, 9, 10, 9, 9, 6 };
1574
1575 static RK_U8 flag_cover_thd0[H265E_SMEAR_STR_NUM] = { 12, 13, 13, 13, 12, 13, 13, 17 };
1576 static RK_U8 flag_cover_thd1[H265E_SMEAR_STR_NUM] = { 61, 70, 70, 70, 61, 70, 70, 90 };
1577 static RK_U8 flag_bndry_thd0[H265E_SMEAR_STR_NUM] = { 12, 12, 12, 12, 12, 12, 12, 12 };
1578 static RK_U8 flag_bndry_thd1[H265E_SMEAR_STR_NUM] = { 73, 73, 73, 73, 73, 73, 73, 73 };
1579
1580 static RK_S8 flag_cover_wgt[3] = { 1, 0, -3 };
1581 static RK_S8 flag_bndry_wgt[3] = { 0, 0, 0 };
1582 static RK_S8 flag_bndry_intra_wgt0[3] = { -12, 0, 12 };
1583 static RK_S8 flag_bndry_intra_wgt1[3] = { -12, 0, 12 };
1584
1585 flag_cover = (cover_num * 1000 < flag_cover_thd0[str] * st_ctu_num) ? 0 :
1586 (cover_num * 1000 < flag_cover_thd1[str] * st_ctu_num) ? 1 : 2;
1587
1588 flag_bndry = (bndry_num * 1000 < flag_bndry_thd0[str] * st_ctu_num) ? 0 :
1589 (bndry_num * 1000 < flag_bndry_thd1[str] * st_ctu_num) ? 1 : 2;
1590
1591 /* anti smear */
1592 s->smear_opt_cfg0.anti_smear_en = ctx->cfg->tune.deblur_en;
1593 s->smear_opt_cfg0.smear_strength = (smear_strength[str] > 2) ?
1594 (smear_strength[str] + flag_bndry_wgt[flag_bndry]) : smear_strength[str];
1595
1596 s->smear_opt_cfg0.thre_mv_inconfor_cime = 8;
1597 s->smear_opt_cfg0.thre_mv_confor_cime = 2;
1598 s->smear_opt_cfg0.thre_mv_inconfor_cime_gmv = 8;
1599 s->smear_opt_cfg0.thre_mv_confor_cime_gmv = 2;
1600 s->smear_opt_cfg0.thre_num_mv_confor_cime = 3;
1601 s->smear_opt_cfg0.thre_num_mv_confor_cime_gmv = 2;
1602 s->smear_opt_cfg0.frm_static = 1;
1603
1604 s->smear_opt_cfg0.smear_load_en = ((frm_num % gop == 0) ||
1605 (s->smear_opt_cfg0.frm_static == 0) || (frm_num % gop == 1)) ? 0 : 1;
1606 s->smear_opt_cfg0.smear_stor_en = ((frm_num % gop == 0) ||
1607 (s->smear_opt_cfg0.frm_static == 0) || (frm_num % gop == gop - 1)) ? 0 : 1;
1608 s->smear_opt_cfg1.dist0_frm_avg = 0;
1609 s->smear_opt_cfg1.thre_dsp_static = 10;
1610 s->smear_opt_cfg1.thre_dsp_mov = 15;
1611 s->smear_opt_cfg1.thre_dist_mv_confor_cime = 32;
1612
1613 s->smear_madp_thd.thre_madp_stc_dep0 = 10;
1614 s->smear_madp_thd.thre_madp_stc_dep1 = 8;
1615 s->smear_madp_thd.thre_madp_stc_dep2 = 8;
1616 s->smear_madp_thd.thre_madp_mov_dep0 = 16;
1617 s->smear_madp_thd.thre_madp_mov_dep1 = 18;
1618 s->smear_madp_thd.thre_madp_mov_dep2 = 20;
1619
1620 s->smear_stat_thd.thre_num_pt_stc_dep0 = 47;
1621 s->smear_stat_thd.thre_num_pt_stc_dep1 = 11;
1622 s->smear_stat_thd.thre_num_pt_stc_dep2 = 3;
1623 s->smear_stat_thd.thre_num_pt_mov_dep0 = 47;
1624 s->smear_stat_thd.thre_num_pt_mov_dep1 = 11;
1625 s->smear_stat_thd.thre_num_pt_mov_dep2 = 3;
1626
1627 s->smear_bmv_dist_thd0.confor_cime_gmv0 = 21;
1628 s->smear_bmv_dist_thd0.confor_cime_gmv1 = 16;
1629 s->smear_bmv_dist_thd0.inconfor_cime_gmv0 = 48;
1630 s->smear_bmv_dist_thd0.inconfor_cime_gmv1 = 34;
1631
1632 s->smear_bmv_dist_thd1.inconfor_cime_gmv2 = 32;
1633 s->smear_bmv_dist_thd1.inconfor_cime_gmv3 = 29;
1634 s->smear_bmv_dist_thd1.inconfor_cime_gmv4 = 27;
1635
1636 s->smear_min_bndry_gmv.thre_min_num_confor_csu0_bndry_cime_gmv = 0;
1637 s->smear_min_bndry_gmv.thre_max_num_confor_csu0_bndry_cime_gmv = 3;
1638 s->smear_min_bndry_gmv.thre_min_num_inconfor_csu0_bndry_cime_gmv = 0;
1639 s->smear_min_bndry_gmv.thre_max_num_inconfor_csu0_bndry_cime_gmv = 3;
1640 s->smear_min_bndry_gmv.thre_split_dep0 = 2;
1641 s->smear_min_bndry_gmv.thre_zero_srgn = 8;
1642 s->smear_min_bndry_gmv.madi_thre_dep0 = 22;
1643 s->smear_min_bndry_gmv.madi_thre_dep1 = 18;
1644
1645 s->smear_madp_cov_thd.thre_madp_stc_cover0 = thre_madp_stc_cover0[str];
1646 s->smear_madp_cov_thd.thre_madp_stc_cover1 = thre_madp_stc_cover1[str];
1647 s->smear_madp_cov_thd.thre_madp_mov_cover0 = thre_madp_mov_cover0[str];
1648 s->smear_madp_cov_thd.thre_madp_mov_cover1 = thre_madp_mov_cover1[str];
1649 s->smear_madp_cov_thd.smear_qp_strength = qp_strength[str] +
1650 flag_cover_wgt[flag_cover];
1651 s->smear_madp_cov_thd.smear_thre_qp = 30;
1652
1653 s->subj_opt_dqp1.bndry_rdo_mode_intra_jcoef_d0 = bndry_intra_r_dep0[str] +
1654 flag_bndry_intra_wgt0[flag_bndry];
1655 s->subj_opt_dqp1.bndry_rdo_mode_intra_jcoef_d1 = bndry_intra_r_dep1[str] +
1656 flag_bndry_intra_wgt1[flag_bndry];
1657
1658 s->subj_opt_dqp1.skin_thre_qp = 31;
1659 s->subj_opt_dqp1.skin_thre_madp = 64;
1660 s->subj_opt_dqp1.bndry_rdo_mode_intra_jcoef_d0 = 15;
1661 s->subj_opt_dqp1.bndry_rdo_mode_intra_jcoef_d1 = 14;
1662 s->subj_opt_dqp1.smear_frame_thre_qp = 35;
1663 s->subj_opt_rdo_split.line_rdo_split_rcoef_d0 = 11;
1664 s->subj_opt_rdo_split.line_rdo_split_rcoef_d1 = 13;
1665
1666 s->subj_opt_inrar_coef.cover_rmd_mode_intra_jcoef_d0 = 8;
1667 s->subj_opt_inrar_coef.cover_rmd_mode_intra_jcoef_d1 = 8;
1668 s->subj_opt_inrar_coef.cover_rdo_mode_intra_jcoef_d0 = 12;
1669 s->subj_opt_inrar_coef.cover_rdo_mode_intra_jcoef_d1 = 10;
1670 s->subj_opt_inrar_coef.cover_rdoq_rcoef_d0 = 7;
1671 s->subj_opt_inrar_coef.cover_rdoq_rcoef_d1 = 7;
1672
1673 s->smear_opt_cfc_coef.cfc_rmd_mode_intra_jcoef_d0 = 20;
1674 s->smear_opt_cfc_coef.cfc_rmd_mode_intra_jcoef_d1 = 20;
1675 s->smear_opt_cfc_coef.cfc_rdo_mode_intra_jcoef_d0 = 20;
1676 s->smear_opt_cfc_coef.cfc_rdo_mode_intra_jcoef_d1 = 20;
1677 s->smear_opt_cfc_coef.cfc_rdoq_rcoef_d0 = 7;
1678 s->smear_opt_cfc_coef.cfc_rdoq_rcoef_d1 = 7;
1679
1680 s->subj_opt_rdo_split.choose_cu32_split_jcoef = 20;
1681 s->subj_opt_rdo_split.choose_cu16_split_jcoef = 8;
1682 }
1683
vepu511_h265_set_anti_stripe_regs(H265eV511HalContext * ctx,H265eV511RegSet * regs)1684 static void vepu511_h265_set_anti_stripe_regs(H265eV511HalContext *ctx, H265eV511RegSet *regs)
1685 {
1686 H265eVepu511Sqi *s = ®s->reg_sqi;
1687 pre_cst_par* pre_i32 = (pre_cst_par*)&s->preintra32_cst;
1688 pre_cst_par* pre_i16 = (pre_cst_par*)&s->preintra16_cst;
1689
1690 pre_i32->cst_wgt3.anti_strp_e = !!ctx->cfg->tune.atl_str;
1691
1692 pre_i32->cst_madi_thd0.madi_thd0 = 5;
1693 pre_i32->cst_madi_thd0.madi_thd1 = 15;
1694 pre_i32->cst_madi_thd0.madi_thd2 = 5;
1695 pre_i32->cst_madi_thd0.madi_thd3 = 3;
1696 pre_i32->cst_madi_thd1.madi_thd4 = 3;
1697 pre_i32->cst_madi_thd1.madi_thd5 = 6;
1698 pre_i32->cst_madi_thd1.madi_thd6 = 7;
1699 pre_i32->cst_madi_thd1.madi_thd7 = 5;
1700 pre_i32->cst_madi_thd2.madi_thd8 = 10;
1701 pre_i32->cst_madi_thd2.madi_thd9 = 5;
1702 pre_i32->cst_madi_thd2.madi_thd10 = 7;
1703 pre_i32->cst_madi_thd2.madi_thd11 = 5;
1704 pre_i32->cst_madi_thd3.madi_thd12 = 7;
1705 pre_i32->cst_madi_thd3.madi_thd13 = 5;
1706 pre_i32->cst_madi_thd3.mode_th = 5;
1707
1708 pre_i32->cst_wgt0.wgt0 = 20;
1709 pre_i32->cst_wgt0.wgt1 = 18;
1710 pre_i32->cst_wgt0.wgt2 = 19;
1711 pre_i32->cst_wgt0.wgt3 = 18;
1712 pre_i32->cst_wgt1.wgt4 = 12;
1713 pre_i32->cst_wgt1.wgt5 = 6;
1714 pre_i32->cst_wgt1.wgt6 = 13;
1715 pre_i32->cst_wgt1.wgt7 = 9;
1716 pre_i32->cst_wgt2.wgt8 = 12;
1717 pre_i32->cst_wgt2.wgt9 = 6;
1718 pre_i32->cst_wgt2.wgt10 = 13;
1719 pre_i32->cst_wgt2.wgt11 = 9;
1720 pre_i32->cst_wgt3.wgt12 = 18;
1721 pre_i32->cst_wgt3.wgt13 = 17;
1722 pre_i32->cst_wgt3.wgt14 = 17;
1723
1724 pre_i16->cst_madi_thd0.madi_thd0 = 5;
1725 pre_i16->cst_madi_thd0.madi_thd1 = 15;
1726 pre_i16->cst_madi_thd0.madi_thd2 = 5;
1727 pre_i16->cst_madi_thd0.madi_thd3 = 3;
1728 pre_i16->cst_madi_thd1.madi_thd4 = 3;
1729 pre_i16->cst_madi_thd1.madi_thd5 = 6;
1730 pre_i16->cst_madi_thd1.madi_thd6 = 7;
1731 pre_i16->cst_madi_thd1.madi_thd7 = 5;
1732 pre_i16->cst_madi_thd2.madi_thd8 = 10;
1733 pre_i16->cst_madi_thd2.madi_thd9 = 5;
1734 pre_i16->cst_madi_thd2.madi_thd10 = 7;
1735 pre_i16->cst_madi_thd2.madi_thd11 = 5;
1736 pre_i16->cst_madi_thd3.madi_thd12 = 7;
1737 pre_i16->cst_madi_thd3.madi_thd13 = 5;
1738 pre_i16->cst_madi_thd3.mode_th = 5;
1739
1740 pre_i16->cst_wgt0.wgt0 = 20;
1741 pre_i16->cst_wgt0.wgt1 = 18;
1742 pre_i16->cst_wgt0.wgt2 = 19;
1743 pre_i16->cst_wgt0.wgt3 = 18;
1744 pre_i16->cst_wgt1.wgt4 = 12;
1745 pre_i16->cst_wgt1.wgt5 = 6;
1746 pre_i16->cst_wgt1.wgt6 = 13;
1747 pre_i16->cst_wgt1.wgt7 = 9;
1748 pre_i16->cst_wgt2.wgt8 = 12;
1749 pre_i16->cst_wgt2.wgt9 = 6;
1750 pre_i16->cst_wgt2.wgt10 = 13;
1751 pre_i16->cst_wgt2.wgt11 = 9;
1752 pre_i16->cst_wgt3.wgt12 = 18;
1753 pre_i16->cst_wgt3.wgt13 = 17;
1754 pre_i16->cst_wgt3.wgt14 = 17;
1755
1756 pre_i32->cst_madi_thd3.qp_thd = 28;
1757 pre_i32->cst_wgt3.lambda_mv_bit_0 = 5; // lv32
1758 pre_i32->cst_wgt3.lambda_mv_bit_1 = 4; // lv16
1759 pre_i16->cst_wgt3.lambda_mv_bit_0 = 4; // lv8
1760 pre_i16->cst_wgt3.lambda_mv_bit_1 = 3; // lv4
1761 }
1762
vepu511_h265_set_rdo_regs(H265eV511RegSet * regs)1763 static MPP_RET vepu511_h265_set_rdo_regs(H265eV511RegSet *regs)
1764 {
1765 Vepu511RcRoi *reg_rc = ®s->reg_rc_roi;
1766
1767 reg_rc->cudecis_thd0.base_thre_rough_mad32_intra = 9;
1768 reg_rc->cudecis_thd0.delta0_thre_rough_mad32_intra = 10;
1769 reg_rc->cudecis_thd0.delta1_thre_rough_mad32_intra = 55;
1770 reg_rc->cudecis_thd0.delta2_thre_rough_mad32_intra = 55;
1771 reg_rc->cudecis_thd0.delta3_thre_rough_mad32_intra = 66;
1772 reg_rc->cudecis_thd0.delta4_thre_rough_mad32_intra_low5 = 2;
1773
1774 reg_rc->cudecis_thd1.delta4_thre_rough_mad32_intra_high2 = 2;
1775 reg_rc->cudecis_thd1.delta5_thre_rough_mad32_intra = 74;
1776 reg_rc->cudecis_thd1.delta6_thre_rough_mad32_intra = 106;
1777 reg_rc->cudecis_thd1.base_thre_fine_mad32_intra = 8;
1778 reg_rc->cudecis_thd1.delta0_thre_fine_mad32_intra = 0;
1779 reg_rc->cudecis_thd1.delta1_thre_fine_mad32_intra = 13;
1780 reg_rc->cudecis_thd1.delta2_thre_fine_mad32_intra_low3 = 6;
1781
1782 reg_rc->cudecis_thd2.delta2_thre_fine_mad32_intra_high2 = 1;
1783 reg_rc->cudecis_thd2.delta3_thre_fine_mad32_intra = 17;
1784 reg_rc->cudecis_thd2.delta4_thre_fine_mad32_intra = 23;
1785 reg_rc->cudecis_thd2.delta5_thre_fine_mad32_intra = 50;
1786 reg_rc->cudecis_thd2.delta6_thre_fine_mad32_intra = 54;
1787 reg_rc->cudecis_thd2.base_thre_str_edge_mad32_intra = 6;
1788 reg_rc->cudecis_thd2.delta0_thre_str_edge_mad32_intra = 0;
1789 reg_rc->cudecis_thd2.delta1_thre_str_edge_mad32_intra = 0;
1790
1791 reg_rc->cudecis_thd3.delta2_thre_str_edge_mad32_intra = 3;
1792 reg_rc->cudecis_thd3.delta3_thre_str_edge_mad32_intra = 8;
1793 reg_rc->cudecis_thd3.base_thre_str_edge_bgrad32_intra = 25;
1794 reg_rc->cudecis_thd3.delta0_thre_str_edge_bgrad32_intra = 0;
1795 reg_rc->cudecis_thd3.delta1_thre_str_edge_bgrad32_intra = 0;
1796 reg_rc->cudecis_thd3.delta2_thre_str_edge_bgrad32_intra = 7;
1797 reg_rc->cudecis_thd3.delta3_thre_str_edge_bgrad32_intra = 19;
1798 reg_rc->cudecis_thd3.base_thre_mad16_intra = 6;
1799 reg_rc->cudecis_thd3.delta0_thre_mad16_intra = 0;
1800
1801 reg_rc->cudecis_thd4.delta1_thre_mad16_intra = 3;
1802 reg_rc->cudecis_thd4.delta2_thre_mad16_intra = 3;
1803 reg_rc->cudecis_thd4.delta3_thre_mad16_intra = 24;
1804 reg_rc->cudecis_thd4.delta4_thre_mad16_intra = 28;
1805 reg_rc->cudecis_thd4.delta5_thre_mad16_intra = 40;
1806 reg_rc->cudecis_thd4.delta6_thre_mad16_intra = 52;
1807 reg_rc->cudecis_thd4.delta0_thre_mad16_ratio_intra = 7;
1808
1809 reg_rc->cudecis_thd5.delta1_thre_mad16_ratio_intra = 7;
1810 reg_rc->cudecis_thd5.delta2_thre_mad16_ratio_intra = 2;
1811 reg_rc->cudecis_thd5.delta3_thre_mad16_ratio_intra = 2;
1812 reg_rc->cudecis_thd5.delta4_thre_mad16_ratio_intra = 0;
1813 reg_rc->cudecis_thd5.delta5_thre_mad16_ratio_intra = 0;
1814 reg_rc->cudecis_thd5.delta6_thre_mad16_ratio_intra = 0;
1815 reg_rc->cudecis_thd5.delta7_thre_mad16_ratio_intra = 4;
1816 reg_rc->cudecis_thd5.delta0_thre_rough_bgrad32_intra = 1;
1817 reg_rc->cudecis_thd5.delta1_thre_rough_bgrad32_intra = 5;
1818 reg_rc->cudecis_thd5.delta2_thre_rough_bgrad32_intra_low4 = 8;
1819
1820 reg_rc->cudecis_thd6.delta2_thre_rough_bgrad32_intra_high2 = 2;
1821 reg_rc->cudecis_thd6.delta3_thre_rough_bgrad32_intra = 540;
1822 reg_rc->cudecis_thd6.delta4_thre_rough_bgrad32_intra = 692;
1823 reg_rc->cudecis_thd6.delta5_thre_rough_bgrad32_intra_low10 = 866;
1824
1825 reg_rc->cudecis_thd7.delta5_thre_rough_bgrad32_intra_high1 = 1;
1826 reg_rc->cudecis_thd7.delta6_thre_rough_bgrad32_intra = 3286;
1827 reg_rc->cudecis_thd7.delta7_thre_rough_bgrad32_intra = 6620;
1828 reg_rc->cudecis_thd7.delta0_thre_bgrad16_ratio_intra = 8;
1829 reg_rc->cudecis_thd7.delta1_thre_bgrad16_ratio_intra_low2 = 3;
1830
1831 reg_rc->cudecis_thd8.delta1_thre_bgrad16_ratio_intra_high2 = 2;
1832 reg_rc->cudecis_thd8.delta2_thre_bgrad16_ratio_intra = 15;
1833 reg_rc->cudecis_thd8.delta3_thre_bgrad16_ratio_intra = 15;
1834 reg_rc->cudecis_thd8.delta4_thre_bgrad16_ratio_intra = 13;
1835 reg_rc->cudecis_thd8.delta5_thre_bgrad16_ratio_intra = 13;
1836 reg_rc->cudecis_thd8.delta6_thre_bgrad16_ratio_intra = 7;
1837 reg_rc->cudecis_thd8.delta7_thre_bgrad16_ratio_intra = 15;
1838 reg_rc->cudecis_thd8.delta0_thre_fme_ratio_inter = 4;
1839 reg_rc->cudecis_thd8.delta1_thre_fme_ratio_inter = 4;
1840
1841 reg_rc->cudecis_thd9.delta2_thre_fme_ratio_inter = 3;
1842 reg_rc->cudecis_thd9.delta3_thre_fme_ratio_inter = 2;
1843 reg_rc->cudecis_thd9.delta4_thre_fme_ratio_inter = 0;
1844 reg_rc->cudecis_thd9.delta5_thre_fme_ratio_inter = 0;
1845 reg_rc->cudecis_thd9.delta6_thre_fme_ratio_inter = 0;
1846 reg_rc->cudecis_thd9.delta7_thre_fme_ratio_inter = 0;
1847 reg_rc->cudecis_thd9.base_thre_fme32_inter = 4;
1848 reg_rc->cudecis_thd9.delta0_thre_fme32_inter = 2;
1849 reg_rc->cudecis_thd9.delta1_thre_fme32_inter = 7;
1850 reg_rc->cudecis_thd9.delta2_thre_fme32_inter = 12;
1851
1852 reg_rc->cudecis_thd10.delta3_thre_fme32_inter = 23;
1853 reg_rc->cudecis_thd10.delta4_thre_fme32_inter = 41;
1854 reg_rc->cudecis_thd10.delta5_thre_fme32_inter = 71;
1855 reg_rc->cudecis_thd10.delta6_thre_fme32_inter = 123;
1856 reg_rc->cudecis_thd10.thre_cme32_inter = 48;
1857
1858 reg_rc->cudecis_thd11.delta0_thre_mad_fme_ratio_inter = 0;
1859 reg_rc->cudecis_thd11.delta1_thre_mad_fme_ratio_inter = 7;
1860 reg_rc->cudecis_thd11.delta2_thre_mad_fme_ratio_inter = 7;
1861 reg_rc->cudecis_thd11.delta3_thre_mad_fme_ratio_inter = 6;
1862 reg_rc->cudecis_thd11.delta4_thre_mad_fme_ratio_inter = 5;
1863 reg_rc->cudecis_thd11.delta5_thre_mad_fme_ratio_inter = 4;
1864 reg_rc->cudecis_thd11.delta6_thre_mad_fme_ratio_inter = 4;
1865 reg_rc->cudecis_thd11.delta7_thre_mad_fme_ratio_inter = 4;
1866
1867 reg_rc->cudecis_thd12.delta0_thre_mad_fme_ratio_inter = 1;
1868 reg_rc->cudecis_thd12.delta1_thre_mad_fme_ratio_inter = 3;
1869 reg_rc->cudecis_thd12.delta2_thre_mad_fme_ratio_inter = 6;
1870 reg_rc->cudecis_thd12.delta3_thre_mad_fme_ratio_inter = 9;
1871 reg_rc->cudecis_thd12.delta4_thre_mad_fme_ratio_inter = 10;
1872 reg_rc->cudecis_thd12.delta5_thre_mad_fme_ratio_inter = 11;
1873 reg_rc->cudecis_thd12.delta6_thre_mad_fme_ratio_inter = 12;
1874 reg_rc->cudecis_thd12.delta7_thre_mad_fme_ratio_inter = 15;
1875
1876 return MPP_OK;
1877 }
1878
vepu511_h265_set_sao_regs(H265eV511RegSet * regs)1879 static void vepu511_h265_set_sao_regs(H265eV511RegSet *regs)
1880 {
1881 H265eVepu511Sqi *sqi = ®s->reg_sqi;
1882
1883 /* Weight values are set to 4 to disable SAO subjective optimization.
1884 * They are not under the control of anti_blur_en.
1885 */
1886 sqi->subj_anti_blur_wgt3.merge_cost_dist_eo_wgt0 = 4;
1887 sqi->subj_anti_blur_wgt3.merge_cost_dist_bo_wgt0 = 4;
1888 sqi->subj_anti_blur_wgt4.merge_cost_dist_eo_wgt1 = 4;
1889 sqi->subj_anti_blur_wgt4.merge_cost_dist_bo_wgt1 = 4;
1890 sqi->subj_anti_blur_wgt4.merge_cost_bit_eo_wgt0 = 4;
1891 sqi->subj_anti_blur_wgt4.merge_cost_bit_bo_wgt0 = 4;
1892 }
1893
vepu511_h265_set_slice_regs(H265eSyntax_new * syn,H265eVepu511Frame * regs)1894 static void vepu511_h265_set_slice_regs(H265eSyntax_new *syn, H265eVepu511Frame *regs)
1895 {
1896 regs->synt_sps.smpl_adpt_ofst_e = syn->pp.sample_adaptive_offset_enabled_flag;
1897 regs->synt_sps.num_st_ref_pic = syn->pp.num_short_term_ref_pic_sets;
1898 regs->synt_sps.num_lt_ref_pic = syn->pp.num_long_term_ref_pics_sps;
1899 regs->synt_sps.lt_ref_pic_prsnt = syn->pp.long_term_ref_pics_present_flag;
1900 regs->synt_sps.tmpl_mvp_e = syn->pp.sps_temporal_mvp_enabled_flag;
1901 regs->synt_sps.log2_max_poc_lsb = syn->pp.log2_max_pic_order_cnt_lsb_minus4;
1902 regs->synt_sps.strg_intra_smth = syn->pp.strong_intra_smoothing_enabled_flag;
1903
1904 regs->synt_pps.dpdnt_sli_seg_en = syn->pp.dependent_slice_segments_enabled_flag;
1905 regs->synt_pps.out_flg_prsnt_flg = syn->pp.output_flag_present_flag;
1906 regs->synt_pps.num_extr_sli_hdr = syn->pp.num_extra_slice_header_bits;
1907 regs->synt_pps.sgn_dat_hid_en = syn->pp.sign_data_hiding_enabled_flag;
1908 regs->synt_pps.cbc_init_prsnt_flg = syn->pp.cabac_init_present_flag;
1909 regs->synt_pps.pic_init_qp = syn->pp.init_qp_minus26 + 26;
1910 regs->synt_pps.cu_qp_dlt_en = syn->pp.cu_qp_delta_enabled_flag;
1911 regs->synt_pps.chrm_qp_ofst_prsn = syn->pp.pps_slice_chroma_qp_offsets_present_flag;
1912 regs->synt_pps.lp_fltr_acrs_sli = syn->pp.pps_loop_filter_across_slices_enabled_flag;
1913 regs->synt_pps.dblk_fltr_ovrd_en = syn->pp.deblocking_filter_override_enabled_flag;
1914 regs->synt_pps.lst_mdfy_prsnt_flg = syn->pp.lists_modification_present_flag;
1915 regs->synt_pps.sli_seg_hdr_extn = syn->pp.slice_segment_header_extension_present_flag;
1916 regs->synt_pps.cu_qp_dlt_depth = syn->pp.diff_cu_qp_delta_depth;
1917 regs->synt_pps.lpf_fltr_acrs_til = syn->pp.loop_filter_across_tiles_enabled_flag;
1918
1919 regs->synt_sli0.cbc_init_flg = syn->sp.cbc_init_flg;
1920 regs->synt_sli0.mvd_l1_zero_flg = syn->sp.mvd_l1_zero_flg;
1921 regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
1922
1923 regs->synt_sli0.num_refidx_l1_act = syn->sp.num_refidx_l1_act;
1924 regs->synt_sli0.num_refidx_l0_act = syn->sp.num_refidx_l0_act;
1925
1926 regs->synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd;
1927
1928 regs->synt_sli0.sli_sao_chrm_flg = syn->sp.sli_sao_chrm_flg;
1929 regs->synt_sli0.sli_sao_luma_flg = syn->sp.sli_sao_luma_flg;
1930 regs->synt_sli0.sli_tmprl_mvp_e = syn->sp.sli_tmprl_mvp_en;
1931 regs->common.enc_pic.num_pic_tot_cur_hevc = syn->sp.tot_poc_num;
1932
1933 regs->synt_sli0.pic_out_flg = syn->sp.pic_out_flg;
1934 regs->synt_sli0.sli_type = syn->sp.slice_type;
1935 regs->synt_sli0.sli_rsrv_flg = syn->sp.slice_rsrv_flg;
1936 regs->synt_sli0.dpdnt_sli_seg_flg = syn->sp.dpdnt_sli_seg_flg;
1937 regs->synt_sli0.sli_pps_id = syn->sp.sli_pps_id;
1938 regs->synt_sli0.no_out_pri_pic = syn->sp.no_out_pri_pic;
1939
1940
1941 regs->synt_sli1.sp_tc_ofst_div2 = syn->sp.sli_tc_ofst_div2;;
1942 regs->synt_sli1.sp_beta_ofst_div2 = syn->sp.sli_beta_ofst_div2;
1943 regs->synt_sli1.sli_lp_fltr_acrs_sli = syn->sp.sli_lp_fltr_acrs_sli;
1944 regs->synt_sli1.sp_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis;
1945 regs->synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg;
1946 regs->synt_sli1.sli_cb_qp_ofst = syn->pp.pps_slice_chroma_qp_offsets_present_flag ?
1947 syn->sp.sli_cb_qp_ofst : syn->pp.pps_cb_qp_offset;
1948 regs->synt_sli1.max_mrg_cnd = 1;
1949
1950 regs->synt_sli1.col_ref_idx = syn->sp.col_ref_idx;
1951 regs->synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg;
1952 regs->synt_sli2.sli_poc_lsb = syn->sp.sli_poc_lsb;
1953 regs->synt_sli2.sli_hdr_ext_len = syn->sp.sli_hdr_ext_len;
1954 }
1955
vepu511_h265_set_ref_regs(H265eSyntax_new * syn,H265eVepu511Frame * regs)1956 static void vepu511_h265_set_ref_regs(H265eSyntax_new *syn, H265eVepu511Frame *regs)
1957 {
1958 regs->synt_refm0.st_ref_pic_flg = syn->sp.st_ref_pic_flg;
1959 regs->synt_refm0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0;
1960 regs->synt_refm0.num_lt_pic = syn->sp.num_lt_pic;
1961
1962 regs->synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
1963 regs->synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
1964 regs->synt_refm1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0;
1965 regs->synt_refm1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1;
1966 regs->synt_refm1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2;
1967 regs->synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
1968 regs->synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
1969 regs->synt_refm1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1;
1970 regs->synt_refm1.num_negative_pics = syn->sp.num_neg_pic;
1971 regs->synt_refm1.num_pos_pic = syn->sp.num_pos_pic;
1972
1973 regs->synt_refm1.used_by_s0_flg = syn->sp.used_by_s0_flg;
1974 regs->synt_refm2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10;
1975 regs->synt_refm2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11;
1976 regs->synt_refm3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12;
1977 regs->synt_refm3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13;
1978
1979 regs->synt_long_refm0.poc_lsb_lt1 = syn->sp.poc_lsb_lt1;
1980 regs->synt_long_refm1.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1;
1981 regs->synt_long_refm0.poc_lsb_lt2 = syn->sp.poc_lsb_lt2;
1982 regs->synt_refm1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2;
1983 regs->synt_long_refm1.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2;
1984 regs->synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0;
1985 regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
1986
1987 return;
1988 }
1989
vepu511_h265_set_atf_regs(H265eV511HalContext * ctx,H265eV511RegSet * regs)1990 static void vepu511_h265_set_atf_regs(H265eV511HalContext *ctx, H265eV511RegSet *regs)
1991 {
1992 H265eVepu511Sqi *reg = ®s->reg_sqi;
1993 RK_U32 str = ctx->cfg->tune.atf_str;
1994 rdo_b32_skip_par *p_rdo_b32_skip = NULL;
1995 rdo_b32_noskip_par *p_rdo_b32_noskip = NULL;
1996 rdo_skip_par *p_rdo_skip = NULL;
1997 rdo_noskip_par *p_rdo_noskip = NULL;
1998
1999 static RK_U16 b32_skip_thd2[4] = { 15, 15, 15, 200 };
2000 static RK_U16 b32_skip_thd3[4] = { 72, 72, 72, 1000 };
2001 static RK_U8 b32_skip_wgt0[4] = { 16, 20, 20, 16 };
2002 static RK_U8 b32_skip_wgt3[4] = { 16, 16, 16, 17 };
2003 static RK_U16 b16_skip_thd2[4] = { 15, 15, 15, 200 };
2004 static RK_U16 b16_skip_thd3[4] = { 25, 25, 25, 1000 };
2005 static RK_U8 b16_skip_wgt0[4] = { 16, 20, 20, 16 };
2006 static RK_U8 b16_skip_wgt3[4] = { 16, 16, 16, 17 };
2007 static RK_U16 b32_intra_thd0[4] = { 20, 20, 20, 24 };
2008 static RK_U16 b32_intra_thd1[4] = { 40, 40, 40, 48 };
2009 static RK_U16 b32_intra_thd2[4] = { 60, 72, 72, 96 };
2010 static RK_U8 b32_intra_wgt0[4] = { 16, 22, 27, 28 };
2011 static RK_U8 b32_intra_wgt1[4] = { 16, 20, 25, 26 };
2012 static RK_U8 b32_intra_wgt2[4] = { 16, 18, 20, 24 };
2013 static RK_U16 b16_intra_thd0[4] = { 20, 20, 20, 24 };
2014 static RK_U16 b16_intra_thd1[4] = { 40, 40, 40, 48 };
2015 static RK_U16 b16_intra_thd2[4] = { 60, 72, 72, 96 };
2016 static RK_U8 b16_intra_wgt0[4] = { 16, 22, 27, 28 };
2017 static RK_U8 b16_intra_wgt1[4] = { 16, 20, 25, 26 };
2018 static RK_U8 b16_intra_wgt2[4] = { 16, 18, 20, 24 };
2019
2020 regs->reg_frm.rdo_cfg.atf_e = !!str;
2021
2022 p_rdo_b32_skip = ®->rdo_b32_skip;
2023 p_rdo_b32_skip->atf_thd0.madp_thd0 = 5;
2024 p_rdo_b32_skip->atf_thd0.madp_thd1 = 10;
2025 p_rdo_b32_skip->atf_thd1.madp_thd2 = b32_skip_thd2[str];
2026 p_rdo_b32_skip->atf_thd1.madp_thd3 = b32_skip_thd3[str];
2027 p_rdo_b32_skip->atf_wgt0.wgt0 = b32_skip_wgt0[str];
2028 p_rdo_b32_skip->atf_wgt0.wgt1 = 16;
2029 p_rdo_b32_skip->atf_wgt0.wgt2 = 16;
2030 p_rdo_b32_skip->atf_wgt0.wgt3 = b32_skip_wgt3[str];
2031 p_rdo_b32_skip->atf_thd0.flckr_frame_qp_en = 1;
2032 p_rdo_b32_skip->atf_thd0.flckr_lgt_chng_en = 1;
2033
2034 p_rdo_b32_noskip = ®->rdo_b32_inter;
2035 p_rdo_b32_noskip->atf_thd0.madp_thd0 = 20;
2036 p_rdo_b32_noskip->atf_thd0.madp_thd1 = 40;
2037 p_rdo_b32_noskip->atf_thd1.madp_thd2 = 72;
2038 p_rdo_b32_noskip->atf_wgt.wgt0 = 16;
2039 p_rdo_b32_noskip->atf_wgt.wgt1 = 16;
2040 p_rdo_b32_noskip->atf_wgt.wgt2 = 16;
2041
2042 p_rdo_noskip = ®->rdo_b32_intra;
2043 p_rdo_noskip->ratf_thd0.madp_thd0 = b32_intra_thd0[str];
2044 p_rdo_noskip->ratf_thd0.madp_thd1 = b32_intra_thd1[str];
2045 p_rdo_noskip->ratf_thd1.madp_thd2 = b32_intra_thd2[str];
2046 p_rdo_noskip->atf_wgt.wgt0 = b32_intra_wgt0[str];
2047 p_rdo_noskip->atf_wgt.wgt1 = b32_intra_wgt1[str];
2048 p_rdo_noskip->atf_wgt.wgt2 = b32_intra_wgt2[str];
2049
2050 p_rdo_skip = ®->rdo_b16_skip;
2051 p_rdo_skip->atf_thd0.madp_thd0 = 1;
2052 p_rdo_skip->atf_thd0.madp_thd1 = 10;
2053 p_rdo_skip->atf_thd1.madp_thd2 = b16_skip_thd2[str];
2054 p_rdo_skip->atf_thd1.madp_thd3 = b16_skip_thd3[str];
2055 p_rdo_skip->atf_wgt0.wgt0 = b16_skip_wgt0[str];
2056 p_rdo_skip->atf_wgt0.wgt1 = 16;
2057 p_rdo_skip->atf_wgt0.wgt2 = 16;
2058 p_rdo_skip->atf_wgt0.wgt3 = b16_skip_wgt3[str];
2059
2060 p_rdo_noskip = ®->rdo_b16_inter;
2061 p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
2062 p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
2063 p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
2064 p_rdo_noskip->atf_wgt.wgt0 = 16;
2065 p_rdo_noskip->atf_wgt.wgt1 = 16;
2066 p_rdo_noskip->atf_wgt.wgt2 = 16;
2067 p_rdo_noskip->atf_wgt.wgt3 = 16;
2068
2069 p_rdo_noskip = ®->rdo_b16_intra;
2070 p_rdo_noskip->ratf_thd0.madp_thd0 = b16_intra_thd0[str];
2071 p_rdo_noskip->ratf_thd0.madp_thd1 = b16_intra_thd1[str];
2072 p_rdo_noskip->ratf_thd1.madp_thd2 = b16_intra_thd2[str];
2073 p_rdo_noskip->atf_wgt.wgt0 = b16_intra_wgt0[str];
2074 p_rdo_noskip->atf_wgt.wgt1 = b16_intra_wgt1[str];
2075 p_rdo_noskip->atf_wgt.wgt2 = b16_intra_wgt2[str];
2076 p_rdo_noskip->atf_wgt.wgt3 = 16;
2077 }
2078
vepu511_h265_set_aq(H265eV511HalContext * ctx,H265eV511RegSet * regs)2079 static void vepu511_h265_set_aq(H265eV511HalContext *ctx, H265eV511RegSet *regs)
2080 {
2081 MppEncHwCfg *hw = &ctx->cfg->hw;
2082 Vepu511RcRoi *rc_regs = ®s->reg_rc_roi;
2083 RK_S32 *aq_step, *aq_rnge;
2084 RK_U32 *aq_thd;
2085 RK_U32 i;
2086
2087 if (ctx->frame_type == INTRA_FRAME) {
2088 aq_thd = &hw->aq_thrd_i[0];
2089 aq_step = &hw->aq_step_i[0];
2090 aq_rnge = &hw->aq_rnge_arr[0];
2091 } else {
2092 aq_thd = &hw->aq_thrd_p[0];
2093 aq_step = &hw->aq_step_p[0];
2094 aq_rnge = &hw->aq_rnge_arr[5];
2095 }
2096
2097 rc_regs->aq_stp0.aq_stp_s0 = aq_step[0] & 0x1f;
2098 rc_regs->aq_stp0.aq_stp_0t1 = aq_step[1] & 0x1f;
2099 rc_regs->aq_stp0.aq_stp_1t2 = aq_step[2] & 0x1f;
2100 rc_regs->aq_stp0.aq_stp_2t3 = aq_step[3] & 0x1f;
2101 rc_regs->aq_stp0.aq_stp_3t4 = aq_step[4] & 0x1f;
2102 rc_regs->aq_stp0.aq_stp_4t5 = aq_step[5] & 0x1f;
2103 rc_regs->aq_stp1.aq_stp_5t6 = aq_step[6] & 0x1f;
2104 rc_regs->aq_stp1.aq_stp_6t7 = aq_step[7] & 0x1f;
2105 rc_regs->aq_stp1.aq_stp_7t8 = 0;
2106 rc_regs->aq_stp1.aq_stp_8t9 = aq_step[8] & 0x1f;
2107 rc_regs->aq_stp1.aq_stp_9t10 = aq_step[9] & 0x1f;
2108 rc_regs->aq_stp1.aq_stp_10t11 = aq_step[10] & 0x1f;
2109 rc_regs->aq_stp2.aq_stp_11t12 = aq_step[11] & 0x1f;
2110 rc_regs->aq_stp2.aq_stp_12t13 = aq_step[12] & 0x1f;
2111 rc_regs->aq_stp2.aq_stp_13t14 = aq_step[13] & 0x1f;
2112 rc_regs->aq_stp2.aq_stp_14t15 = aq_step[14] & 0x1f;
2113 rc_regs->aq_stp2.aq_stp_b15 = aq_step[15];
2114
2115 for (i = 0; i < 16; i++)
2116 rc_regs->aq_tthd[i] = aq_thd[i];
2117
2118 rc_regs->aq_clip.aq16_rnge = aq_rnge[0];
2119 rc_regs->aq_clip.aq32_rnge = aq_rnge[1];
2120 rc_regs->aq_clip.aq8_rnge = aq_rnge[2];
2121 rc_regs->aq_clip.aq16_dif0 = aq_rnge[3];
2122 rc_regs->aq_clip.aq16_dif1 = aq_rnge[4];
2123
2124 rc_regs->aq_clip.aq_rme_en = 1;
2125 rc_regs->aq_clip.aq_cme_en = 1;
2126 }
2127
vepu511_h265_global_cfg_set(H265eV511HalContext * ctx,H265eV511RegSet * regs)2128 static void vepu511_h265_global_cfg_set(H265eV511HalContext *ctx, H265eV511RegSet *regs)
2129 {
2130 H265eVepu511Frame *reg_frm = ®s->reg_frm;
2131 H265eVepu511Param *reg_param = ®s->reg_param;
2132 RK_S32 lambda_idx_p = ctx->cfg->tune.lambda_idx_i;
2133
2134 reg_frm->sao_cfg.sao_lambda_multi = ctx->cfg->h265.sao_cfg.sao_bit_ratio;
2135
2136 if (ctx->frame_type == INTRA_FRAME) {
2137 memcpy(®_param->pprd_lamb_satd_0_51[0], lambda_tbl_pre_intra, sizeof(lambda_tbl_pre_intra));
2138 } else {
2139 memcpy(®_param->pprd_lamb_satd_0_51[0], lambda_tbl_pre_inter, sizeof(lambda_tbl_pre_inter));
2140 }
2141
2142 {
2143 RK_U32 *lambda_tbl;
2144
2145 if (ctx->frame_type == INTRA_FRAME) {
2146 lambda_tbl = &rdo_lambda_table_I[lambda_idx_p];
2147 } else {
2148 lambda_idx_p = ctx->cfg->tune.lambda_idx_p;
2149 lambda_tbl = &rdo_lambda_table_P[lambda_idx_p];
2150 }
2151
2152 memcpy(®_param->rdo_wgta_qp_grpa_0_51[0], lambda_tbl, H265E_LAMBDA_TAB_SIZE);
2153 }
2154
2155 /* 0x1064 */
2156 regs->reg_rc_roi.madi_st_thd.madi_th0 = 5;
2157 regs->reg_rc_roi.madi_st_thd.madi_th1 = 12;
2158 regs->reg_rc_roi.madi_st_thd.madi_th2 = 20;
2159 /* 0x1068 */
2160 regs->reg_rc_roi.madp_st_thd0.madp_th0 = 4 << 4;
2161 regs->reg_rc_roi.madp_st_thd0.madp_th1 = 9 << 4;
2162 /* 0x106C */
2163 regs->reg_rc_roi.madp_st_thd1.madp_th2 = 15 << 4;
2164 regs->reg_param.prmd_intra_lamb_ofst.lambda_luma_offset = 11;
2165 regs->reg_param.prmd_intra_lamb_ofst.lambda_chroma_offset = 11;
2166
2167 }
2168
hal_h265e_vepu511_gen_regs(void * hal,HalEncTask * task)2169 MPP_RET hal_h265e_vepu511_gen_regs(void *hal, HalEncTask *task)
2170 {
2171 H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
2172 Vepu511H265eFrmCfg *frm_cfg = ctx->frm;
2173 H265eV511RegSet *regs = frm_cfg->regs_set;
2174 MPP_RET ret = MPP_OK;
2175
2176 HalEncTask *enc_task = task;
2177 H265eSyntax_new *syn = ctx->syn;
2178 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
2179 H265eVepu511Frame *reg_frm = ®s->reg_frm;
2180 EncFrmStatus *frm = &task->rc_task->frm;
2181
2182 hal_h265e_enter();
2183
2184 hal_h265e_dbg_simple("frame %d | type %d | start gen regs11",
2185 ctx->frame_num, ctx->frame_type);
2186
2187 memset(regs, 0, sizeof(H265eV511RegSet));
2188
2189 vepu511_h265_set_normal(ctx, regs);
2190 vepu511_h265_set_prep(ctx, task, regs);
2191 vepu511_h265_set_me_regs(ctx, syn , regs);
2192 vepu511_h265_set_split(regs, ctx->cfg);
2193 vepu511_h265_set_hw_address(ctx, reg_frm, task);
2194 vepu511_h265_set_pp_regs(regs, fmt, &ctx->cfg->prep, task);
2195 vepu511_h265_set_vsp_filtering(ctx, regs);
2196 vepu511_h265_set_rc_regs(ctx, regs, task);
2197 vepu511_h265_set_rdo_regs(regs);
2198 vepu511_h265_set_quant_regs(ctx, regs);
2199 vepu511_h265_set_sao_regs(regs);
2200 vepu511_h265_set_slice_regs(syn, reg_frm);
2201 vepu511_h265_set_ref_regs(syn, reg_frm);
2202
2203 ret = vepu511_h265_set_patch_info(syn, (VepuFmt)fmt->format, ctx->reg_cfg, enc_task);
2204 if (ret)
2205 return ret;
2206
2207 setup_vepu511_ext_line_buf(ctx, regs);
2208 vepu511_h265_set_atf_regs(ctx, regs);
2209 vepu511_h265_set_anti_stripe_regs(ctx, regs);
2210 vepu511_h265_set_atr_regs(regs);
2211 vepu511_h265_set_smear_regs(ctx, regs);
2212 vepu511_h265_set_scaling_list(regs);
2213 vepu511_h265_set_aq(ctx, regs);
2214
2215 if (ctx->osd_cfg.osd_data3)
2216 vepu511_set_osd(&ctx->osd_cfg, ®s->reg_osd.osd_comb_cfg);
2217
2218 if (ctx->roi_data)
2219 vepu511_set_roi(®s->reg_rc_roi.roi_cfg, ctx->roi_data,
2220 ctx->cfg->prep.width, ctx->cfg->prep.height);
2221
2222 /*paramet cfg*/
2223 vepu511_h265_global_cfg_set(ctx, regs);
2224
2225 /* two pass register patch */
2226 if (frm->save_pass1)
2227 vepu511_h265e_save_pass1_patch(regs, ctx, syn->pp.tiles_enabled_flag);
2228
2229 if (frm->use_pass1)
2230 vepu511_h265e_use_pass1_patch(regs, ctx);
2231
2232 ctx->frame_num++;
2233
2234 hal_h265e_leave();
2235 return MPP_OK;
2236 }
2237
hal_h265e_vepu511_start(void * hal,HalEncTask * enc_task)2238 MPP_RET hal_h265e_vepu511_start(void *hal, HalEncTask *enc_task)
2239 {
2240 MPP_RET ret = MPP_OK;
2241 H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
2242 Vepu511H265eFrmCfg *frm = ctx->frm;
2243 RK_U32 *regs = (RK_U32*)frm->regs_set;
2244 H265eV511RegSet *hw_regs = frm->regs_set;
2245 H265eV511StatusElem *reg_out = (H265eV511StatusElem *)frm->regs_ret;
2246 MppDevRegWrCfg cfg;
2247 MppDevRegRdCfg cfg1;
2248 RK_U32 i = 0;
2249
2250 hal_h265e_enter();
2251 if (enc_task->flags.err) {
2252 hal_h265e_err("enc_task->flags.err %08x, return e arly",
2253 enc_task->flags.err);
2254 return MPP_NOK;
2255 }
2256
2257 cfg.reg = (RK_U32*)&hw_regs->reg_ctl;
2258 cfg.size = sizeof(Vepu511ControlCfg);
2259 cfg.offset = VEPU511_CTL_OFFSET;
2260
2261 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
2262 if (ret) {
2263 mpp_err_f("set register write failed %d\n", ret);
2264 return ret;
2265 }
2266
2267 if (hal_h265e_debug & HAL_H265E_DBG_CTL_REGS) {
2268 regs = (RK_U32*)&hw_regs->reg_ctl;
2269 for (i = 0; i < sizeof(Vepu511ControlCfg) / 4; i++) {
2270 hal_h265e_dbg_ctl("ctl reg[%04x]: 0%08x\n", i * 4, regs[i]);
2271 }
2272 }
2273
2274 cfg.reg = &hw_regs->reg_frm;
2275 cfg.size = sizeof(H265eVepu511Frame);
2276 cfg.offset = VEPU511_FRAME_OFFSET;
2277
2278 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
2279 if (ret) {
2280 mpp_err_f("set register write failed %d\n", ret);
2281 return ret;
2282 }
2283
2284 if (hal_h265e_debug & HAL_H265E_DBG_REGS) {
2285 regs = (RK_U32*)(&hw_regs->reg_frm);
2286 for (i = 0; i < 32; i++) {
2287 hal_h265e_dbg_regs("hw add cfg reg[%04x]: 0x%08x\n", i * 4, regs[i]);
2288 }
2289 regs += 32;
2290 for (i = 0; i < (sizeof(H265eVepu511Frame) - 128) / 4; i++) {
2291 hal_h265e_dbg_regs("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
2292 }
2293 }
2294 cfg.reg = &hw_regs->reg_rc_roi;
2295 cfg.size = sizeof(Vepu511RcRoi);
2296 cfg.offset = VEPU511_RC_ROI_OFFSET;
2297
2298 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
2299 if (ret) {
2300 mpp_err_f("set register write failed %d\n", ret);
2301 return ret;
2302 }
2303
2304 if (hal_h265e_debug & HAL_H265E_DBG_RCKUT_REGS) {
2305 regs = (RK_U32*)&hw_regs->reg_rc_roi;
2306 for (i = 0; i < sizeof(Vepu511RcRoi) / 4; i++) {
2307 hal_h265e_dbg_rckut("set rc roi reg[%04x]: 0%08x\n", i * 4, regs[i]);
2308 }
2309 }
2310
2311 cfg.reg = &hw_regs->reg_param;
2312 cfg.size = sizeof(H265eVepu511Param);
2313 cfg.offset = VEPU511_PARAM_OFFSET;
2314
2315 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
2316 if (ret) {
2317 mpp_err_f("set register write failed %d\n", ret);
2318 return ret;
2319 }
2320
2321 if (hal_h265e_debug & HAL_H265E_DBG_WGT_REGS) {
2322 regs = (RK_U32*)&hw_regs->reg_param;
2323 for (i = 0; i < sizeof(H265eVepu511Param) / 4; i++) {
2324 hal_h265e_dbg_wgt("set param reg[%04x]: 0%08x\n", i * 4, regs[i]);
2325 }
2326 }
2327
2328 cfg.reg = &hw_regs->reg_sqi;
2329 cfg.size = sizeof(H265eVepu511Sqi);
2330 cfg.offset = VEPU511_SQI_OFFSET;
2331
2332 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
2333 if (ret) {
2334 mpp_err_f("set register write failed %d\n", ret);
2335 return ret;
2336 }
2337
2338 if (hal_h265e_debug & HAL_H265E_DBG_WGT_REGS) {
2339 regs = (RK_U32*)&hw_regs->reg_sqi;
2340 for (i = 0; i < sizeof(H265eVepu511Sqi) / 4; i++) {
2341 hal_h265e_dbg_wgt("set sqi reg[%04x]: 0%08x\n", i * 4, regs[i]);
2342 }
2343 }
2344
2345 cfg.reg = &hw_regs->reg_scl;
2346 cfg.size = sizeof(hw_regs->reg_scl);
2347 cfg.offset = VEPU511_SCL_OFFSET ;
2348
2349 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
2350 if (ret) {
2351 mpp_err_f("set register write failed %d\n", ret);
2352 return ret;
2353 }
2354
2355 if (hal_h265e_debug & HAL_H265E_DBG_WGT_REGS) {
2356 regs = (RK_U32*)&hw_regs->reg_scl;
2357 for (i = 0; i < sizeof(H265eVepu511SclCfg) / 4; i++) {
2358 hal_h265e_dbg_wgt("set scl reg[%04x]: 0%08x\n", i * 4, regs[i]);
2359 }
2360 }
2361
2362 cfg.reg = &hw_regs->reg_osd;
2363 cfg.size = sizeof(hw_regs->reg_osd);
2364 cfg.offset = VEPU511_OSD_OFFSET ;
2365
2366 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
2367 if (ret) {
2368 mpp_err_f("set register write failed %d\n", ret);
2369 return ret;
2370 }
2371
2372 if (hal_h265e_debug & HAL_H265E_DBG_WGT_REGS) {
2373 regs = (RK_U32*)&hw_regs->reg_osd;
2374 for (i = 0; i < sizeof(Vepu511OsdRegs) / 4; i++) {
2375 hal_h265e_dbg_wgt("set osd reg[%04x]: 0%08x\n", i * 4, regs[i]);
2376 }
2377 }
2378
2379 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFS, ctx->reg_cfg);
2380 if (ret) {
2381 mpp_err_f("set register offsets failed %d\n", ret);
2382 return ret;
2383 }
2384
2385 cfg1.reg = ®_out->hw_status;
2386 cfg1.size = sizeof(RK_U32);
2387 cfg1.offset = VEPU511_REG_BASE_HW_STATUS;
2388
2389 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
2390 if (ret) {
2391 mpp_err_f("set register read failed %d\n", ret);
2392 return ret;
2393 }
2394
2395 cfg1.reg = ®_out->st;
2396 cfg1.size = sizeof(H265eV511StatusElem) - 4;
2397 cfg1.offset = VEPU511_STATUS_OFFSET;
2398
2399 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
2400 if (ret) {
2401 mpp_err_f("set register read failed %d\n", ret);
2402 return ret;
2403 }
2404
2405 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
2406 if (ret) {
2407 mpp_err_f("send cmd failed %d\n", ret);
2408 }
2409 hal_h265e_leave();
2410 return ret;
2411 }
2412
vepu511_h265_set_feedback(H265eV511HalContext * ctx,HalEncTask * enc_task)2413 static MPP_RET vepu511_h265_set_feedback(H265eV511HalContext *ctx, HalEncTask *enc_task)
2414 {
2415 EncRcTaskInfo *hal_rc_ret = (EncRcTaskInfo *)&enc_task->rc_task->info;
2416 Vepu511H265eFrmCfg *frm = ctx->frms[enc_task->flags.reg_idx];
2417 Vepu511H265Fbk *fb = &frm->feedback;
2418 MppEncCfgSet *cfg = ctx->cfg;
2419 RK_S32 mb8_num = MPP_ALIGN(cfg->prep.width, 8) * MPP_ALIGN(cfg->prep.height, 8) / 64;
2420 RK_S32 mb4_num = (mb8_num << 2);
2421 H265eV511StatusElem *elem = (H265eV511StatusElem *)frm->regs_ret;
2422 RK_U32 hw_status = elem->hw_status;
2423
2424 hal_h265e_enter();
2425
2426 fb->qp_sum += elem->st.qp_sum;
2427 fb->out_strm_size += elem->st.bs_lgth_l32;
2428 fb->sse_sum += (RK_S64)(elem->st.sse_h32 << 16) +
2429 (elem->st.st_sse_bsl.sse_l16 & 0xffff);
2430
2431 fb->hw_status = hw_status;
2432 hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status);
2433 if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)
2434 hal_h265e_err("RKV_ENC_INT_LINKTABLE_FINISH");
2435
2436 if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH)
2437 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_FRAME_FINISH");
2438
2439 if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)
2440 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_SLICE_FINISH");
2441
2442 if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)
2443 hal_h265e_err("RKV_ENC_INT_SAFE_CLEAR_FINISH");
2444
2445 if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW)
2446 hal_h265e_err("RKV_ENC_INT_BIT_STREAM_OVERFLOW");
2447
2448 if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL)
2449 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_FULL");
2450
2451 if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR)
2452 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_ERROR");
2453
2454 if (hw_status & RKV_ENC_INT_BUS_READ_ERROR)
2455 hal_h265e_err("RKV_ENC_INT_BUS_READ_ERROR");
2456
2457 if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR)
2458 hal_h265e_err("RKV_ENC_INT_TIMEOUT_ERROR");
2459
2460 fb->st_mb_num += elem->st.st_bnum_b16.num_b16;
2461
2462 fb->st_lvl64_inter_num += elem->st.st_pnum_p64.pnum_p64;
2463 fb->st_lvl32_inter_num += elem->st.st_pnum_p32.pnum_p32;
2464 fb->st_lvl32_intra_num += elem->st.st_pnum_i32.pnum_i32;
2465 fb->st_lvl16_inter_num += elem->st.st_pnum_p16.pnum_p16;
2466 fb->st_lvl16_intra_num += elem->st.st_pnum_i16.pnum_i16;
2467 fb->st_lvl8_inter_num += elem->st.st_pnum_p8.pnum_p8;
2468 fb->st_lvl8_intra_num += elem->st.st_pnum_i8.pnum_i8;
2469 fb->st_lvl4_intra_num += elem->st.st_pnum_i4.pnum_i4;
2470
2471 ctx->feedback.acc_cover16_num = elem->st.st_skin_sum1.num1_point_skin;
2472 ctx->feedback.acc_bndry16_num = elem->st.st_skin_sum2.num2_point_skin;
2473 ctx->feedback.acc_zero_mv = elem->st.acc_zero_mv;
2474 ctx->feedback.st_ctu_num = elem->st.st_bnum_b16.num_b16;
2475 memcpy(&fb->st_cu_num_qp[0], &elem->st.st_b8_qp, 52 * sizeof(RK_U32));
2476
2477 if (mb4_num > 0)
2478 hal_rc_ret->iblk4_prop = ((((fb->st_lvl4_intra_num + fb->st_lvl8_intra_num) << 2) +
2479 (fb->st_lvl16_intra_num << 4) +
2480 (fb->st_lvl32_intra_num << 6)) << 8) / mb4_num;
2481
2482 if (mb8_num > 0) {
2483 hal_rc_ret->quality_real = fb->qp_sum / mb8_num;
2484 }
2485
2486 hal_h265e_leave();
2487 return MPP_OK;
2488 }
2489
hal_h265e_vepu511_status_check(H265eV511RegSet * regs)2490 static MPP_RET hal_h265e_vepu511_status_check(H265eV511RegSet *regs)
2491 {
2492 MPP_RET ret = MPP_OK;
2493
2494 if (regs->reg_ctl.int_sta.lkt_node_done_sta)
2495 hal_h265e_dbg_detail("lkt_done finish");
2496
2497 if (regs->reg_ctl.int_sta.enc_done_sta)
2498 hal_h265e_dbg_detail("enc_done finish");
2499
2500 if (regs->reg_ctl.int_sta.vslc_done_sta)
2501 hal_h265e_dbg_detail("enc_slice finsh");
2502
2503 if (regs->reg_ctl.int_sta.sclr_done_sta)
2504 hal_h265e_dbg_detail("safe clear finsh");
2505
2506 if (regs->reg_ctl.int_sta.vbsf_oflw_sta) {
2507 mpp_err_f("bit stream overflow");
2508 ret = MPP_NOK;
2509 }
2510
2511 if (regs->reg_ctl.int_sta.vbuf_lens_sta) {
2512 mpp_err_f("bus write full");
2513 ret = MPP_NOK;
2514 }
2515
2516 if (regs->reg_ctl.int_sta.enc_err_sta) {
2517 mpp_err_f("bus error");
2518 ret = MPP_NOK;
2519 }
2520
2521 if (regs->reg_ctl.int_sta.wdg_sta) {
2522 mpp_err_f("wdg timeout");
2523 ret = MPP_NOK;
2524 }
2525
2526 return ret;
2527 }
2528
vepu511_h265e_update_tune_stat(H265eV511HalContext * ctx,HalEncTask * task)2529 static void vepu511_h265e_update_tune_stat(H265eV511HalContext *ctx, HalEncTask *task)
2530 {
2531 RK_S32 task_idx = task->flags.reg_idx;
2532 Vepu511H265eFrmCfg *frm = ctx->frms[task_idx];
2533 Vepu511H265Fbk *fb = &frm->feedback;
2534 H265eV511RegSet *regs = frm->regs_set;
2535 Vepu511RcRoi *s = ®s->reg_rc_roi;
2536 MppEncCfgSet *cfg = ctx->cfg;
2537 Vepu511Status *st = &frm->regs_ret->st;
2538 EncRcTaskInfo *info = (EncRcTaskInfo *)&task->rc_task->info;
2539 RK_U32 b16_num = MPP_ALIGN(cfg->prep.width, 16) * MPP_ALIGN(cfg->prep.height, 16) / 256;
2540 RK_U32 madi_cnt = 0, madp_cnt = 0;
2541
2542 RK_U32 madi_th_cnt0 = st->st_madi_lt_num0.madi_th_lt_cnt0 +
2543 st->st_madi_rt_num0.madi_th_rt_cnt0 +
2544 st->st_madi_lb_num0.madi_th_lb_cnt0 +
2545 st->st_madi_rb_num0.madi_th_rb_cnt0;
2546 RK_U32 madi_th_cnt1 = st->st_madi_lt_num0.madi_th_lt_cnt1 +
2547 st->st_madi_rt_num0.madi_th_rt_cnt1 +
2548 st->st_madi_lb_num0.madi_th_lb_cnt1 +
2549 st->st_madi_rb_num0.madi_th_rb_cnt1;
2550 RK_U32 madi_th_cnt2 = st->st_madi_lt_num1.madi_th_lt_cnt2 +
2551 st->st_madi_rt_num1.madi_th_rt_cnt2 +
2552 st->st_madi_lb_num1.madi_th_lb_cnt2 +
2553 st->st_madi_rb_num1.madi_th_rb_cnt2;
2554 RK_U32 madi_th_cnt3 = st->st_madi_lt_num1.madi_th_lt_cnt3 +
2555 st->st_madi_rt_num1.madi_th_rt_cnt3 +
2556 st->st_madi_lb_num1.madi_th_lb_cnt3 +
2557 st->st_madi_rb_num1.madi_th_rb_cnt3;
2558 RK_U32 madp_th_cnt0 = st->st_madp_lt_num0.madp_th_lt_cnt0 +
2559 st->st_madp_rt_num0.madp_th_rt_cnt0 +
2560 st->st_madp_lb_num0.madp_th_lb_cnt0 +
2561 st->st_madp_rb_num0.madp_th_rb_cnt0;
2562 RK_U32 madp_th_cnt1 = st->st_madp_lt_num0.madp_th_lt_cnt1 +
2563 st->st_madp_rt_num0.madp_th_rt_cnt1 +
2564 st->st_madp_lb_num0.madp_th_lb_cnt1 +
2565 st->st_madp_rb_num0.madp_th_rb_cnt1;
2566 RK_U32 madp_th_cnt2 = st->st_madp_lt_num1.madp_th_lt_cnt2 +
2567 st->st_madp_rt_num1.madp_th_rt_cnt2 +
2568 st->st_madp_lb_num1.madp_th_lb_cnt2 +
2569 st->st_madp_rb_num1.madp_th_rb_cnt2;
2570 RK_U32 madp_th_cnt3 = st->st_madp_lt_num1.madp_th_lt_cnt3 +
2571 st->st_madp_rt_num1.madp_th_rt_cnt3 +
2572 st->st_madp_lb_num1.madp_th_lb_cnt3 +
2573 st->st_madp_rb_num1.madp_th_rb_cnt3;
2574
2575 madi_cnt = (6 * madi_th_cnt3 + 5 * madi_th_cnt2 + 4 * madi_th_cnt1) >> 2;
2576 info->complex_level = (madi_cnt * 100 > 30 * b16_num) ? 2 :
2577 (madi_cnt * 100 > 13 * b16_num) ? 1 : 0;
2578
2579 {
2580 RK_U32 md_cnt = 0, motion_level = 0;
2581
2582 if (ctx->smart_en)
2583 md_cnt = (12 * madp_th_cnt3 + 11 * madp_th_cnt2 + 8 * madp_th_cnt1) >> 2;
2584 else
2585 md_cnt = (24 * madp_th_cnt3 + 22 * madp_th_cnt2 + 17 * madp_th_cnt1) >> 2;
2586
2587 if (md_cnt * 100 > 15 * b16_num)
2588 motion_level = 200;
2589 else if (md_cnt * 100 > 5 * b16_num)
2590 motion_level = 100;
2591 else if (md_cnt * 100 > (b16_num >> 2))
2592 motion_level = 1;
2593 else
2594 motion_level = 0;
2595 info->motion_level = motion_level;
2596 }
2597 hal_h265e_dbg_st("frame %d complex_level %d motion_level %d\n",
2598 ctx->frame_num - 1, info->complex_level, info->motion_level);
2599
2600 fb->st_madi = madi_th_cnt0 * s->madi_st_thd.madi_th0 +
2601 madi_th_cnt1 * (s->madi_st_thd.madi_th0 + s->madi_st_thd.madi_th1) / 2 +
2602 madi_th_cnt2 * (s->madi_st_thd.madi_th1 + s->madi_st_thd.madi_th2) / 2 +
2603 madi_th_cnt3 * s->madi_st_thd.madi_th2;
2604
2605 madi_cnt = madi_th_cnt0 + madi_th_cnt1 + madi_th_cnt2 + madi_th_cnt3;
2606 if (madi_cnt)
2607 fb->st_madi = fb->st_madi / madi_cnt;
2608
2609 fb->st_madp = madp_th_cnt0 * s->madp_st_thd0.madp_th0 +
2610 madp_th_cnt1 * (s->madp_st_thd0.madp_th0 + s->madp_st_thd0.madp_th1) / 2 +
2611 madp_th_cnt2 * (s->madp_st_thd0.madp_th1 + s->madp_st_thd1.madp_th2) / 2 +
2612 madp_th_cnt3 * s->madp_st_thd1.madp_th2;
2613
2614 madp_cnt = madp_th_cnt0 + madp_th_cnt1 + madp_th_cnt2 + madp_th_cnt3;
2615 if (madp_cnt)
2616 fb->st_madp = fb->st_madp / madp_cnt;
2617
2618 fb->st_mb_num += st->st_bnum_b16.num_b16;
2619 fb->frame_type = task->rc_task->frm.is_intra ? INTRA_FRAME : INTER_P_FRAME;
2620 info->bit_real = fb->out_strm_size * 8;
2621 info->madi = fb->st_madi;
2622 info->madp = fb->st_madp;
2623
2624 hal_h265e_dbg_st("frame %d bit_real %d quality_real %d madi %d madp %d\n",
2625 ctx->frame_num - 1, info->bit_real, info->quality_real, info->madi, info->madp);
2626 }
2627
2628 //#define DUMP_DATA
hal_h265e_vepu511_wait(void * hal,HalEncTask * task)2629 MPP_RET hal_h265e_vepu511_wait(void *hal, HalEncTask *task)
2630 {
2631 MPP_RET ret = MPP_OK;
2632 H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
2633 HalEncTask *enc_task = task;
2634 MppPacket pkt = enc_task->packet;
2635 RK_U32 split_out = ctx->cfg->split.split_out;
2636 RK_S32 task_idx = task->flags.reg_idx;
2637 Vepu511H265eFrmCfg *frm = ctx->frms[task_idx];
2638 H265eV511RegSet *regs = frm->regs_set;
2639 RK_U32 offset = mpp_packet_get_length(pkt);
2640 RK_U32 seg_offset = offset;
2641 H265eVepu511Frame *reg_frm = ®s->reg_frm;
2642 RK_U32 type = reg_frm->synt_nal.nal_unit_type;
2643 H265eV511StatusElem *elem = (H265eV511StatusElem *)frm->regs_ret;
2644
2645 hal_h265e_enter();
2646
2647 if (enc_task->flags.err) {
2648 hal_h265e_err("enc_task->flags.err %08x, return early",
2649 enc_task->flags.err);
2650 return MPP_NOK;
2651 }
2652
2653 /* if pass1 mode, it will disable split mode and the split out need to be disable */
2654 if (enc_task->rc_task->frm.save_pass1)
2655 split_out = 0;
2656
2657 if (split_out) {
2658 EncOutParam param;
2659 RK_U32 slice_len = 0;
2660 RK_U32 slice_last = 0;
2661 MppDevPollCfg *poll_cfg = (MppDevPollCfg *)((char *)ctx->poll_cfgs);
2662 param.task = task;
2663 param.base = mpp_packet_get_data(task->packet);
2664
2665 do {
2666 RK_S32 i = 0;
2667 poll_cfg->poll_type = 0;
2668 poll_cfg->poll_ret = 0;
2669 poll_cfg->count_max = ctx->poll_slice_max;
2670 poll_cfg->count_ret = 0;
2671
2672 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, poll_cfg);
2673 for (i = 0; i < poll_cfg->count_ret; i++) {
2674 slice_last = poll_cfg->slice_info[i].last;
2675 slice_len = poll_cfg->slice_info[i].length;
2676 param.length = slice_len;
2677
2678 mpp_packet_add_segment_info(pkt, type, seg_offset, slice_len);
2679 seg_offset += slice_len;
2680
2681 if (split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) {
2682 param.length = slice_len;
2683 if (slice_last)
2684 ctx->output_cb->cmd = ENC_OUTPUT_FINISH;
2685 else
2686 ctx->output_cb->cmd = ENC_OUTPUT_SLICE;
2687
2688 mpp_callback(ctx->output_cb, ¶m);
2689 }
2690 }
2691 } while (!slice_last);
2692
2693 ret = hal_h265e_vepu511_status_check(regs);
2694 if (!ret)
2695 task->hw_length += elem->st.bs_lgth_l32;
2696
2697 } else {
2698 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
2699 if (ret) {
2700 mpp_err_f("poll cmd failed %d\n", ret);
2701 ret = MPP_ERR_VPUHW;
2702 } else {
2703 ret = hal_h265e_vepu511_status_check(regs);
2704 if (!ret)
2705 task->hw_length += elem->st.bs_lgth_l32;
2706 }
2707 mpp_packet_add_segment_info(pkt, type, offset, elem->st.bs_lgth_l32);
2708 }
2709
2710 #ifdef DUMP_DATA
2711 vepu511_h265e_dump(ctx, task);
2712 #endif
2713
2714 if (ret)
2715 mpp_err_f("poll cmd failed %d status %d \n", ret, elem->hw_status);
2716
2717 hal_h265e_leave();
2718 return ret;
2719 }
2720
hal_h265e_vepu511_get_task(void * hal,HalEncTask * task)2721 MPP_RET hal_h265e_vepu511_get_task(void *hal, HalEncTask *task)
2722 {
2723 H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
2724 Vepu511H265eFrmCfg *frm_cfg = NULL;
2725 MppFrame frame = task->frame;
2726 EncFrmStatus *frm_status = &task->rc_task->frm;
2727 RK_S32 task_idx = ctx->task_idx;
2728
2729 hal_h265e_enter();
2730
2731 ctx->syn = (H265eSyntax_new *)task->syntax.data;
2732 ctx->dpb = (H265eDpb*)ctx->syn->dpb;
2733 ctx->smart_en = (ctx->cfg->rc.rc_mode == MPP_ENC_RC_MODE_SMTRC);
2734 ctx->qpmap_en = ctx->cfg->tune.deblur_en;
2735
2736 if (vepu511_h265_setup_hal_bufs(ctx)) {
2737 hal_h265e_err("vepu541_h265_allocate_buffers failed, free buffers and return\n");
2738 task->flags.err |= HAL_ENC_TASK_ERR_ALLOC;
2739 return MPP_ERR_MALLOC;
2740 }
2741
2742 ctx->last_frame_type = ctx->frame_type;
2743 frm_cfg = ctx->frms[task_idx];
2744 ctx->frm = frm_cfg;
2745
2746 if (frm_status->is_intra) {
2747 ctx->frame_type = INTRA_FRAME;
2748 } else {
2749 ctx->frame_type = INTER_P_FRAME;
2750 }
2751
2752 if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
2753 MppMeta meta = mpp_frame_get_meta(frame);
2754
2755 mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
2756 mpp_meta_get_ptr_d(meta, KEY_OSD_DATA3, (void **)&ctx->osd_cfg.osd_data3, NULL);
2757 }
2758
2759 task->flags.reg_idx = ctx->task_idx;
2760 ctx->ext_line_buf = ctx->ext_line_bufs[ctx->task_idx];
2761 frm_cfg->frame_count = ++ctx->frame_count;
2762
2763 ctx->task_idx++;
2764 if (ctx->task_idx >= ctx->task_cnt)
2765 ctx->task_idx = 0;
2766
2767 frm_cfg->hal_curr_idx = ctx->syn->sp.recon_pic.slot_idx;
2768 frm_cfg->hal_refr_idx = ctx->syn->sp.ref_pic.slot_idx;
2769
2770 h265e_dpb_hal_start(ctx->dpb, frm_cfg->hal_curr_idx);
2771 h265e_dpb_hal_start(ctx->dpb, frm_cfg->hal_refr_idx);
2772
2773 memset(&frm_cfg->feedback, 0, sizeof(Vepu511H265Fbk));
2774
2775 hal_h265e_leave();
2776 return MPP_OK;
2777 }
2778
hal_h265e_vepu511_ret_task(void * hal,HalEncTask * task)2779 MPP_RET hal_h265e_vepu511_ret_task(void *hal, HalEncTask *task)
2780 {
2781 H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
2782 HalEncTask *enc_task = task;
2783 RK_S32 task_idx = task->flags.reg_idx;
2784 Vepu511H265eFrmCfg *frm = ctx->frms[task_idx];
2785 Vepu511H265Fbk *fb = &frm->feedback;
2786 EncRcTaskInfo *rc_info = &task->rc_task->info;
2787 RK_U32 offset = mpp_packet_get_length(enc_task->packet);
2788
2789 hal_h265e_enter();
2790
2791 vepu511_h265_set_feedback(ctx, enc_task);
2792 mpp_buffer_sync_partial_begin(enc_task->output, offset, fb->out_strm_size);
2793 hal_h265e_amend_temporal_id(task, fb->out_strm_size);
2794
2795 rc_info->sse = fb->sse_sum;
2796 rc_info->lvl64_inter_num = fb->st_lvl64_inter_num;
2797 rc_info->lvl32_inter_num = fb->st_lvl32_inter_num;
2798 rc_info->lvl16_inter_num = fb->st_lvl16_inter_num;
2799 rc_info->lvl8_inter_num = fb->st_lvl8_inter_num;
2800 rc_info->lvl32_intra_num = fb->st_lvl32_intra_num;
2801 rc_info->lvl16_intra_num = fb->st_lvl16_intra_num;
2802 rc_info->lvl8_intra_num = fb->st_lvl8_intra_num;
2803 rc_info->lvl4_intra_num = fb->st_lvl4_intra_num;
2804
2805 enc_task->hw_length = fb->out_strm_size;
2806 enc_task->length += fb->out_strm_size;
2807
2808 h265e_dpb_hal_end(ctx->dpb, frm->hal_curr_idx);
2809 h265e_dpb_hal_end(ctx->dpb, frm->hal_refr_idx);
2810
2811 vepu511_h265e_update_tune_stat(ctx, enc_task);
2812
2813 hal_h265e_dbg_detail("output stream size %d\n", fb->out_strm_size);
2814 hal_h265e_leave();
2815 return MPP_OK;
2816 }
2817
2818 const MppEncHalApi hal_h265e_vepu511 = {
2819 .name = "hal_h265e_v511",
2820 .coding = MPP_VIDEO_CodingHEVC,
2821 .ctx_size = sizeof(H265eV511HalContext),
2822 .flag = 0,
2823 .init = hal_h265e_vepu511_init,
2824 .deinit = hal_h265e_vepu511_deinit,
2825 .prepare = hal_h265e_vepu511_prepare,
2826 .get_task = hal_h265e_vepu511_get_task,
2827 .gen_regs = hal_h265e_vepu511_gen_regs,
2828 .start = hal_h265e_vepu511_start,
2829 .wait = hal_h265e_vepu511_wait,
2830 .part_start = NULL,
2831 .part_wait = NULL,
2832 .ret_task = hal_h265e_vepu511_ret_task,
2833 };
2834