1 /* SPDX-License-Identifier: Apache-2.0 */
2 /*
3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4 */
5
6 #define MODULE_TAG "hal_h264e_vepu510"
7
8 #include <string.h>
9
10 #include "mpp_env.h"
11 #include "mpp_mem.h"
12 #include "mpp_common.h"
13 #include "mpp_frame_impl.h"
14 #include "mpp_packet_impl.h"
15 #include "mpp_enc_cb_param.h"
16
17 #include "rkv_enc_def.h"
18 #include "hal_h264e_debug.h"
19 #include "hal_bufs.h"
20 #include "hal_h264e_vepu510_reg.h"
21 #include "hal_h264e_vepu510.h"
22 #include "hal_h264e_stream_amend.h"
23 #include "h264e_dpb.h"
24
25 #include "vepu5xx.h"
26 #include "vepu5xx_common.h"
27 #include "vepu510_common.h"
28
29 #define DUMP_REG 0
30 #define MAX_TASK_CNT 2
31 #define VEPU540C_MAX_ROI_NUM 8
32
33 /* Custom Quant Matrices: Joint Video Team */
34 static RK_U8 vepu510_h264_cqm_jvt8i[64] = {
35 6, 10, 13, 16, 18, 23, 25, 27,
36 10, 11, 16, 18, 23, 25, 27, 29,
37 13, 16, 18, 23, 25, 27, 29, 31,
38 16, 18, 23, 25, 27, 29, 31, 33,
39 18, 23, 25, 27, 29, 31, 33, 36,
40 23, 25, 27, 29, 31, 33, 36, 38,
41 25, 27, 29, 31, 33, 36, 38, 40,
42 27, 29, 31, 33, 36, 38, 40, 42
43 };
44
45 static RK_U8 vepu510_h264_cqm_jvt8p[64] = {
46 9, 13, 15, 17, 19, 21, 22, 24,
47 13, 13, 17, 19, 21, 22, 24, 25,
48 15, 17, 19, 21, 22, 24, 25, 27,
49 17, 19, 21, 22, 24, 25, 27, 28,
50 19, 21, 22, 24, 25, 27, 28, 30,
51 21, 22, 24, 25, 27, 28, 30, 32,
52 22, 24, 25, 27, 28, 30, 32, 33,
53 24, 25, 27, 28, 30, 32, 33, 35
54 };
55
56 typedef struct Vepu510RoiH264BsCfg_t {
57 RK_U64 force_inter : 42;
58 RK_U64 mode_mask : 9;
59 RK_U64 reserved : 10;
60 RK_U64 force_intra : 1;
61 RK_U64 qp_adj_en : 1;
62 RK_U64 amv_en : 1;
63 } Vepu510RoiH264BsCfg;
64
65 typedef struct Vepu510H264Fbk_t {
66 RK_U32 hw_status; /* 0:corret, 1:error */
67 RK_U32 frame_type;
68 RK_U32 qp_sum;
69 RK_U32 out_strm_size;
70 RK_U32 out_hw_strm_size;
71 RK_S64 sse_sum;
72 RK_U32 st_lvl64_inter_num;
73 RK_U32 st_lvl32_inter_num;
74 RK_U32 st_lvl16_inter_num;
75 RK_U32 st_lvl8_inter_num;
76 RK_U32 st_lvl32_intra_num;
77 RK_U32 st_lvl16_intra_num;
78 RK_U32 st_lvl8_intra_num;
79 RK_U32 st_lvl4_intra_num;
80 RK_U32 st_cu_num_qp[52];
81 RK_U32 st_madp;
82 RK_U32 st_madi;
83 RK_U32 st_mb_num;
84 RK_U32 st_ctu_num;
85 RK_U32 st_smear_cnt[5];
86 } Vepu510H264Fbk;
87
88 typedef struct HalH264eVepu510Ctx_t {
89 MppEncCfgSet *cfg;
90
91 MppDev dev;
92 RK_S32 frame_cnt;
93 RK_U32 task_cnt;
94
95 /* buffers management */
96 HalBufs hw_recn;
97 RK_S32 pixel_buf_fbc_hdr_size;
98 RK_S32 pixel_buf_fbc_bdy_size;
99 RK_S32 pixel_buf_size;
100 RK_S32 thumb_buf_size;
101 RK_S32 max_buf_cnt;
102 MppDevRegOffCfgs *offsets;
103
104 /* external line buffer over 4K */
105 MppBufferGroup ext_line_buf_grp;
106 MppBuffer ext_line_bufs[MAX_TASK_CNT];
107 RK_S32 ext_line_buf_size;
108
109 /* syntax for input from enc_impl */
110 RK_U32 updated;
111 H264eSps *sps;
112 H264ePps *pps;
113 H264eDpb *dpb;
114 H264eFrmInfo *frms;
115
116 /* async encode TSVC info */
117 H264eReorderInfo *reorder;
118 H264eMarkingInfo *marking;
119
120 /* syntax for output to enc_impl */
121 EncRcTaskInfo hal_rc_cfg;
122
123 /* roi */
124 void *roi_data;
125 MppBufferGroup roi_grp;
126 MppBuffer roir_buf;
127 RK_S32 roir_buf_size;
128
129 /* two-pass deflicker */
130 MppBuffer buf_pass1;
131
132 /* register */
133 HalVepu510RegSet *regs_sets;
134 HalH264eVepuStreamAmend *amend_sets;
135
136 H264ePrefixNal *prefix_sets;
137 H264eSlice *slice_sets;
138
139 /* frame parallel info */
140 RK_S32 task_idx;
141 RK_S32 curr_idx;
142 RK_S32 prev_idx;
143 HalVepu510RegSet *regs_set;
144 HalH264eVepuStreamAmend *amend;
145 H264ePrefixNal *prefix;
146 H264eSlice *slice;
147
148 MppBuffer ext_line_buf;
149
150 /* slice low delay output callback */
151 MppCbCtx *output_cb;
152 RK_S32 poll_slice_max;
153 RK_S32 poll_cfg_size;
154 MppDevPollCfg *poll_cfgs;
155
156 Vepu510H264Fbk feedback;
157 Vepu510H264Fbk last_frame_fb;
158
159 void *tune;
160 RK_S32 smart_en;
161 RK_S32 qpmap_en;
162 RK_S32 sp_enc_en;
163 } HalH264eVepu510Ctx;
164
165 #include "hal_h264e_vepu510_tune.c"
166
167 static RK_S32 h264_aq_tthd_default[16] = {
168 0, 0, 0, 0, 3, 3, 5, 5,
169 8, 8, 8, 15, 15, 20, 25, 25
170 };
171
172 static RK_S32 h264_P_aq_step_default[16] = {
173 -8, -7, -6, -5, -4, -3, -2, -1,
174 0, 1, 2, 3, 4, 5, 7, 8
175 };
176
177 static RK_S32 h264_I_aq_step_default[16] = {
178 -8, -7, -6, -5, -4, -3, -2, -1,
179 0, 1, 2, 3, 4, 5, 7, 8
180 };
181
setup_ext_line_bufs(HalH264eVepu510Ctx * ctx)182 static void setup_ext_line_bufs(HalH264eVepu510Ctx *ctx)
183 {
184 RK_U32 i;
185
186 for (i = 0; i < ctx->task_cnt; i++) {
187 if (ctx->ext_line_bufs[i])
188 continue;
189
190 mpp_buffer_get(ctx->ext_line_buf_grp, &ctx->ext_line_bufs[i],
191 ctx->ext_line_buf_size);
192 }
193 }
194
clear_ext_line_bufs(HalH264eVepu510Ctx * ctx)195 static void clear_ext_line_bufs(HalH264eVepu510Ctx *ctx)
196 {
197 RK_U32 i;
198
199 for (i = 0; i < ctx->task_cnt; i++) {
200 if (ctx->ext_line_bufs[i]) {
201 mpp_buffer_put(ctx->ext_line_bufs[i]);
202 ctx->ext_line_bufs[i] = NULL;
203 }
204 }
205 }
206
hal_h264e_vepu510_deinit(void * hal)207 static MPP_RET hal_h264e_vepu510_deinit(void *hal)
208 {
209 HalH264eVepu510Ctx *p = (HalH264eVepu510Ctx *)hal;
210 RK_U32 i;
211
212 hal_h264e_dbg_func("enter %p\n", p);
213
214 if (p->dev) {
215 mpp_dev_deinit(p->dev);
216 p->dev = NULL;
217 }
218
219 clear_ext_line_bufs(p);
220
221 if (p->amend_sets) {
222 for (i = 0; i < p->task_cnt; i++)
223 h264e_vepu_stream_amend_deinit(&p->amend_sets[i]);
224 }
225
226 MPP_FREE(p->regs_sets);
227 MPP_FREE(p->amend_sets);
228 MPP_FREE(p->prefix_sets);
229 MPP_FREE(p->slice_sets);
230 MPP_FREE(p->reorder);
231 MPP_FREE(p->marking);
232 MPP_FREE(p->poll_cfgs);
233
234 if (p->ext_line_buf_grp) {
235 mpp_buffer_group_put(p->ext_line_buf_grp);
236 p->ext_line_buf_grp = NULL;
237 }
238
239 if (p->hw_recn) {
240 hal_bufs_deinit(p->hw_recn);
241 p->hw_recn = NULL;
242 }
243
244 if (p->roir_buf) {
245 mpp_buffer_put(p->roir_buf);
246 p->roir_buf = NULL;
247 p->roir_buf_size = 0;
248 }
249
250 if (p->roi_grp) {
251 mpp_buffer_group_put(p->roi_grp);
252 p->roi_grp = NULL;
253 }
254
255 if (p->offsets) {
256 mpp_dev_multi_offset_deinit(p->offsets);
257 p->offsets = NULL;
258 }
259
260 if (p->buf_pass1) {
261 mpp_buffer_put(p->buf_pass1);
262 p->buf_pass1 = NULL;
263 }
264
265 if (p->tune) {
266 vepu510_h264e_tune_deinit(p->tune);
267 p->tune = NULL;
268 }
269
270 hal_h264e_dbg_func("leave %p\n", p);
271
272 return MPP_OK;
273 }
274
hal_h264e_vepu510_init(void * hal,MppEncHalCfg * cfg)275 static MPP_RET hal_h264e_vepu510_init(void *hal, MppEncHalCfg *cfg)
276 {
277 HalH264eVepu510Ctx *p = (HalH264eVepu510Ctx *)hal;
278 MPP_RET ret = MPP_OK;
279 RK_U32 i;
280
281 hal_h264e_dbg_func("enter %p\n", p);
282
283 p->cfg = cfg->cfg;
284
285 /* update output to MppEnc */
286 cfg->type = VPU_CLIENT_RKVENC;
287 ret = mpp_dev_init(&cfg->dev, cfg->type);
288 if (ret) {
289 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
290 goto DONE;
291 }
292 p->dev = cfg->dev;
293 p->task_cnt = cfg->task_cnt;
294 mpp_assert(p->task_cnt && p->task_cnt <= MAX_TASK_CNT);
295
296 ret = hal_bufs_init(&p->hw_recn);
297 if (ret) {
298 mpp_err_f("init vepu buffer failed ret: %d\n", ret);
299 goto DONE;
300 }
301
302 p->regs_sets = mpp_malloc(HalVepu510RegSet, p->task_cnt);
303 if (NULL == p->regs_sets) {
304 ret = MPP_ERR_MALLOC;
305 mpp_err_f("init register buffer failed\n");
306 goto DONE;
307 }
308
309 p->amend_sets = mpp_malloc(HalH264eVepuStreamAmend, p->task_cnt);
310 if (NULL == p->amend_sets) {
311 ret = MPP_ERR_MALLOC;
312 mpp_err_f("init amend data failed\n");
313 goto DONE;
314 }
315
316 if (p->task_cnt > 1) {
317 p->prefix_sets = mpp_malloc(H264ePrefixNal, p->task_cnt);
318 if (NULL == p->prefix_sets) {
319 ret = MPP_ERR_MALLOC;
320 mpp_err_f("init amend data failed\n");
321 goto DONE;
322 }
323
324 p->slice_sets = mpp_malloc(H264eSlice, p->task_cnt);
325 if (NULL == p->slice_sets) {
326 ret = MPP_ERR_MALLOC;
327 mpp_err_f("init amend data failed\n");
328 goto DONE;
329 }
330
331 p->reorder = mpp_malloc(H264eReorderInfo, 1);
332 if (NULL == p->reorder) {
333 ret = MPP_ERR_MALLOC;
334 mpp_err_f("init amend data failed\n");
335 goto DONE;
336 }
337
338 p->marking = mpp_malloc(H264eMarkingInfo, 1);
339 if (NULL == p->marking) {
340 ret = MPP_ERR_MALLOC;
341 mpp_err_f("init amend data failed\n");
342 goto DONE;
343 }
344 }
345
346 p->poll_slice_max = 8;
347 p->poll_cfg_size = (sizeof(p->poll_cfgs) + sizeof(RK_S32) * p->poll_slice_max);
348 p->poll_cfgs = mpp_malloc_size(MppDevPollCfg, p->poll_cfg_size * p->task_cnt);
349 if (NULL == p->poll_cfgs) {
350 ret = MPP_ERR_MALLOC;
351 mpp_err_f("init poll cfg buffer failed\n");
352 goto DONE;
353 }
354
355 { /* setup default hardware config */
356 MppEncHwCfg *hw = &cfg->cfg->hw;
357
358 hw->qp_delta_row_i = 1;
359 hw->qp_delta_row = 2;
360 hw->extra_buf = 1;
361 hw->qbias_i = 683;
362 hw->qbias_p = 341;
363 hw->qbias_en = 0;
364
365 memcpy(hw->aq_thrd_i, h264_aq_tthd_default, sizeof(hw->aq_thrd_i));
366 memcpy(hw->aq_thrd_p, h264_aq_tthd_default, sizeof(hw->aq_thrd_p));
367 memcpy(hw->aq_step_i, h264_I_aq_step_default, sizeof(hw->aq_step_i));
368 memcpy(hw->aq_step_p, h264_P_aq_step_default, sizeof(hw->aq_step_p));
369
370 for (i = 0; i < MPP_ARRAY_ELEMS(hw->mode_bias); i++)
371 hw->mode_bias[i] = 8;
372
373 hw->skip_sad = 8;
374 hw->skip_bias = 8;
375 }
376
377 mpp_dev_multi_offset_init(&p->offsets, 24);
378 p->output_cb = cfg->output_cb;
379 cfg->cap_recn_out = 1;
380 for (i = 0; i < p->task_cnt; i++)
381 h264e_vepu_stream_amend_init(&p->amend_sets[i]);
382
383 p->tune = vepu510_h264e_tune_init(p);
384
385 DONE:
386 if (ret)
387 hal_h264e_vepu510_deinit(hal);
388
389 hal_h264e_dbg_func("leave %p\n", p);
390 return ret;
391 }
392
393 /*
394 * NOTE: recon / refer buffer is FBC data buffer.
395 * And FBC data require extra 16 lines space for hardware io.
396 */
setup_hal_bufs(HalH264eVepu510Ctx * ctx)397 static void setup_hal_bufs(HalH264eVepu510Ctx *ctx)
398 {
399 MppEncCfgSet *cfg = ctx->cfg;
400 MppEncPrepCfg *prep = &cfg->prep;
401 RK_S32 alignment_w = 64;
402 RK_S32 alignment_h = 16;
403 RK_S32 aligned_w = MPP_ALIGN(prep->width, alignment_w);
404 RK_S32 aligned_h = MPP_ALIGN(prep->height, alignment_h) + 16;
405 RK_S32 pixel_buf_fbc_hdr_size = MPP_ALIGN(aligned_w * aligned_h / 64, SZ_8K);
406 RK_S32 pixel_buf_fbc_bdy_size = aligned_w * aligned_h * 3 / 2;
407 RK_S32 pixel_buf_size = pixel_buf_fbc_hdr_size + pixel_buf_fbc_bdy_size;
408 RK_S32 thumb_buf_size = MPP_ALIGN(aligned_w / 64 * aligned_h / 64 * 256, SZ_8K);
409 RK_S32 old_max_cnt = ctx->max_buf_cnt;
410 RK_S32 new_max_cnt = 4;
411 MppEncRefCfg ref_cfg = cfg->ref_cfg;
412
413 if (ref_cfg) {
414 MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
415 if (new_max_cnt < MPP_MAX(new_max_cnt, info->dpb_size + 1))
416 new_max_cnt = MPP_MAX(new_max_cnt, info->dpb_size + 1);
417 }
418
419 if (aligned_w > SZ_4K) {
420 RK_S32 ctu_w = (aligned_w + 63) / 64;
421 RK_S32 ext_line_buf_size = ((ctu_w - 53) * 53 + 15) / 16 * 16 * 16;
422
423 if (NULL == ctx->ext_line_buf_grp)
424 mpp_buffer_group_get_internal(&ctx->ext_line_buf_grp, MPP_BUFFER_TYPE_ION);
425 else if (ext_line_buf_size != ctx->ext_line_buf_size) {
426 clear_ext_line_bufs(ctx);
427 mpp_buffer_group_clear(ctx->ext_line_buf_grp);
428 }
429
430 mpp_assert(ctx->ext_line_buf_grp);
431
432 ctx->ext_line_buf_size = ext_line_buf_size;
433 setup_ext_line_bufs(ctx);
434 } else {
435 clear_ext_line_bufs(ctx);
436 if (ctx->ext_line_buf_grp) {
437 mpp_buffer_group_clear(ctx->ext_line_buf_grp);
438 mpp_buffer_group_put(ctx->ext_line_buf_grp);
439 ctx->ext_line_buf_grp = NULL;
440 }
441 ctx->ext_line_buf_size = 0;
442 }
443
444 if ((ctx->pixel_buf_fbc_hdr_size != pixel_buf_fbc_hdr_size) ||
445 (ctx->pixel_buf_fbc_bdy_size != pixel_buf_fbc_bdy_size) ||
446 (ctx->pixel_buf_size != pixel_buf_size) ||
447 (ctx->thumb_buf_size != thumb_buf_size) ||
448 (new_max_cnt > old_max_cnt)) {
449 size_t sizes[3];
450
451 hal_h264e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
452 ctx->pixel_buf_size, pixel_buf_size,
453 old_max_cnt, new_max_cnt);
454
455 /* pixel buffer */
456 sizes[0] = pixel_buf_size;
457 /* thumb buffer */
458 sizes[1] = thumb_buf_size;
459 /* smear buffer */
460 sizes[2] = MPP_ALIGN(aligned_w / 64, 16) * MPP_ALIGN(aligned_h / 16, 16);
461 new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
462
463 hal_bufs_setup(ctx->hw_recn, new_max_cnt, MPP_ARRAY_ELEMS(sizes), sizes);
464
465 ctx->pixel_buf_fbc_hdr_size = pixel_buf_fbc_hdr_size;
466 ctx->pixel_buf_fbc_bdy_size = pixel_buf_fbc_bdy_size;
467 ctx->pixel_buf_size = pixel_buf_size;
468 ctx->thumb_buf_size = thumb_buf_size;
469 ctx->max_buf_cnt = new_max_cnt;
470 }
471 }
472
hal_h264e_vepu510_prepare(void * hal)473 static MPP_RET hal_h264e_vepu510_prepare(void *hal)
474 {
475 HalH264eVepu510Ctx *ctx = (HalH264eVepu510Ctx *)hal;
476 MppEncPrepCfg *prep = &ctx->cfg->prep;
477
478 hal_h264e_dbg_func("enter %p\n", hal);
479
480 if (prep->change_res) {
481 RK_S32 i;
482
483 // pre-alloc required buffers to reduce first frame delay
484 setup_hal_bufs(ctx);
485 for (i = 0; i < ctx->max_buf_cnt; i++)
486 hal_bufs_get_buf(ctx->hw_recn, i);
487
488 prep->change_res = 0;
489 }
490
491 hal_h264e_dbg_func("leave %p\n", hal);
492
493 return MPP_OK;
494 }
495
update_vepu510_syntax(HalH264eVepu510Ctx * ctx,MppSyntax * syntax)496 static RK_U32 update_vepu510_syntax(HalH264eVepu510Ctx *ctx, MppSyntax *syntax)
497 {
498 H264eSyntaxDesc *desc = syntax->data;
499 RK_S32 syn_num = syntax->number;
500 RK_U32 updated = 0;
501 RK_S32 i;
502
503 for (i = 0; i < syn_num; i++, desc++) {
504 switch (desc->type) {
505 case H264E_SYN_CFG : {
506 hal_h264e_dbg_detail("update cfg");
507 ctx->cfg = desc->p;
508 } break;
509 case H264E_SYN_SPS : {
510 hal_h264e_dbg_detail("update sps");
511 ctx->sps = desc->p;
512 } break;
513 case H264E_SYN_PPS : {
514 hal_h264e_dbg_detail("update pps");
515 ctx->pps = desc->p;
516 } break;
517 case H264E_SYN_DPB : {
518 hal_h264e_dbg_detail("update dpb");
519 ctx->dpb = desc->p;
520 } break;
521 case H264E_SYN_SLICE : {
522 hal_h264e_dbg_detail("update slice");
523 ctx->slice = desc->p;
524 } break;
525 case H264E_SYN_FRAME : {
526 hal_h264e_dbg_detail("update frames");
527 ctx->frms = desc->p;
528 } break;
529 case H264E_SYN_PREFIX : {
530 hal_h264e_dbg_detail("update prefix nal");
531 ctx->prefix = desc->p;
532 } break;
533 default : {
534 mpp_log_f("invalid syntax type %d\n", desc->type);
535 } break;
536 }
537
538 updated |= SYN_TYPE_FLAG(desc->type);
539 }
540
541 return updated;
542 }
543
hal_h264e_vepu510_get_task(void * hal,HalEncTask * task)544 static MPP_RET hal_h264e_vepu510_get_task(void *hal, HalEncTask *task)
545 {
546 HalH264eVepu510Ctx *ctx = (HalH264eVepu510Ctx *)hal;
547 MppEncCfgSet *cfg_set = ctx->cfg;
548 MppEncRefCfgImpl *ref = (MppEncRefCfgImpl *)cfg_set->ref_cfg;
549 MppEncH264HwCfg *hw_cfg = &cfg_set->h264.hw_cfg;
550 RK_U32 updated = update_vepu510_syntax(ctx, &task->syntax);
551 EncFrmStatus *frm_status = &task->rc_task->frm;
552 H264eFrmInfo *frms = ctx->frms;
553
554 hal_h264e_dbg_func("enter %p\n", hal);
555
556 ctx->smart_en = (ctx->cfg->rc.rc_mode == MPP_ENC_RC_MODE_SMTRC);
557 ctx->qpmap_en = ctx->cfg->tune.deblur_en;
558 ctx->sp_enc_en = ctx->cfg->rc.rc_mode == MPP_ENC_RC_MODE_SE;
559
560 if (updated & SYN_TYPE_FLAG(H264E_SYN_CFG))
561 setup_hal_bufs(ctx);
562
563 if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
564 MppMeta meta = mpp_frame_get_meta(task->frame);
565 mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
566 }
567
568 if (!frm_status->reencode)
569 ctx->last_frame_fb = ctx->feedback;
570
571 if (ctx->dpb) {
572 h264e_dpb_hal_start(ctx->dpb, frms->curr_idx);
573 h264e_dpb_hal_start(ctx->dpb, frms->refr_idx);
574 }
575
576 task->flags.reg_idx = ctx->task_idx;
577 task->flags.curr_idx = frms->curr_idx;
578 task->flags.refr_idx = frms->refr_idx;
579 task->part_first = 1;
580 task->part_last = 0;
581
582 ctx->ext_line_buf = ctx->ext_line_bufs[ctx->task_idx];
583 ctx->regs_set = &ctx->regs_sets[ctx->task_idx];
584 ctx->amend = &ctx->amend_sets[ctx->task_idx];
585
586 /* if not VEPU1/2, update log2_max_frame_num_minus4 in hw_cfg */
587 hw_cfg->hw_log2_max_frame_num_minus4 = ctx->sps->log2_max_frame_num_minus4;
588 hw_cfg->hw_poc_type = ctx->sps->pic_order_cnt_type;
589
590 if (ctx->task_cnt > 1 && (ref->lt_cfg_cnt || ref->st_cfg_cnt > 1)) {
591 H264ePrefixNal *prefix = &ctx->prefix_sets[ctx->task_idx];
592 H264eSlice *slice = &ctx->slice_sets[ctx->task_idx];
593
594 //store async encode TSVC info
595 if (ctx->prefix)
596 memcpy(prefix, ctx->prefix, sizeof(H264ePrefixNal));
597 else
598 prefix = NULL;
599
600 if (ctx->slice) {
601 memcpy(slice, ctx->slice, sizeof(H264eSlice));
602
603 /*
604 * Generally, reorder and marking are shared by dpb and slice.
605 * However, async encoding TSVC will change reorder and marking in each task.
606 * Therefore, malloc a special space for async encoding TSVC.
607 */
608 ctx->amend->reorder = ctx->reorder;
609 ctx->amend->marking = ctx->marking;
610 }
611
612 h264e_vepu_stream_amend_config(ctx->amend, task->packet, ctx->cfg,
613 slice, prefix);
614 } else {
615 h264e_vepu_stream_amend_config(ctx->amend, task->packet, ctx->cfg,
616 ctx->slice, ctx->prefix);
617 }
618
619 if (ctx->task_cnt > 1)
620 ctx->task_idx = !ctx->task_idx;
621
622 hal_h264e_dbg_func("leave %p\n", hal);
623
624 return MPP_OK;
625 }
626
setup_vepu510_normal(HalVepu510RegSet * regs)627 static void setup_vepu510_normal(HalVepu510RegSet *regs)
628 {
629 hal_h264e_dbg_func("enter\n");
630 /* reg000 VERSION is read only */
631
632 /* reg001 ENC_STRT */
633 regs->reg_ctl.enc_strt.lkt_num = 0;
634 regs->reg_ctl.enc_strt.vepu_cmd = 1;
635
636 regs->reg_ctl.opt_strg.cke = 1;
637 regs->reg_ctl.opt_strg.resetn_hw_en = 1;
638
639 /* reg002 ENC_CLR */
640 regs->reg_ctl.enc_clr.safe_clr = 0;
641 regs->reg_ctl.enc_clr.force_clr = 0;
642
643 /* reg004 INT_EN */
644 regs->reg_ctl.int_en.enc_done_en = 1;
645 regs->reg_ctl.int_en.lkt_node_done_en = 1;
646 regs->reg_ctl.int_en.sclr_done_en = 1;
647 regs->reg_ctl.int_en.vslc_done_en = 0;
648 regs->reg_ctl.int_en.vbsf_oflw_en = 1;
649 regs->reg_ctl.int_en.vbuf_lens_en = 1;
650 regs->reg_ctl.int_en.enc_err_en = 1;
651
652 regs->reg_ctl.int_en.wdg_en = 1;
653 regs->reg_ctl.int_en.vsrc_err_en = 1;
654 regs->reg_ctl.int_en.wdg_en = 1;
655 regs->reg_ctl.int_en.lkt_err_int_en = 1;
656 regs->reg_ctl.int_en.lkt_err_stop_en = 1;
657 regs->reg_ctl.int_en.lkt_force_stop_en = 1;
658 regs->reg_ctl.int_en.jslc_done_en = 1;
659 regs->reg_ctl.int_en.jbsf_oflw_en = 1;
660 regs->reg_ctl.int_en.jbuf_lens_en = 1;
661 regs->reg_ctl.int_en.dvbm_err_en = 0;
662
663 /* reg005 INT_MSK */
664 regs->reg_ctl.int_msk.enc_done_msk = 0;
665 regs->reg_ctl.int_msk.lkt_node_done_msk = 0;
666 regs->reg_ctl.int_msk.sclr_done_msk = 0;
667 regs->reg_ctl.int_msk.vslc_done_msk = 0;
668 regs->reg_ctl.int_msk.vbsf_oflw_msk = 0;
669 regs->reg_ctl.int_msk.vbuf_lens_msk = 0;
670 regs->reg_ctl.int_msk.enc_err_msk = 0;
671 regs->reg_ctl.int_msk.vsrc_err_msk = 0;
672 regs->reg_ctl.int_msk.wdg_msk = 0;
673 regs->reg_ctl.int_msk.lkt_err_int_msk = 0;
674 regs->reg_ctl.int_msk.lkt_err_stop_msk = 0;
675 regs->reg_ctl.int_msk.lkt_force_stop_msk = 0;
676 regs->reg_ctl.int_msk.jslc_done_msk = 0;
677 regs->reg_ctl.int_msk.jbsf_oflw_msk = 0;
678 regs->reg_ctl.int_msk.jbuf_lens_msk = 0;
679 regs->reg_ctl.int_msk.dvbm_err_msk = 0;
680
681 /* reg006 INT_CLR is not set */
682 /* reg007 INT_STA is read only */
683 /* reg008 ~ reg0011 gap */
684 regs->reg_ctl.enc_wdg.vs_load_thd = 0;
685
686 /* reg015 DTRNS_MAP */
687 regs->reg_ctl.dtrns_map.jpeg_bus_edin = 0;
688 regs->reg_ctl.dtrns_map.src_bus_edin = 0;
689 regs->reg_ctl.dtrns_map.meiw_bus_edin = 0;
690 regs->reg_ctl.dtrns_map.bsw_bus_edin = 7;
691 regs->reg_ctl.dtrns_map.lktw_bus_edin = 0;
692 regs->reg_ctl.dtrns_map.rec_nfbc_bus_edin = 0;
693
694 regs->reg_ctl.dtrns_cfg.axi_brsp_cke = 0;
695
696 hal_h264e_dbg_func("leave\n");
697 }
698
setup_vepu510_prep(HalVepu510RegSet * regs,MppEncPrepCfg * prep)699 static MPP_RET setup_vepu510_prep(HalVepu510RegSet *regs, MppEncPrepCfg *prep)
700 {
701 H264eVepu510Frame *reg_frm = ®s->reg_frm;
702 VepuFmtCfg cfg;
703 MppFrameFormat fmt = prep->format;
704 MPP_RET ret = vepu5xx_set_fmt(&cfg, fmt);
705 RK_U32 hw_fmt = cfg.format;
706 RK_S32 y_stride;
707 RK_S32 c_stride;
708
709 hal_h264e_dbg_func("enter\n");
710
711 /* do nothing when color format is not supported */
712 if (ret)
713 return ret;
714
715 reg_frm->common.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1;
716 reg_frm->common.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width;
717 reg_frm->common.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1;
718 reg_frm->common.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height;
719
720 regs->reg_ctl.dtrns_map.src_bus_edin = cfg.src_endian;
721
722 reg_frm->common.src_fmt.src_cfmt = hw_fmt;
723 reg_frm->common.src_fmt.alpha_swap = cfg.alpha_swap;
724 reg_frm->common.src_fmt.rbuv_swap = cfg.rbuv_swap;
725 reg_frm->common.src_fmt.out_fmt = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400 ? 0 : 1);
726
727 if (MPP_FRAME_FMT_IS_FBC(fmt)) {
728 mpp_err("Unsupported FBC format input.\n");
729
730 return MPP_ERR_VALUE;
731 } else if (prep->hor_stride) {
732 if (MPP_FRAME_FMT_IS_TILE(fmt)) {
733 switch (fmt & MPP_FRAME_FMT_MASK) {
734 case MPP_FMT_YUV400:
735 y_stride = prep->hor_stride * 4;
736 break;
737 case MPP_FMT_YUV420P:
738 case MPP_FMT_YUV420SP:
739 y_stride = prep->hor_stride * 4 * 3 / 2;
740 break;
741 case MPP_FMT_YUV422P:
742 case MPP_FMT_YUV422SP:
743 y_stride = prep->hor_stride * 4 * 2;
744 break;
745 case MPP_FMT_YUV444P:
746 case MPP_FMT_YUV444SP:
747 y_stride = prep->hor_stride * 4 * 3;
748 break;
749 default:
750 mpp_err("Unsupported input format 0x%08x, with TILE mask.\n", fmt);
751 return MPP_ERR_VALUE;
752 break;
753 }
754 } else {
755 y_stride = prep->hor_stride;
756 }
757 } else {
758 if (hw_fmt == VEPU5xx_FMT_BGRA8888 )
759 y_stride = prep->width * 4;
760 else if (hw_fmt == VEPU5xx_FMT_BGR888 )
761 y_stride = prep->width * 3;
762 else if (hw_fmt == VEPU5xx_FMT_BGR565 ||
763 hw_fmt == VEPU5xx_FMT_YUYV422 ||
764 hw_fmt == VEPU5xx_FMT_UYVY422)
765 y_stride = prep->width * 2;
766 else
767 y_stride = prep->width;
768 }
769
770 switch (hw_fmt) {
771 case VEPU5xx_FMT_YUV444SP : {
772 c_stride = y_stride * 2;
773 } break;
774 case VEPU5xx_FMT_YUV422SP :
775 case VEPU5xx_FMT_YUV420SP :
776 case VEPU5xx_FMT_YUV444P : {
777 c_stride = y_stride;
778 } break;
779 default : {
780 c_stride = y_stride / 2;
781 } break;
782 }
783
784 if (hw_fmt < VEPU5xx_FMT_ARGB1555) {
785 const VepuRgb2YuvCfg *cfg_coeffs = get_rgb2yuv_cfg(prep->range, prep->color);
786
787 hal_h264e_dbg_flow("input color range %d colorspace %d", prep->range, prep->color);
788
789 reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff;
790 reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff;
791 reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff;
792
793 reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff;
794 reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff;
795 reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff;
796
797 reg_frm->common.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff;
798 reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff;
799 reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff;
800
801 reg_frm->common.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset;
802 reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset;
803 reg_frm->common.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset;
804
805 hal_h264e_dbg_flow("use color range %d colorspace %d", cfg_coeffs->dst_range, cfg_coeffs->color);
806 } else {
807 reg_frm->common.src_udfy.csc_wgt_b2y = cfg.weight[0];
808 reg_frm->common.src_udfy.csc_wgt_g2y = cfg.weight[1];
809 reg_frm->common.src_udfy.csc_wgt_r2y = cfg.weight[2];
810
811 reg_frm->common.src_udfu.csc_wgt_b2u = cfg.weight[3];
812 reg_frm->common.src_udfu.csc_wgt_g2u = cfg.weight[4];
813 reg_frm->common.src_udfu.csc_wgt_r2u = cfg.weight[5];
814
815 reg_frm->common.src_udfv.csc_wgt_b2v = cfg.weight[6];
816 reg_frm->common.src_udfv.csc_wgt_g2v = cfg.weight[7];
817 reg_frm->common.src_udfv.csc_wgt_r2v = cfg.weight[8];
818
819 reg_frm->common.src_udfo.csc_ofst_y = cfg.offset[0];
820 reg_frm->common.src_udfo.csc_ofst_u = cfg.offset[1];
821 reg_frm->common.src_udfo.csc_ofst_v = cfg.offset[2];
822 }
823
824 reg_frm->common.src_strd0.src_strd0 = y_stride;
825 reg_frm->common.src_strd1.src_strd1 = c_stride;
826
827 reg_frm->common.src_proc.src_mirr = prep->mirroring > 0;
828 reg_frm->common.src_proc.src_rot = prep->rotation;
829
830 if (MPP_FRAME_FMT_IS_TILE(fmt))
831 reg_frm->common.src_proc.tile4x4_en = 1;
832 else
833 reg_frm->common.src_proc.tile4x4_en = 0;
834
835 reg_frm->sli_cfg.mv_v_lmt_thd = 0;
836 reg_frm->sli_cfg.mv_v_lmt_en = 0;
837
838 reg_frm->common.pic_ofst.pic_ofst_y = 0;
839 reg_frm->common.pic_ofst.pic_ofst_x = 0;
840
841 hal_h264e_dbg_func("leave\n");
842
843 return ret;
844 }
845
vepu510_h264e_save_pass1_patch(HalVepu510RegSet * regs,HalH264eVepu510Ctx * ctx)846 static MPP_RET vepu510_h264e_save_pass1_patch(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ctx)
847 {
848 H264eVepu510Frame *reg_frm = ®s->reg_frm;
849 RK_S32 width_align = MPP_ALIGN(ctx->cfg->prep.width, 16);
850 RK_S32 height_align = MPP_ALIGN(ctx->cfg->prep.height, 16);
851
852 if (NULL == ctx->buf_pass1) {
853 mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2);
854 if (!ctx->buf_pass1) {
855 mpp_err("buf_pass1 malloc fail, debreath invaild");
856 return MPP_NOK;
857 }
858 }
859
860 reg_frm->common.enc_pic.cur_frm_ref = 1;
861 reg_frm->common.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1);
862 reg_frm->common.rfpw_b_addr = reg_frm->common.rfpw_h_addr;
863 reg_frm->common.enc_pic.rec_fbc_dis = 1;
864
865 mpp_dev_multi_offset_update(ctx->offsets, 164, 0);
866
867 /* NOTE: disable split to avoid lowdelay slice output */
868 reg_frm->common.sli_splt.sli_splt = 0;
869 reg_frm->common.enc_pic.slen_fifo = 0;
870
871 return MPP_OK;
872 }
873
vepu510_h264e_use_pass1_patch(HalVepu510RegSet * regs,HalH264eVepu510Ctx * ctx)874 static MPP_RET vepu510_h264e_use_pass1_patch(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ctx)
875 {
876 MppEncPrepCfg *prep = &ctx->cfg->prep;
877 H264eVepu510Frame *reg_frm = ®s->reg_frm;
878 RK_S32 fd_in = mpp_buffer_get_fd(ctx->buf_pass1);
879 RK_S32 y_stride;
880 RK_S32 c_stride;
881
882 hal_h264e_dbg_func("enter\n");
883
884 reg_frm->common.src_fmt.src_cfmt = VEPU5xx_FMT_YUV420SP;
885 reg_frm->common.src_fmt.alpha_swap = 0;
886 reg_frm->common.src_fmt.rbuv_swap = 0;
887 reg_frm->common.src_fmt.out_fmt = 1;
888 reg_frm->common.src_fmt.src_rcne = 1;
889 y_stride = MPP_ALIGN(prep->width, 16);
890 c_stride = y_stride;
891
892 reg_frm->common.src_strd0.src_strd0 = y_stride;
893 reg_frm->common.src_strd1.src_strd1 = 3 * c_stride;
894
895 reg_frm->common.src_proc.src_mirr = 0;
896 reg_frm->common.src_proc.src_rot = 0;
897
898 reg_frm->common.pic_ofst.pic_ofst_y = 0;
899 reg_frm->common.pic_ofst.pic_ofst_x = 0;
900
901
902 reg_frm->common.adr_src0 = fd_in;
903 reg_frm->common.adr_src1 = fd_in;
904 reg_frm->common.adr_src2 = fd_in;
905
906 mpp_dev_multi_offset_update(ctx->offsets, 161, 2 * y_stride);
907
908 hal_h264e_dbg_func("leave\n");
909 return MPP_OK;
910 }
911
setup_vepu510_codec(HalVepu510RegSet * regs,H264eSps * sps,H264ePps * pps,H264eSlice * slice)912 static void setup_vepu510_codec(HalVepu510RegSet *regs, H264eSps *sps,
913 H264ePps *pps, H264eSlice *slice)
914 {
915 H264eVepu510Frame *reg_frm = ®s->reg_frm;
916
917 hal_h264e_dbg_func("enter\n");
918
919 reg_frm->common.enc_pic.enc_stnd = 0;
920 reg_frm->common.enc_pic.cur_frm_ref = slice->nal_reference_idc > 0;
921 reg_frm->common.enc_pic.bs_scp = 1;
922
923 reg_frm->synt_nal.nal_ref_idc = slice->nal_reference_idc;
924 reg_frm->synt_nal.nal_unit_type = slice->nalu_type;
925
926 reg_frm->synt_sps.max_fnum = sps->log2_max_frame_num_minus4;
927 reg_frm->synt_sps.drct_8x8 = sps->direct8x8_inference;
928 reg_frm->synt_sps.mpoc_lm4 = sps->log2_max_poc_lsb_minus4;
929 reg_frm->synt_sps.poc_type = sps->pic_order_cnt_type;
930
931 reg_frm->synt_pps.etpy_mode = pps->entropy_coding_mode;
932 reg_frm->synt_pps.trns_8x8 = pps->transform_8x8_mode;
933 reg_frm->synt_pps.csip_flag = pps->constrained_intra_pred;
934 reg_frm->synt_pps.num_ref0_idx = pps->num_ref_idx_l0_default_active - 1;
935 reg_frm->synt_pps.num_ref1_idx = pps->num_ref_idx_l1_default_active - 1;
936 reg_frm->synt_pps.pic_init_qp = pps->pic_init_qp;
937 reg_frm->synt_pps.cb_ofst = pps->chroma_qp_index_offset;
938 reg_frm->synt_pps.cr_ofst = pps->second_chroma_qp_index_offset;
939 reg_frm->synt_pps.dbf_cp_flg = pps->deblocking_filter_control;
940
941 reg_frm->synt_sli0.sli_type = (slice->slice_type == H264_I_SLICE) ? (2) : (0);
942 reg_frm->synt_sli0.pps_id = slice->pic_parameter_set_id;
943 reg_frm->synt_sli0.drct_smvp = 0;
944 reg_frm->synt_sli0.num_ref_ovrd = slice->num_ref_idx_override;
945 reg_frm->synt_sli0.cbc_init_idc = slice->cabac_init_idc;
946 reg_frm->synt_sli0.frm_num = slice->frame_num;
947
948 reg_frm->synt_sli1.idr_pid = (slice->slice_type == H264_I_SLICE) ? slice->idr_pic_id : (RK_U32)(-1);
949 reg_frm->synt_sli1.poc_lsb = slice->pic_order_cnt_lsb;
950
951
952 reg_frm->synt_sli2.dis_dblk_idc = slice->disable_deblocking_filter_idc;
953 reg_frm->synt_sli2.sli_alph_ofst = slice->slice_alpha_c0_offset_div2;
954
955 h264e_reorder_rd_rewind(slice->reorder);
956 { /* reorder process */
957 H264eRplmo rplmo;
958 MPP_RET ret = h264e_reorder_rd_op(slice->reorder, &rplmo);
959
960 if (MPP_OK == ret) {
961 reg_frm->synt_sli2.ref_list0_rodr = 1;
962 reg_frm->synt_sli2.rodr_pic_idx = rplmo.modification_of_pic_nums_idc;
963
964 switch (rplmo.modification_of_pic_nums_idc) {
965 case 0 :
966 case 1 : {
967 reg_frm->synt_sli2.rodr_pic_num = rplmo.abs_diff_pic_num_minus1;
968 } break;
969 case 2 : {
970 reg_frm->synt_sli2.rodr_pic_num = rplmo.long_term_pic_idx;
971 } break;
972 default : {
973 mpp_err_f("invalid modification_of_pic_nums_idc %d\n",
974 rplmo.modification_of_pic_nums_idc);
975 } break;
976 }
977 } else {
978 // slice->ref_pic_list_modification_flag;
979 reg_frm->synt_sli2.ref_list0_rodr = 0;
980 reg_frm->synt_sli2.rodr_pic_idx = 0;
981 reg_frm->synt_sli2.rodr_pic_num = 0;
982 }
983 }
984
985 /* clear all mmco arg first */
986 reg_frm->synt_refm0.nopp_flg = 0;
987 reg_frm->synt_refm0.ltrf_flg = 0;
988 reg_frm->synt_refm0.arpm_flg = 0;
989 reg_frm->synt_refm0.mmco4_pre = 0;
990 reg_frm->synt_refm0.mmco_type0 = 0;
991 reg_frm->synt_refm0.mmco_parm0 = 0;
992 reg_frm->synt_refm0.mmco_type1 = 0;
993 reg_frm->synt_refm1.mmco_parm1 = 0;
994 reg_frm->synt_refm0.mmco_type2 = 0;
995 reg_frm->synt_refm1.mmco_parm2 = 0;
996 reg_frm->synt_refm2.long_term_frame_idx0 = 0;
997 reg_frm->synt_refm2.long_term_frame_idx1 = 0;
998 reg_frm->synt_refm2.long_term_frame_idx2 = 0;
999
1000 h264e_marking_rd_rewind(slice->marking);
1001
1002 /* only update used parameter */
1003 if (slice->slice_type == H264_I_SLICE) {
1004 reg_frm->synt_refm0.nopp_flg = slice->no_output_of_prior_pics;
1005 reg_frm->synt_refm0.ltrf_flg = slice->long_term_reference_flag;
1006 } else {
1007 if (!h264e_marking_is_empty(slice->marking)) {
1008 H264eMmco mmco;
1009
1010 reg_frm->synt_refm0.arpm_flg = 1;
1011
1012 /* max 3 mmco */
1013 do {
1014 RK_S32 type = 0;
1015 RK_S32 param_0 = 0;
1016 RK_S32 param_1 = 0;
1017
1018 h264e_marking_rd_op(slice->marking, &mmco);
1019 type = mmco.mmco;
1020 switch (type) {
1021 case 1 : {
1022 param_0 = mmco.difference_of_pic_nums_minus1;
1023 } break;
1024 case 2 : {
1025 param_0 = mmco.long_term_pic_num;
1026 } break;
1027 case 3 : {
1028 param_0 = mmco.difference_of_pic_nums_minus1;
1029 param_1 = mmco.long_term_frame_idx;
1030 } break;
1031 case 4 : {
1032 param_0 = mmco.max_long_term_frame_idx_plus1;
1033 } break;
1034 case 5 : {
1035 } break;
1036 case 6 : {
1037 param_0 = mmco.long_term_frame_idx;
1038 } break;
1039 default : {
1040 mpp_err_f("unsupported mmco 0 %d\n", type);
1041 type = 0;
1042 } break;
1043 }
1044
1045 reg_frm->synt_refm0.mmco_type0 = type;
1046 reg_frm->synt_refm0.mmco_parm0 = param_0;
1047 reg_frm->synt_refm2.long_term_frame_idx0 = param_1;
1048
1049 if (h264e_marking_is_empty(slice->marking))
1050 break;
1051
1052 h264e_marking_rd_op(slice->marking, &mmco);
1053 type = mmco.mmco;
1054 param_0 = 0;
1055 param_1 = 0;
1056 switch (type) {
1057 case 1 : {
1058 param_0 = mmco.difference_of_pic_nums_minus1;
1059 } break;
1060 case 2 : {
1061 param_0 = mmco.long_term_pic_num;
1062 } break;
1063 case 3 : {
1064 param_0 = mmco.difference_of_pic_nums_minus1;
1065 param_1 = mmco.long_term_frame_idx;
1066 } break;
1067 case 4 : {
1068 param_0 = mmco.max_long_term_frame_idx_plus1;
1069 } break;
1070 case 5 : {
1071 } break;
1072 case 6 : {
1073 param_0 = mmco.long_term_frame_idx;
1074 } break;
1075 default : {
1076 mpp_err_f("unsupported mmco 0 %d\n", type);
1077 type = 0;
1078 } break;
1079 }
1080
1081 reg_frm->synt_refm0.mmco_type1 = type;
1082 reg_frm->synt_refm1.mmco_parm1 = param_0;
1083 reg_frm->synt_refm2.long_term_frame_idx1 = param_1;
1084
1085 if (h264e_marking_is_empty(slice->marking))
1086 break;
1087
1088 h264e_marking_rd_op(slice->marking, &mmco);
1089 type = mmco.mmco;
1090 param_0 = 0;
1091 param_1 = 0;
1092 switch (type) {
1093 case 1 : {
1094 param_0 = mmco.difference_of_pic_nums_minus1;
1095 } break;
1096 case 2 : {
1097 param_0 = mmco.long_term_pic_num;
1098 } break;
1099 case 3 : {
1100 param_0 = mmco.difference_of_pic_nums_minus1;
1101 param_1 = mmco.long_term_frame_idx;
1102 } break;
1103 case 4 : {
1104 param_0 = mmco.max_long_term_frame_idx_plus1;
1105 } break;
1106 case 5 : {
1107 } break;
1108 case 6 : {
1109 param_0 = mmco.long_term_frame_idx;
1110 } break;
1111 default : {
1112 mpp_err_f("unsupported mmco 0 %d\n", type);
1113 type = 0;
1114 } break;
1115 }
1116
1117 reg_frm->synt_refm0.mmco_type2 = type;
1118 reg_frm->synt_refm1.mmco_parm2 = param_0;
1119 reg_frm->synt_refm2.long_term_frame_idx2 = param_1;
1120 } while (0);
1121 }
1122 }
1123
1124 hal_h264e_dbg_func("leave\n");
1125 }
1126
setup_vepu510_rdo_pred(HalH264eVepu510Ctx * ctx,H264eSps * sps,H264ePps * pps,H264eSlice * slice)1127 static void setup_vepu510_rdo_pred(HalH264eVepu510Ctx *ctx, H264eSps *sps,
1128 H264ePps *pps, H264eSlice *slice)
1129 {
1130 HalVepu510RegSet *regs = ctx->regs_set;
1131 H264eVepu510Frame *reg_frm = ®s->reg_frm;
1132 RK_U32 is_ipc_scene = (ctx->cfg->tune.scene_mode == MPP_ENC_SCENE_MODE_IPC);
1133
1134 hal_h264e_dbg_func("enter\n");
1135
1136 if (slice->slice_type == H264_I_SLICE) {
1137 regs->reg_rc_roi.klut_ofst.chrm_klut_ofst = 6;
1138 } else {
1139 regs->reg_rc_roi.klut_ofst.chrm_klut_ofst = is_ipc_scene ? 9 : 6;
1140 }
1141
1142 reg_frm->rdo_cfg.rect_size = (sps->profile_idc == H264_PROFILE_BASELINE &&
1143 sps->level_idc <= H264_LEVEL_3_0) ? 1 : 0;
1144 reg_frm->rdo_cfg.vlc_lmt = (sps->profile_idc < H264_PROFILE_MAIN) &&
1145 !pps->entropy_coding_mode;
1146 reg_frm->rdo_cfg.chrm_spcl = 1;
1147 reg_frm->rdo_cfg.ccwa_e = 1;
1148 reg_frm->rdo_cfg.scl_lst_sel = pps->pic_scaling_matrix_present;
1149 reg_frm->rdo_cfg.atf_e = ctx->cfg->tune.anti_flicker_str > 0;
1150 reg_frm->rdo_cfg.atr_e = ctx->cfg->tune.atr_str_i > 0;
1151 reg_frm->rdo_cfg.atr_mult_sel_e = 1;
1152 reg_frm->iprd_csts.rdo_mark_mode = 0;
1153
1154 hal_h264e_dbg_func("leave\n");
1155 }
1156
setup_vepu510_rc_base(HalVepu510RegSet * regs,HalH264eVepu510Ctx * ctx,EncRcTask * rc_task)1157 static void setup_vepu510_rc_base(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ctx, EncRcTask *rc_task)
1158 {
1159 H264eSps *sps = ctx->sps;
1160 H264eSlice *slice = ctx->slice;
1161 MppEncCfgSet *cfg = ctx->cfg;
1162 MppEncRcCfg *rc = &cfg->rc;
1163 MppEncHwCfg *hw = &cfg->hw;
1164 EncRcTaskInfo *rc_info = &rc_task->info;
1165 H264eVepu510Frame *reg_frm = ®s->reg_frm;
1166 RK_S32 mb_w = sps->pic_width_in_mbs;
1167 RK_S32 mb_h = sps->pic_height_in_mbs;
1168 RK_U32 qp_target = rc_info->quality_target;
1169 RK_U32 qp_min = rc_info->quality_min;
1170 RK_U32 qp_max = rc_info->quality_max;
1171 RK_U32 qpmap_mode = 1;
1172 RK_S32 mb_target_bits_mul_16 = (rc_info->bit_target << 4) / (mb_w * mb_h);
1173 RK_S32 mb_target_bits;
1174 RK_S32 negative_bits_thd;
1175 RK_S32 positive_bits_thd;
1176
1177 hal_h264e_dbg_rc("bittarget %d qp [%d %d %d]\n", rc_info->bit_target,
1178 qp_min, qp_target, qp_max);
1179
1180 hal_h264e_dbg_func("enter\n");
1181
1182 regs->reg_rc_roi.roi_qthd0.qpmin_area0 = qp_min;
1183 regs->reg_rc_roi.roi_qthd0.qpmax_area0 = qp_max;
1184 regs->reg_rc_roi.roi_qthd0.qpmin_area1 = qp_min;
1185 regs->reg_rc_roi.roi_qthd0.qpmax_area1 = qp_max;
1186 regs->reg_rc_roi.roi_qthd0.qpmin_area2 = qp_min;
1187
1188 regs->reg_rc_roi.roi_qthd1.qpmax_area2 = qp_max;
1189 regs->reg_rc_roi.roi_qthd1.qpmin_area3 = qp_min;
1190 regs->reg_rc_roi.roi_qthd1.qpmax_area3 = qp_max;
1191 regs->reg_rc_roi.roi_qthd1.qpmin_area4 = qp_min;
1192 regs->reg_rc_roi.roi_qthd1.qpmax_area4 = qp_max;
1193
1194 regs->reg_rc_roi.roi_qthd2.qpmin_area5 = qp_min;
1195 regs->reg_rc_roi.roi_qthd2.qpmax_area5 = qp_max;
1196 regs->reg_rc_roi.roi_qthd2.qpmin_area6 = qp_min;
1197 regs->reg_rc_roi.roi_qthd2.qpmax_area6 = qp_max;
1198 regs->reg_rc_roi.roi_qthd2.qpmin_area7 = qp_min;
1199
1200 regs->reg_rc_roi.roi_qthd3.qpmax_area7 = qp_max;
1201 regs->reg_rc_roi.roi_qthd3.qpmap_mode = qpmap_mode;
1202
1203 if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) {
1204 reg_frm->common.enc_pic.pic_qp = rc_info->quality_target;
1205 reg_frm->common.rc_qp.rc_max_qp = rc_info->quality_target;
1206 reg_frm->common.rc_qp.rc_min_qp = rc_info->quality_target;
1207
1208 return;
1209 }
1210
1211 if (mb_target_bits_mul_16 >= 0x100000)
1212 mb_target_bits_mul_16 = 0x50000;
1213
1214 mb_target_bits = (mb_target_bits_mul_16 * mb_w) >> 4;
1215 negative_bits_thd = 0 - 5 * mb_target_bits / 16;
1216 positive_bits_thd = 5 * mb_target_bits / 16;
1217
1218 reg_frm->common.enc_pic.pic_qp = qp_target;
1219
1220 reg_frm->common.rc_cfg.rc_en = 1;
1221 reg_frm->common.rc_cfg.aq_en = 1;
1222 reg_frm->common.rc_cfg.rc_ctu_num = mb_w;
1223
1224 reg_frm->common.rc_qp.rc_max_qp = qp_max;
1225 reg_frm->common.rc_qp.rc_min_qp = qp_min;
1226 reg_frm->common.rc_tgt.ctu_ebit = mb_target_bits_mul_16;
1227
1228 if (rc->rc_mode == MPP_ENC_RC_MODE_SMTRC || rc->rc_mode == MPP_ENC_RC_MODE_SE) {
1229 reg_frm->common.rc_qp.rc_qp_range = 0;
1230 } else {
1231 reg_frm->common.rc_qp.rc_qp_range = (slice->slice_type == H264_I_SLICE) ?
1232 hw->qp_delta_row_i : hw->qp_delta_row;
1233 }
1234
1235 {
1236 /* fixed frame level QP */
1237 RK_S32 fqp_min, fqp_max;
1238
1239 if (slice->slice_type == H264_I_SLICE) {
1240 fqp_min = rc->fqp_min_i;
1241 fqp_max = rc->fqp_max_i;
1242 } else {
1243 fqp_min = rc->fqp_min_p;
1244 fqp_max = rc->fqp_max_p;
1245 }
1246
1247 if ((fqp_min == fqp_max) && (fqp_min >= 1) && (fqp_max <= 51)) {
1248 reg_frm->common.enc_pic.pic_qp = fqp_min;
1249 reg_frm->common.rc_qp.rc_qp_range = 0;
1250 }
1251 }
1252
1253 regs->reg_rc_roi.rc_adj0.qp_adj0 = -2;
1254 regs->reg_rc_roi.rc_adj0.qp_adj1 = -1;
1255 regs->reg_rc_roi.rc_adj0.qp_adj2 = 0;
1256 regs->reg_rc_roi.rc_adj0.qp_adj3 = 1;
1257 regs->reg_rc_roi.rc_adj0.qp_adj4 = 2;
1258 regs->reg_rc_roi.rc_adj1.qp_adj5 = 0;
1259 regs->reg_rc_roi.rc_adj1.qp_adj6 = 0;
1260 regs->reg_rc_roi.rc_adj1.qp_adj7 = 0;
1261 regs->reg_rc_roi.rc_adj1.qp_adj8 = 0;
1262
1263 regs->reg_rc_roi.rc_dthd_0_8[0] = 4 * negative_bits_thd;
1264 regs->reg_rc_roi.rc_dthd_0_8[1] = negative_bits_thd;
1265 regs->reg_rc_roi.rc_dthd_0_8[2] = positive_bits_thd;
1266 regs->reg_rc_roi.rc_dthd_0_8[3] = 4 * positive_bits_thd;
1267 regs->reg_rc_roi.rc_dthd_0_8[4] = 0x7FFFFFFF;
1268 regs->reg_rc_roi.rc_dthd_0_8[5] = 0x7FFFFFFF;
1269 regs->reg_rc_roi.rc_dthd_0_8[6] = 0x7FFFFFFF;
1270 regs->reg_rc_roi.rc_dthd_0_8[7] = 0x7FFFFFFF;
1271 regs->reg_rc_roi.rc_dthd_0_8[8] = 0x7FFFFFFF;
1272
1273 hal_h264e_dbg_func("leave\n");
1274 }
1275
setup_vepu510_io_buf(HalVepu510RegSet * regs,MppDevRegOffCfgs * offsets,HalEncTask * task)1276 static void setup_vepu510_io_buf(HalVepu510RegSet *regs, MppDevRegOffCfgs *offsets,
1277 HalEncTask *task)
1278 {
1279 MppFrame frm = task->frame;
1280 MppPacket pkt = task->packet;
1281 MppBuffer buf_in = mpp_frame_get_buffer(frm);
1282 MppBuffer buf_out = task->output;
1283 MppFrameFormat fmt = mpp_frame_get_fmt(frm);
1284 H264eVepu510Frame *reg_frm = ®s->reg_frm;
1285 RK_S32 hor_stride = mpp_frame_get_hor_stride(frm);
1286 RK_S32 ver_stride = mpp_frame_get_ver_stride(frm);
1287 RK_S32 fd_in = mpp_buffer_get_fd(buf_in);
1288 RK_U32 off_in[2] = {0};
1289 RK_U32 off_out = mpp_packet_get_length(pkt);
1290 size_t siz_out = mpp_buffer_get_size(buf_out);
1291 RK_S32 fd_out = mpp_buffer_get_fd(buf_out);
1292
1293 hal_h264e_dbg_func("enter\n");
1294
1295 reg_frm->common.adr_src0 = fd_in;
1296 reg_frm->common.adr_src1 = fd_in;
1297 reg_frm->common.adr_src2 = fd_in;
1298
1299 reg_frm->common.bsbt_addr = fd_out;
1300 reg_frm->common.bsbb_addr = fd_out;
1301 reg_frm->common.adr_bsbs = fd_out;
1302 reg_frm->common.bsbr_addr = fd_out;
1303
1304 reg_frm->common.rfpt_h_addr = 0xffffffff;
1305 reg_frm->common.rfpb_h_addr = 0;
1306 reg_frm->common.rfpt_b_addr = 0xffffffff;
1307 reg_frm->common.adr_rfpb_b = 0;
1308
1309 if (MPP_FRAME_FMT_IS_YUV(fmt)) {
1310 VepuFmtCfg cfg;
1311
1312 vepu5xx_set_fmt(&cfg, fmt);
1313 switch (cfg.format) {
1314 case VEPU5xx_FMT_BGRA8888 :
1315 case VEPU5xx_FMT_BGR888 :
1316 case VEPU5xx_FMT_BGR565 : {
1317 off_in[0] = 0;
1318 off_in[1] = 0;
1319 } break;
1320 case VEPU5xx_FMT_YUV420SP :
1321 case VEPU5xx_FMT_YUV422SP : {
1322 off_in[0] = hor_stride * ver_stride;
1323 off_in[1] = hor_stride * ver_stride;
1324 } break;
1325 case VEPU5xx_FMT_YUV422P : {
1326 off_in[0] = hor_stride * ver_stride;
1327 off_in[1] = hor_stride * ver_stride * 3 / 2;
1328 } break;
1329 case VEPU5xx_FMT_YUV420P : {
1330 off_in[0] = hor_stride * ver_stride;
1331 off_in[1] = hor_stride * ver_stride * 5 / 4;
1332 } break;
1333 case VEPU5xx_FMT_YUV400 :
1334 case VEPU5xx_FMT_YUYV422 :
1335 case VEPU5xx_FMT_UYVY422 : {
1336 off_in[0] = 0;
1337 off_in[1] = 0;
1338 } break;
1339 case VEPU5xx_FMT_YUV444SP : {
1340 off_in[0] = hor_stride * ver_stride;
1341 off_in[1] = hor_stride * ver_stride;
1342 } break;
1343 case VEPU5xx_FMT_YUV444P : {
1344 off_in[0] = hor_stride * ver_stride;
1345 off_in[1] = hor_stride * ver_stride * 2;
1346 } break;
1347 default : {
1348 off_in[0] = 0;
1349 off_in[1] = 0;
1350 } break;
1351 }
1352 }
1353
1354 mpp_dev_multi_offset_update(offsets, 161, off_in[0]);
1355 mpp_dev_multi_offset_update(offsets, 162, off_in[1]);
1356 mpp_dev_multi_offset_update(offsets, 172, siz_out);
1357 mpp_dev_multi_offset_update(offsets, 174, off_out);
1358
1359 hal_h264e_dbg_func("leave\n");
1360 }
1361
vepu510_h264_set_one_roi(void * buf,MppEncROIRegion * region,RK_S32 w,RK_S32 h)1362 static MPP_RET vepu510_h264_set_one_roi(void *buf, MppEncROIRegion *region, RK_S32 w, RK_S32 h)
1363 {
1364 Vepu510RoiH264BsCfg *ptr = (Vepu510RoiH264BsCfg *)buf;
1365 RK_S32 mb_w = MPP_ALIGN(w, 16) / 16;
1366 RK_S32 mb_h = MPP_ALIGN(h, 16) / 16;
1367 RK_S32 stride_h = MPP_ALIGN(mb_w, 4);
1368 Vepu510RoiH264BsCfg cfg;
1369 MPP_RET ret = MPP_NOK;
1370
1371 if (NULL == buf || NULL == region) {
1372 mpp_err_f("invalid buf %p roi %p\n", buf, region);
1373 goto DONE;
1374 }
1375
1376 RK_S32 roi_width = (region->w + 15) / 16;
1377 RK_S32 roi_height = (region->h + 15) / 16;
1378 RK_S32 pos_x_init = region->x / 16;
1379 RK_S32 pos_y_init = region->y / 16;
1380 RK_S32 pos_x_end = pos_x_init + roi_width;
1381 RK_S32 pos_y_end = pos_y_init + roi_height;
1382 RK_S32 x, y;
1383
1384 pos_x_end = MPP_MIN(pos_x_end, mb_w);
1385 pos_y_end = MPP_MIN(pos_y_end, mb_h);
1386 pos_x_init = MPP_MAX(pos_x_init, 0);
1387 pos_y_init = MPP_MAX(pos_y_init, 0);
1388
1389 mpp_assert(pos_x_end > pos_x_init);
1390 mpp_assert(pos_y_end > pos_y_init);
1391
1392 cfg.force_intra = 1;
1393
1394 ptr += pos_y_init * stride_h + pos_x_init;
1395 roi_width = pos_x_end - pos_x_init;
1396 roi_height = pos_y_end - pos_y_init;
1397
1398 for (y = 0; y < roi_height; y++) {
1399 Vepu510RoiH264BsCfg *dst = ptr;
1400
1401 for (x = 0; x < roi_width; x++, dst++)
1402 memcpy(dst, &cfg, sizeof(cfg));
1403
1404 ptr += stride_h;
1405 }
1406 DONE:
1407 return ret;
1408 }
1409
setup_vepu510_intra_refresh(HalVepu510RegSet * regs,HalH264eVepu510Ctx * ctx,RK_U32 refresh_idx)1410 static MPP_RET setup_vepu510_intra_refresh(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ctx, RK_U32 refresh_idx)
1411 {
1412 MPP_RET ret = MPP_OK;
1413 RK_U32 mb_w = ctx->sps->pic_width_in_mbs;
1414 RK_U32 mb_h = ctx->sps->pic_height_in_mbs;
1415 RK_U32 w = mb_w * 16;
1416 RK_U32 h = mb_h * 16;
1417 MppEncROIRegion *region = NULL;
1418 H264eVepu510Frame *reg_frm = ®s->reg_frm;
1419 RK_U32 refresh_num = ctx->cfg->rc.refresh_num;
1420 RK_U32 stride_h = MPP_ALIGN(mb_w, 4);
1421 RK_U32 stride_v = MPP_ALIGN(mb_h, 4);
1422 RK_U32 roir_buf_size = stride_h * stride_v * 8;
1423 RK_U32 i = 0;
1424
1425 hal_h264e_dbg_func("enter\n");
1426
1427 if (!ctx->cfg->rc.refresh_en) {
1428 ret = MPP_ERR_VALUE;
1429 goto RET;
1430 }
1431
1432 if (NULL == ctx->roir_buf) {
1433 if (NULL == ctx->roi_grp)
1434 mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
1435 mpp_buffer_get(ctx->roi_grp, &ctx->roir_buf, roir_buf_size);
1436 ctx->roir_buf_size = roir_buf_size;
1437 }
1438
1439 mpp_assert(ctx->roir_buf);
1440 void *base_cfg_buf = mpp_buffer_get_ptr(ctx->roir_buf);
1441 Vepu510RoiH264BsCfg base_cfg;
1442 Vepu510RoiH264BsCfg *base_cfg_ptr = (Vepu510RoiH264BsCfg *)base_cfg_buf;
1443
1444 base_cfg.force_intra = 0;
1445 base_cfg.qp_adj_en = 1;
1446
1447 for (i = 0; i < stride_h * stride_v; i++, base_cfg_ptr++)
1448 memcpy(base_cfg_ptr, &base_cfg, sizeof(base_cfg));
1449
1450 region = mpp_calloc(MppEncROIRegion, 1);
1451
1452 if (NULL == region) {
1453 mpp_err_f("Failed to calloc for MppEncROIRegion !\n");
1454 ret = MPP_ERR_MALLOC;
1455 }
1456
1457 if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_ROW) {
1458 region->x = 0;
1459 region->w = w;
1460 if (refresh_idx > 0) {
1461 region->y = refresh_idx * 16 * refresh_num - 32;
1462 region->h = 16 * refresh_num + 32;
1463 } else {
1464 region->y = refresh_idx * 16 * refresh_num;
1465 region->h = 16 * refresh_num;
1466 }
1467 reg_frm->common.me_rnge.cime_srch_uph = 1;
1468 } else if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_COL) {
1469 region->y = 0;
1470 region->h = h;
1471 if (refresh_idx > 0) {
1472 region->x = refresh_idx * 16 * refresh_num - 32;
1473 region->w = 16 * refresh_num + 32;
1474 } else {
1475 region->x = refresh_idx * 16 * refresh_num;
1476 region->w = 16 * refresh_num;
1477 }
1478 reg_frm->common.me_rnge.cime_srch_dwnh = 1;
1479 }
1480
1481 region->intra = 1;
1482 region->quality = -ctx->cfg->rc.qp_delta_ip;
1483
1484 region->area_map_en = 1;
1485 region->qp_area_idx = 1;
1486 region->abs_qp_en = 0;
1487
1488 vepu510_h264_set_one_roi(base_cfg_buf, region, w, h);
1489 mpp_free(region);
1490 RET:
1491 hal_h264e_dbg_func("leave, ret %d\n", ret);
1492 return ret;
1493 }
1494
setup_vepu510_recn_refr(HalH264eVepu510Ctx * ctx,HalVepu510RegSet * regs)1495 static void setup_vepu510_recn_refr(HalH264eVepu510Ctx *ctx, HalVepu510RegSet *regs)
1496 {
1497
1498 H264eVepu510Frame *reg_frm = ®s->reg_frm;
1499 H264eFrmInfo *frms = ctx->frms;
1500 HalBufs bufs = ctx->hw_recn;
1501 RK_S32 fbc_hdr_size = ctx->pixel_buf_fbc_hdr_size;
1502
1503 HalBuf *curr = hal_bufs_get_buf(bufs, frms->curr_idx);
1504 HalBuf *refr = hal_bufs_get_buf(bufs, frms->refr_idx);
1505
1506 hal_h264e_dbg_func("enter\n");
1507
1508 if (curr && curr->cnt) {
1509 MppBuffer buf_pixel = curr->buf[0];
1510 MppBuffer buf_thumb = curr->buf[1];
1511 MppBuffer buf_smear = curr->buf[2];
1512 RK_S32 fd = mpp_buffer_get_fd(buf_pixel);
1513
1514 mpp_assert(buf_pixel);
1515 mpp_assert(buf_thumb);
1516
1517 reg_frm->common.rfpw_h_addr = fd;
1518 reg_frm->common.rfpw_b_addr = fd;
1519 reg_frm->common.dspw_addr = mpp_buffer_get_fd(buf_thumb);
1520 reg_frm->common.adr_smear_wr = mpp_buffer_get_fd(buf_smear);
1521 }
1522
1523 if (refr && refr->cnt) {
1524 MppBuffer buf_pixel = refr->buf[0];
1525 MppBuffer buf_thumb = refr->buf[1];
1526 MppBuffer buf_smear = refr->buf[2];
1527 RK_S32 fd = mpp_buffer_get_fd(buf_pixel);
1528
1529 mpp_assert(buf_pixel);
1530 mpp_assert(buf_thumb);
1531
1532 reg_frm->common.rfpr_h_addr = fd;
1533 reg_frm->common.rfpr_b_addr = fd;
1534 reg_frm->common.dspr_addr = mpp_buffer_get_fd(buf_thumb);
1535 reg_frm->common.adr_smear_rd = mpp_buffer_get_fd(buf_smear);
1536 }
1537 mpp_dev_multi_offset_update(ctx->offsets, 164, fbc_hdr_size);
1538 mpp_dev_multi_offset_update(ctx->offsets, 166, fbc_hdr_size);
1539
1540 hal_h264e_dbg_func("leave\n");
1541 }
1542
setup_vepu510_split(HalVepu510RegSet * regs,MppEncCfgSet * enc_cfg)1543 static void setup_vepu510_split(HalVepu510RegSet *regs, MppEncCfgSet *enc_cfg)
1544 {
1545 H264eVepu510Frame *reg_frm = ®s->reg_frm;
1546 MppEncSliceSplit *cfg = &enc_cfg->split;
1547
1548 hal_h264e_dbg_func("enter\n");
1549
1550 switch (cfg->split_mode) {
1551 case MPP_ENC_SPLIT_NONE : {
1552 reg_frm->common.sli_splt.sli_splt = 0;
1553 reg_frm->common.sli_splt.sli_splt_mode = 0;
1554 reg_frm->common.sli_splt.sli_splt_cpst = 0;
1555 reg_frm->common.sli_splt.sli_max_num_m1 = 0;
1556 reg_frm->common.sli_splt.sli_flsh = 0;
1557 reg_frm->common.sli_cnum.sli_splt_cnum_m1 = 0;
1558
1559 reg_frm->common.sli_byte.sli_splt_byte = 0;
1560 reg_frm->common.enc_pic.slen_fifo = 0;
1561 } break;
1562 case MPP_ENC_SPLIT_BY_BYTE : {
1563 reg_frm->common.sli_splt.sli_splt = 1;
1564 reg_frm->common.sli_splt.sli_splt_mode = 0;
1565 reg_frm->common.sli_splt.sli_splt_cpst = 0;
1566 reg_frm->common.sli_splt.sli_max_num_m1 = 500;
1567 reg_frm->common.sli_splt.sli_flsh = 1;
1568 reg_frm->common.sli_cnum.sli_splt_cnum_m1 = 0;
1569
1570 reg_frm->common.sli_byte.sli_splt_byte = cfg->split_arg;
1571 reg_frm->common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
1572 regs->reg_ctl.int_en.vslc_done_en = reg_frm->common.enc_pic.slen_fifo;
1573 } break;
1574 case MPP_ENC_SPLIT_BY_CTU : {
1575 RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 16) / 16;
1576 RK_U32 mb_h = MPP_ALIGN(enc_cfg->prep.height, 16) / 16;
1577 RK_U32 slice_num = (mb_w * mb_h + cfg->split_arg - 1) / cfg->split_arg;
1578
1579 reg_frm->common.sli_splt.sli_splt = 1;
1580 reg_frm->common.sli_splt.sli_splt_mode = 1;
1581 reg_frm->common.sli_splt.sli_splt_cpst = 0;
1582 reg_frm->common.sli_splt.sli_max_num_m1 = 500;
1583 reg_frm->common.sli_splt.sli_flsh = 1;
1584 reg_frm->common.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1;
1585
1586 reg_frm->common.sli_byte.sli_splt_byte = 0;
1587 reg_frm->common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
1588 if ((cfg->split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) ||
1589 (regs->reg_frm.common.enc_pic.slen_fifo && (slice_num > VEPU510_SLICE_FIFO_LEN)))
1590 regs->reg_ctl.int_en.vslc_done_en = 1;
1591 } break;
1592 default : {
1593 mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
1594 } break;
1595 }
1596
1597 hal_h264e_dbg_func("leave\n");
1598 }
1599
setup_vepu510_me(HalH264eVepu510Ctx * ctx)1600 static void setup_vepu510_me(HalH264eVepu510Ctx *ctx)
1601 {
1602 HalVepu510RegSet *regs = ctx->regs_set;
1603 H264eVepu510Frame *reg_frm = ®s->reg_frm;
1604 H264eVepu510Param *reg_param = ®s->reg_param;
1605 MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
1606
1607 hal_h264e_dbg_func("enter\n");
1608
1609 reg_frm->common.me_rnge.cime_srch_dwnh = 15;
1610 reg_frm->common.me_rnge.cime_srch_uph = 15;
1611 reg_frm->common.me_rnge.cime_srch_rgtw = 12;
1612 reg_frm->common.me_rnge.cime_srch_lftw = 12;
1613 reg_frm->common.me_cfg.rme_srch_h = 3;
1614 reg_frm->common.me_cfg.rme_srch_v = 3;
1615
1616 reg_frm->common.me_cfg.srgn_max_num = 54;
1617 reg_frm->common.me_cfg.cime_dist_thre = 1024;
1618 reg_frm->common.me_cfg.rme_dis = 0;
1619 reg_frm->common.me_cfg.fme_dis = 0;
1620 reg_frm->common.me_rnge.dlt_frm_num = 0x0;
1621 reg_frm->common.me_cach.cime_zero_thre = 64;
1622
1623 /* CIME: 0x1760 - 0x176C */
1624 reg_param->me_sqi_comb.cime_pmv_num = 1;
1625 reg_param->me_sqi_comb.cime_fuse = 1;
1626 reg_param->me_sqi_comb.itp_mode = 0;
1627 reg_param->me_sqi_comb.move_lambda = 0;
1628 reg_param->me_sqi_comb.rime_lvl_mrg = 1;
1629 reg_param->me_sqi_comb.rime_prelvl_en = 0;
1630 reg_param->me_sqi_comb.rime_prersu_en = 0;
1631 reg_param->cime_mvd_th_comb.cime_mvd_th0 = 16;
1632 reg_param->cime_mvd_th_comb.cime_mvd_th1 = 48;
1633 reg_param->cime_mvd_th_comb.cime_mvd_th2 = 80;
1634 reg_param->cime_madp_th_comb.cime_madp_th = 16;
1635 reg_param->cime_multi_comb.cime_multi0 = 8;
1636 reg_param->cime_multi_comb.cime_multi1 = 12;
1637 reg_param->cime_multi_comb.cime_multi2 = 16;
1638 reg_param->cime_multi_comb.cime_multi3 = 20;
1639
1640 /* RFME: 0x1770 - 0x1778 */
1641 reg_param->rime_mvd_th_comb.rime_mvd_th0 = 1;
1642 reg_param->rime_mvd_th_comb.rime_mvd_th1 = 2;
1643 reg_param->rime_mvd_th_comb.fme_madp_th = 0;
1644 reg_param->rime_madp_th_comb.rime_madp_th0 = 8;
1645 reg_param->rime_madp_th_comb.rime_madp_th1 = 16;
1646 reg_param->rime_multi_comb.rime_multi0 = 4;
1647 reg_param->rime_multi_comb.rime_multi1 = 8;
1648 reg_param->rime_multi_comb.rime_multi2 = 12;
1649 reg_param->cmv_st_th_comb.cmv_th0 = 64;
1650 reg_param->cmv_st_th_comb.cmv_th1 = 96;
1651 reg_param->cmv_st_th_comb.cmv_th2 = 128;
1652
1653 if (sm != MPP_ENC_SCENE_MODE_IPC) {
1654 /* disable subjective optimization */
1655 reg_param->cime_madp_th_comb.cime_madp_th = 0;
1656 reg_param->rime_madp_th_comb.rime_madp_th0 = 0;
1657 reg_param->rime_madp_th_comb.rime_madp_th1 = 0;
1658 reg_param->cime_multi_comb.cime_multi0 = 4;
1659 reg_param->cime_multi_comb.cime_multi1 = 4;
1660 reg_param->cime_multi_comb.cime_multi2 = 4;
1661 reg_param->cime_multi_comb.cime_multi3 = 4;
1662 reg_param->rime_multi_comb.rime_multi0 = 4;
1663 reg_param->rime_multi_comb.rime_multi1 = 4;
1664 reg_param->rime_multi_comb.rime_multi2 = 4;
1665 }
1666
1667 /* 0x1064 */
1668 regs->reg_rc_roi.madi_st_thd.madi_th0 = 5;
1669 regs->reg_rc_roi.madi_st_thd.madi_th1 = 12;
1670 regs->reg_rc_roi.madi_st_thd.madi_th2 = 20;
1671 /* 0x1068 */
1672 regs->reg_rc_roi.madp_st_thd0.madp_th0 = 4 << 4;
1673 regs->reg_rc_roi.madp_st_thd0.madp_th1 = 9 << 4;
1674 /* 0x106C */
1675 regs->reg_rc_roi.madp_st_thd1.madp_th2 = 15 << 4;
1676
1677 hal_h264e_dbg_func("leave\n");
1678 }
1679
1680 #define H264E_LAMBDA_TAB_SIZE (52 * sizeof(RK_U32))
1681
1682 static RK_U32 h264e_lambda_default[60] = {
1683 0x00000005, 0x00000006, 0x00000007, 0x00000009,
1684 0x0000000b, 0x0000000e, 0x00000012, 0x00000016,
1685 0x0000001c, 0x00000024, 0x0000002d, 0x00000039,
1686 0x00000048, 0x0000005b, 0x00000073, 0x00000091,
1687 0x000000b6, 0x000000e6, 0x00000122, 0x0000016d,
1688 0x000001cc, 0x00000244, 0x000002db, 0x00000399,
1689 0x00000489, 0x000005b6, 0x00000733, 0x00000912,
1690 0x00000b6d, 0x00000e66, 0x00001224, 0x000016db,
1691 0x00001ccc, 0x00002449, 0x00002db7, 0x00003999,
1692 0x00004892, 0x00005b6f, 0x00007333, 0x00009124,
1693 0x0000b6de, 0x0000e666, 0x00012249, 0x00016dbc,
1694 0x0001cccc, 0x00024492, 0x0002db79, 0x00039999,
1695 0x00048924, 0x0005b6f2, 0x00073333, 0x00091249,
1696 0x000b6de5, 0x000e6666, 0x00122492, 0x0016dbcb,
1697 0x001ccccc, 0x00244924, 0x002db796, 0x00399998,
1698 };
1699
1700 static RK_U32 h264e_lambda_cvr[60] = {
1701 0x00000009, 0x0000000b, 0x0000000e, 0x00000011,
1702 0x00000016, 0x0000001b, 0x00000022, 0x0000002b,
1703 0x00000036, 0x00000045, 0x00000056, 0x0000006d,
1704 0x00000089, 0x000000ad, 0x000000da, 0x00000112,
1705 0x00000159, 0x000001b3, 0x00000224, 0x000002b3,
1706 0x00000366, 0x00000449, 0x00000566, 0x000006cd,
1707 0x00000891, 0x00000acb, 0x00000d9a, 0x000013c1,
1708 0x000018e4, 0x00001f5c, 0x00002783, 0x000031c8,
1709 0x00003eb8, 0x00004f06, 0x00006390, 0x00008e14,
1710 0x0000b302, 0x0000e18a, 0x00011c29, 0x00016605,
1711 0x0001c313, 0x00027ae1, 0x00031fe6, 0x0003efcf,
1712 0x0004f5c3, 0x0006e785, 0x0008b2ef, 0x000af5c3,
1713 0x000f1e7a, 0x00130c7f, 0x00180000, 0x001e3cf4,
1714 0x002618fe, 0x00300000, 0x003c79e8, 0x004c31fc,
1715 0x00600000, 0x0078f3d0, 0x009863f8, 0x0c000000,
1716 };
1717
1718 static void
setup_vepu510_l2(HalH264eVepu510Ctx * ctx,MppEncHwCfg * hw)1719 setup_vepu510_l2(HalH264eVepu510Ctx *ctx, MppEncHwCfg *hw)
1720 {
1721 HalVepu510RegSet *regs = ctx->regs_set;
1722 MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
1723 RK_S32 lambda_idx = ctx->cfg->tune.lambda_idx_i; //TODO: lambda_idx_p
1724
1725 hal_h264e_dbg_func("enter\n");
1726
1727 if (sm == MPP_ENC_SCENE_MODE_IPC) {
1728 memcpy(regs->reg_param.rdo_wgta_qp_grpa_0_51,
1729 &h264e_lambda_default[lambda_idx], H264E_LAMBDA_TAB_SIZE);
1730 } else {
1731 memcpy(regs->reg_param.rdo_wgta_qp_grpa_0_51,
1732 &h264e_lambda_cvr[lambda_idx], H264E_LAMBDA_TAB_SIZE);
1733 }
1734
1735 if (hw->qbias_en) {
1736 regs->reg_param.qnt_bias_comb.qnt_f_bias_i = hw->qbias_i;
1737 regs->reg_param.qnt_bias_comb.qnt_f_bias_p = hw->qbias_p;
1738 } else {
1739 regs->reg_param.qnt_bias_comb.qnt_f_bias_i = 683;
1740 regs->reg_param.qnt_bias_comb.qnt_f_bias_p = 341;
1741 }
1742
1743 hal_h264e_dbg_func("leave\n");
1744 }
1745
setup_vepu510_ext_line_buf(HalVepu510RegSet * regs,HalH264eVepu510Ctx * ctx)1746 static void setup_vepu510_ext_line_buf(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ctx)
1747 {
1748 H264eVepu510Frame *reg_frm = ®s->reg_frm;
1749 MppDevRcbInfoCfg rcb_cfg;
1750 RK_S32 offset = 0;
1751 RK_S32 fd;
1752
1753 if (!ctx->ext_line_buf) {
1754 reg_frm->common.ebufb_addr = 0;
1755 reg_frm->common.ebufb_addr = 0;
1756 return;
1757 }
1758
1759 fd = mpp_buffer_get_fd(ctx->ext_line_buf);
1760 offset = ctx->ext_line_buf_size;
1761
1762 reg_frm->common.ebuft_addr = fd;
1763 reg_frm->common.ebufb_addr = fd;
1764
1765 mpp_dev_multi_offset_update(ctx->offsets, 178, offset);
1766
1767 /* rcb info for sram */
1768 rcb_cfg.reg_idx = 179;
1769 rcb_cfg.size = offset;
1770
1771 mpp_dev_ioctl(ctx->dev, MPP_DEV_RCB_INFO, &rcb_cfg);
1772
1773 rcb_cfg.reg_idx = 178;
1774 rcb_cfg.size = 0;
1775
1776 mpp_dev_ioctl(ctx->dev, MPP_DEV_RCB_INFO, &rcb_cfg);
1777 }
1778
setup_vepu510_dual_core(HalH264eVepu510Ctx * ctx,H264SliceType slice_type)1779 static MPP_RET setup_vepu510_dual_core(HalH264eVepu510Ctx *ctx, H264SliceType slice_type)
1780 {
1781 H264eVepu510Frame *reg_frm = &ctx->regs_set->reg_frm;
1782 RK_U32 dchs_ofst = 9;
1783 RK_U32 dchs_rxe = 1;
1784 RK_U32 dchs_dly = 0;
1785
1786 if (ctx->task_cnt == 1)
1787 return MPP_OK;
1788
1789 if (slice_type == H264_I_SLICE) {
1790 ctx->curr_idx = 0;
1791 ctx->prev_idx = 0;
1792 dchs_rxe = 0;
1793 }
1794
1795 reg_frm->common.dual_core.dchs_txid = ctx->curr_idx;
1796 reg_frm->common.dual_core.dchs_rxid = ctx->prev_idx;
1797 reg_frm->common.dual_core.dchs_txe = 1;
1798 reg_frm->common.dual_core.dchs_rxe = dchs_rxe;
1799 reg_frm->common.dual_core.dchs_ofst = dchs_ofst;
1800 reg_frm->common.dual_core.dchs_dly = dchs_dly;
1801
1802 ctx->prev_idx = ctx->curr_idx++;
1803 if (ctx->curr_idx > 3)
1804 ctx->curr_idx = 0;
1805
1806 return MPP_OK;
1807 }
1808
setup_vepu510_aq(HalH264eVepu510Ctx * ctx)1809 static void setup_vepu510_aq(HalH264eVepu510Ctx *ctx)
1810 {
1811 MppEncCfgSet *cfg = ctx->cfg;
1812 MppEncHwCfg *hw = &cfg->hw;
1813 Vepu510RcRoi *s = &ctx->regs_set->reg_rc_roi;
1814 RK_S32 *aq_step, *aq_thd;
1815 RK_U8 i;
1816
1817 if (ctx->slice->slice_type == H264_I_SLICE) {
1818 aq_thd = (RK_S32 *)&hw->aq_thrd_i[0];
1819 aq_step = &hw->aq_step_i[0];
1820 } else {
1821 aq_thd = (RK_S32 *)&hw->aq_thrd_p[0];
1822 aq_step = &hw->aq_step_p[0];
1823 }
1824
1825 for (i = 0; i < 16; i++)
1826 s->aq_tthd[i] = aq_thd[i] & 0xff;
1827
1828 s->aq_stp0.aq_stp_s0 = aq_step[0] & 0x1f;
1829 s->aq_stp0.aq_stp_0t1 = aq_step[1] & 0x1f;
1830 s->aq_stp0.aq_stp_1t2 = aq_step[2] & 0x1f;
1831 s->aq_stp0.aq_stp_2t3 = aq_step[3] & 0x1f;
1832 s->aq_stp0.aq_stp_3t4 = aq_step[4] & 0x1f;
1833 s->aq_stp0.aq_stp_4t5 = aq_step[5] & 0x1f;
1834 s->aq_stp1.aq_stp_5t6 = aq_step[6] & 0x1f;
1835 s->aq_stp1.aq_stp_6t7 = aq_step[7] & 0x1f;
1836 s->aq_stp1.aq_stp_7t8 = 0;
1837 s->aq_stp1.aq_stp_8t9 = aq_step[8] & 0x1f;
1838 s->aq_stp1.aq_stp_9t10 = aq_step[9] & 0x1f;
1839 s->aq_stp1.aq_stp_10t11 = aq_step[10] & 0x1f;
1840 s->aq_stp2.aq_stp_11t12 = aq_step[11] & 0x1f;
1841 s->aq_stp2.aq_stp_12t13 = aq_step[12] & 0x1f;
1842 s->aq_stp2.aq_stp_13t14 = aq_step[13] & 0x1f;
1843 s->aq_stp2.aq_stp_14t15 = aq_step[14] & 0x1f;
1844 s->aq_stp2.aq_stp_b15 = aq_step[15] & 0x1f;
1845 }
1846
setup_vepu510_anti_stripe(HalH264eVepu510Ctx * ctx)1847 static void setup_vepu510_anti_stripe(HalH264eVepu510Ctx *ctx)
1848 {
1849 HalVepu510RegSet *regs = ctx->regs_set;
1850 H264eVepu510Param *s = ®s->reg_param;
1851 RK_S32 str = ctx->cfg->tune.atl_str;
1852
1853 s->iprd_tthdy4_0.iprd_tthdy4_0 = 1;
1854 s->iprd_tthdy4_0.iprd_tthdy4_1 = 3;
1855 s->iprd_tthdy4_1.iprd_tthdy4_2 = 6;
1856 s->iprd_tthdy4_1.iprd_tthdy4_3 = 8;
1857 s->iprd_tthdc8_0.iprd_tthdc8_0 = 1;
1858 s->iprd_tthdc8_0.iprd_tthdc8_1 = 3;
1859 s->iprd_tthdc8_1.iprd_tthdc8_2 = 6;
1860 s->iprd_tthdc8_1.iprd_tthdc8_3 = 8;
1861 s->iprd_tthdy8_0.iprd_tthdy8_0 = 1;
1862 s->iprd_tthdy8_0.iprd_tthdy8_1 = 3;
1863 s->iprd_tthdy8_1.iprd_tthdy8_2 = 6;
1864 s->iprd_tthdy8_1.iprd_tthdy8_3 = 8;
1865
1866 if (ctx->cfg->tune.scene_mode != MPP_ENC_SCENE_MODE_IPC)
1867 s->iprd_tthd_ul.iprd_tthd_ul = 4095; /* disable anti-stripe */
1868 else
1869 s->iprd_tthd_ul.iprd_tthd_ul = str ? 4 : 255;
1870
1871 s->iprd_wgty8.iprd_wgty8_0 = str ? 22 : 16;
1872 s->iprd_wgty8.iprd_wgty8_1 = str ? 23 : 16;
1873 s->iprd_wgty8.iprd_wgty8_2 = str ? 20 : 16;
1874 s->iprd_wgty8.iprd_wgty8_3 = str ? 22 : 16;
1875 s->iprd_wgty4.iprd_wgty4_0 = str ? 22 : 16;
1876 s->iprd_wgty4.iprd_wgty4_1 = str ? 26 : 16;
1877 s->iprd_wgty4.iprd_wgty4_2 = str ? 20 : 16;
1878 s->iprd_wgty4.iprd_wgty4_3 = str ? 22 : 16;
1879 s->iprd_wgty16.iprd_wgty16_0 = 22;
1880 s->iprd_wgty16.iprd_wgty16_1 = 26;
1881 s->iprd_wgty16.iprd_wgty16_2 = 20;
1882 s->iprd_wgty16.iprd_wgty16_3 = 22;
1883 s->iprd_wgtc8.iprd_wgtc8_0 = 18;
1884 s->iprd_wgtc8.iprd_wgtc8_1 = 21;
1885 s->iprd_wgtc8.iprd_wgtc8_2 = 20;
1886 s->iprd_wgtc8.iprd_wgtc8_3 = 19;
1887 }
1888
setup_vepu510_anti_ringing(HalH264eVepu510Ctx * ctx)1889 static void setup_vepu510_anti_ringing(HalH264eVepu510Ctx *ctx)
1890 {
1891 HalVepu510RegSet *regs = ctx->regs_set;
1892 H264eVepu510Param *s = ®s->reg_param;
1893 MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
1894
1895 s->atr_thd1.thdqp = (sm == MPP_ENC_SCENE_MODE_IPC) ? 32 : 45;
1896 if (ctx->slice->slice_type == H264_I_SLICE) {
1897 s->atr_thd0.thd0 = 1;
1898 s->atr_thd0.thd1 = 2;
1899 s->atr_thd1.thd2 = 6;
1900 s->atr_wgt16.atr_lv16_wgt0 = 16;
1901 s->atr_wgt16.atr_lv16_wgt1 = 16;
1902 s->atr_wgt16.atr_lv16_wgt2 = 16;
1903
1904 if (sm == MPP_ENC_SCENE_MODE_IPC) {
1905 s->atr_wgt8.atr_lv8_wgt0 = 22;
1906 s->atr_wgt8.atr_lv8_wgt1 = 21;
1907 s->atr_wgt8.atr_lv8_wgt2 = 20;
1908 s->atr_wgt4.atr_lv4_wgt0 = 20;
1909 s->atr_wgt4.atr_lv4_wgt1 = 18;
1910 s->atr_wgt4.atr_lv4_wgt2 = 16;
1911 } else {
1912 s->atr_wgt8.atr_lv8_wgt0 = 18;
1913 s->atr_wgt8.atr_lv8_wgt1 = 17;
1914 s->atr_wgt8.atr_lv8_wgt2 = 18;
1915 s->atr_wgt4.atr_lv4_wgt0 = 16;
1916 s->atr_wgt4.atr_lv4_wgt1 = 16;
1917 s->atr_wgt4.atr_lv4_wgt2 = 16;
1918 }
1919 } else {
1920 if (sm == MPP_ENC_SCENE_MODE_IPC) {
1921 s->atr_thd0.thd0 = 2;
1922 s->atr_thd0.thd1 = 4;
1923 s->atr_thd1.thd2 = 9;
1924 s->atr_wgt16.atr_lv16_wgt0 = 25;
1925 s->atr_wgt16.atr_lv16_wgt1 = 20;
1926 s->atr_wgt16.atr_lv16_wgt2 = 16;
1927 s->atr_wgt8.atr_lv8_wgt0 = 25;
1928 s->atr_wgt8.atr_lv8_wgt1 = 20;
1929 s->atr_wgt8.atr_lv8_wgt2 = 18;
1930 s->atr_wgt4.atr_lv4_wgt0 = 25;
1931 s->atr_wgt4.atr_lv4_wgt1 = 20;
1932 s->atr_wgt4.atr_lv4_wgt2 = 16;
1933 } else {
1934 s->atr_thd0.thd0 = 1;
1935 s->atr_thd0.thd1 = 2;
1936 s->atr_thd1.thd2 = 7;
1937 s->atr_wgt16.atr_lv16_wgt0 = 23;
1938 s->atr_wgt16.atr_lv16_wgt1 = 22;
1939 s->atr_wgt16.atr_lv16_wgt2 = 20;
1940 s->atr_wgt8.atr_lv8_wgt0 = 24;
1941 s->atr_wgt8.atr_lv8_wgt1 = 24;
1942 s->atr_wgt8.atr_lv8_wgt2 = 24;
1943 s->atr_wgt4.atr_lv4_wgt0 = 23;
1944 s->atr_wgt4.atr_lv4_wgt1 = 22;
1945 s->atr_wgt4.atr_lv4_wgt2 = 20;
1946 }
1947 }
1948 }
1949
setup_vepu510_anti_flicker(HalH264eVepu510Ctx * ctx)1950 static void setup_vepu510_anti_flicker(HalH264eVepu510Ctx *ctx)
1951 {
1952 HalVepu510RegSet *regs = ctx->regs_set;
1953 H264eVepu510Sqi *reg = ®s->reg_sqi;
1954 RK_U32 str = ctx->cfg->tune.anti_flicker_str;
1955 rdo_skip_par *p_skip = NULL;
1956 rdo_noskip_par *p_no_skip = NULL;
1957
1958 static RK_U8 pskip_atf_th0[4] = { 0, 0, 0, 1 };
1959 static RK_U8 pskip_atf_th1[4] = { 7, 7, 7, 10 };
1960 static RK_U8 pskip_atf_wgt0[4] = { 16, 16, 16, 20 };
1961 static RK_U8 pskip_atf_wgt1[4] = { 16, 16, 14, 16 };
1962 static RK_U8 intra_atf_th0[4] = { 8, 16, 20, 20 };
1963 static RK_U8 intra_atf_th1[4] = { 16, 32, 40, 40 };
1964 static RK_U8 intra_atf_th2[4] = { 32, 56, 72, 72 };
1965 static RK_U8 intra_atf_wgt0[4] = { 16, 24, 27, 27 };
1966 static RK_U8 intra_atf_wgt1[4] = { 16, 22, 25, 25 };
1967 static RK_U8 intra_atf_wgt2[4] = { 16, 19, 20, 20 };
1968
1969 p_skip = ®->rdo_b16_skip;
1970 p_skip->atf_thd0.madp_thd0 = pskip_atf_th0[str];
1971 p_skip->atf_thd0.madp_thd1 = pskip_atf_th1[str];
1972 p_skip->atf_thd1.madp_thd2 = 15;
1973 p_skip->atf_thd1.madp_thd3 = 25;
1974 p_skip->atf_wgt0.wgt0 = pskip_atf_wgt0[str];
1975 p_skip->atf_wgt0.wgt1 = pskip_atf_wgt1[str];
1976 p_skip->atf_wgt0.wgt2 = 16;
1977 p_skip->atf_wgt0.wgt3 = 16;
1978 p_skip->atf_wgt1.wgt4 = 16;
1979
1980 p_no_skip = ®->rdo_b16_inter;
1981 p_no_skip->ratf_thd0.madp_thd0 = 20;
1982 p_no_skip->ratf_thd0.madp_thd1 = 40;
1983 p_no_skip->ratf_thd1.madp_thd2 = 72;
1984 p_no_skip->atf_wgt.wgt0 = 16;
1985 p_no_skip->atf_wgt.wgt1 = 16;
1986 p_no_skip->atf_wgt.wgt2 = 16;
1987 p_no_skip->atf_wgt.wgt3 = 16;
1988
1989 p_no_skip = ®->rdo_b16_intra;
1990 p_no_skip->ratf_thd0.madp_thd0 = intra_atf_th0[str];
1991 p_no_skip->ratf_thd0.madp_thd1 = intra_atf_th1[str];
1992 p_no_skip->ratf_thd1.madp_thd2 = intra_atf_th2[str];
1993 p_no_skip->atf_wgt.wgt0 = intra_atf_wgt0[str];
1994 p_no_skip->atf_wgt.wgt1 = intra_atf_wgt1[str];
1995 p_no_skip->atf_wgt.wgt2 = intra_atf_wgt2[str];
1996 p_no_skip->atf_wgt.wgt3 = 16;
1997
1998 reg->rdo_b16_intra_atf_cnt_thd.thd0 = 1;
1999 reg->rdo_b16_intra_atf_cnt_thd.thd1 = 4;
2000 reg->rdo_b16_intra_atf_cnt_thd.thd2 = 1;
2001 reg->rdo_b16_intra_atf_cnt_thd.thd3 = 4;
2002
2003 reg->rdo_atf_resi_thd.big_th0 = 16;
2004 reg->rdo_atf_resi_thd.big_th1 = 16;
2005 reg->rdo_atf_resi_thd.small_th0 = 8;
2006 reg->rdo_atf_resi_thd.small_th1 = 8;
2007 }
2008
setup_vepu510_anti_smear(HalH264eVepu510Ctx * ctx)2009 static void setup_vepu510_anti_smear(HalH264eVepu510Ctx *ctx)
2010 {
2011 HalVepu510RegSet *regs = ctx->regs_set;
2012 H264eVepu510Sqi *reg = ®s->reg_sqi;
2013 H264eSlice *slice = ctx->slice;
2014 Vepu510H264Fbk *last_fb = &ctx->last_frame_fb;
2015 RK_U32 mb_cnt = last_fb->st_mb_num;
2016 RK_U32 *smear_cnt = last_fb->st_smear_cnt;
2017 RK_S32 deblur_str = ctx->cfg->tune.deblur_str;
2018 RK_S32 delta_qp = 0;
2019 RK_S32 flg0 = smear_cnt[4] < (mb_cnt >> 6);
2020 RK_S32 flg1 = 1, flg2 = 0, flg3 = 0;
2021 RK_S32 smear_multi[4] = { 9, 12, 16, 16 };
2022
2023 hal_h264e_dbg_func("enter\n");
2024
2025 if ((smear_cnt[3] < ((5 * mb_cnt) >> 10)) ||
2026 (smear_cnt[3] < ((1126 * MPP_MAX3(smear_cnt[0], smear_cnt[1], smear_cnt[2])) >> 10)) ||
2027 (deblur_str == 6) || (deblur_str == 7))
2028 flg1 = 0;
2029
2030 flg3 = flg1 ? 3 : (smear_cnt[4] > ((102 * mb_cnt) >> 10)) ? 2 :
2031 (smear_cnt[4] > ((66 * mb_cnt) >> 10)) ? 1 : 0;
2032
2033 if (ctx->cfg->tune.scene_mode == MPP_ENC_SCENE_MODE_IPC) {
2034 reg->smear_opt_cfg.rdo_smear_en = ctx->qpmap_en;
2035 if (ctx->qpmap_en && deblur_str > 3)
2036 reg->smear_opt_cfg.rdo_smear_lvl16_multi = smear_multi[flg3];
2037 else
2038 reg->smear_opt_cfg.rdo_smear_lvl16_multi = flg0 ? 9 : 12;
2039 } else {
2040 reg->smear_opt_cfg.rdo_smear_en = 0;
2041 reg->smear_opt_cfg.rdo_smear_lvl16_multi = 16;
2042 }
2043
2044 if (ctx->qpmap_en && deblur_str > 3) {
2045 flg2 = 1;
2046 if (smear_cnt[2] + smear_cnt[3] > (3 * smear_cnt[4] / 4))
2047 delta_qp = 1;
2048 if (smear_cnt[4] < (mb_cnt >> 4))
2049 delta_qp -= 8;
2050 else if (smear_cnt[4] < ((3 * mb_cnt) >> 5))
2051 delta_qp -= 7;
2052 else
2053 delta_qp -= 6;
2054
2055 if (flg3 == 2)
2056 delta_qp = 0;
2057 else if (flg3 == 1)
2058 delta_qp = -2;
2059 } else {
2060 if (smear_cnt[2] + smear_cnt[3] > smear_cnt[4] / 2)
2061 delta_qp = 1;
2062 if (smear_cnt[4] < (mb_cnt >> 8))
2063 delta_qp -= (deblur_str < 2) ? 6 : 8;
2064 else if (smear_cnt[4] < (mb_cnt >> 7))
2065 delta_qp -= (deblur_str < 2) ? 5 : 6;
2066 else if (smear_cnt[4] < (mb_cnt >> 6))
2067 delta_qp -= (deblur_str < 2) ? 3 : 4;
2068 else
2069 delta_qp -= 1;
2070 }
2071 reg->smear_opt_cfg.rdo_smear_dlt_qp = delta_qp;
2072
2073 if ((H264_I_SLICE == slice->slice_type) ||
2074 (H264_I_SLICE == last_fb->frame_type))
2075 reg->smear_opt_cfg.stated_mode = 1;
2076 else
2077 reg->smear_opt_cfg.stated_mode = 2;
2078
2079 reg->smear_madp_thd0.madp_cur_thd0 = 0;
2080 reg->smear_madp_thd0.madp_cur_thd1 = flg2 ? 48 : 24;
2081 reg->smear_madp_thd1.madp_cur_thd2 = flg2 ? 64 : 48;
2082 reg->smear_madp_thd1.madp_cur_thd3 = flg2 ? 72 : 64;
2083 reg->smear_madp_thd2.madp_around_thd0 = flg2 ? 4095 : 16;
2084 reg->smear_madp_thd2.madp_around_thd1 = 32;
2085 reg->smear_madp_thd3.madp_around_thd2 = 48;
2086 reg->smear_madp_thd3.madp_around_thd3 = flg2 ? 0 : 96;
2087 reg->smear_madp_thd4.madp_around_thd4 = 48;
2088 reg->smear_madp_thd4.madp_around_thd5 = 24;
2089 reg->smear_madp_thd5.madp_ref_thd0 = flg2 ? 64 : 96;
2090 reg->smear_madp_thd5.madp_ref_thd1 = 48;
2091
2092 reg->smear_cnt_thd0.cnt_cur_thd0 = flg2 ? 2 : 1;
2093 reg->smear_cnt_thd0.cnt_cur_thd1 = flg2 ? 5 : 3;
2094 reg->smear_cnt_thd0.cnt_cur_thd2 = 1;
2095 reg->smear_cnt_thd0.cnt_cur_thd3 = 3;
2096 reg->smear_cnt_thd1.cnt_around_thd0 = 1;
2097 reg->smear_cnt_thd1.cnt_around_thd1 = 4;
2098 reg->smear_cnt_thd1.cnt_around_thd2 = 1;
2099 reg->smear_cnt_thd1.cnt_around_thd3 = 4;
2100 reg->smear_cnt_thd2.cnt_around_thd4 = 0;
2101 reg->smear_cnt_thd2.cnt_around_thd5 = 3;
2102 reg->smear_cnt_thd2.cnt_around_thd6 = 0;
2103 reg->smear_cnt_thd2.cnt_around_thd7 = 3;
2104 reg->smear_cnt_thd3.cnt_ref_thd0 = 1;
2105 reg->smear_cnt_thd3.cnt_ref_thd1 = 3;
2106
2107 reg->smear_resi_thd0.resi_small_cur_th0 = 6;
2108 reg->smear_resi_thd0.resi_big_cur_th0 = 9;
2109 reg->smear_resi_thd0.resi_small_cur_th1 = 6;
2110 reg->smear_resi_thd0.resi_big_cur_th1 = 9;
2111 reg->smear_resi_thd1.resi_small_around_th0 = 6;
2112 reg->smear_resi_thd1.resi_big_around_th0 = 11;
2113 reg->smear_resi_thd1.resi_small_around_th1 = 6;
2114 reg->smear_resi_thd1.resi_big_around_th1 = 8;
2115 reg->smear_resi_thd2.resi_small_around_th2 = 9;
2116 reg->smear_resi_thd2.resi_big_around_th2 = 20;
2117 reg->smear_resi_thd2.resi_small_around_th3 = 6;
2118 reg->smear_resi_thd2.resi_big_around_th3 = 20;
2119 reg->smear_resi_thd3.resi_small_ref_th0 = 7;
2120 reg->smear_resi_thd3.resi_big_ref_th0 = 16;
2121 reg->smear_resi_thd4.resi_th0 = flg2 ? 0 : 10;
2122 reg->smear_resi_thd4.resi_th1 = flg2 ? 0 : 6;
2123
2124 reg->smear_st_thd.madp_cnt_th0 = flg2 ? 0 : 1;
2125 reg->smear_st_thd.madp_cnt_th1 = flg2 ? 0 : 5;
2126 reg->smear_st_thd.madp_cnt_th2 = flg2 ? 0 : 1;
2127 reg->smear_st_thd.madp_cnt_th3 = flg2 ? 0 : 3;
2128
2129 hal_h264e_dbg_func("leave\n");
2130 }
2131
setup_vepu510_scaling_list(HalH264eVepu510Ctx * ctx)2132 static void setup_vepu510_scaling_list(HalH264eVepu510Ctx *ctx)
2133 {
2134 HalVepu510RegSet *regs = ctx->regs_set;
2135 Vepu510SclCfg *s = ®s->reg_scl;
2136 RK_U8 *p = (RK_U8 *)&s->tu8_intra_y[0];
2137 RK_U8 idx;
2138
2139 hal_h264e_dbg_func("enter\n");
2140
2141 /* intra4x4 and inter4x4 is not supported on VEPU500.
2142 * valid range: 0x2200 ~ 0x221F
2143 */
2144 if (ctx->pps->pic_scaling_matrix_present == 1) {
2145 for (idx = 0; idx < 64; idx++) {
2146 p[idx] = vepu510_h264_cqm_jvt8i[63 - idx]; /* intra8x8 */
2147 p[idx + 64] = vepu510_h264_cqm_jvt8p[63 - idx]; /* inter8x8 */
2148 }
2149 } else if (ctx->pps->pic_scaling_matrix_present == 2) {
2150 //TODO: Update scaling list for (scaling_list_mode == 2)
2151 mpp_log_f("scaling_list_mode 2 is not supported yet\n");
2152 }
2153
2154 hal_h264e_dbg_func("leave\n");
2155 }
2156
hal_h264e_vepu510_gen_regs(void * hal,HalEncTask * task)2157 static MPP_RET hal_h264e_vepu510_gen_regs(void *hal, HalEncTask *task)
2158 {
2159 HalH264eVepu510Ctx *ctx = (HalH264eVepu510Ctx *)hal;
2160 HalVepu510RegSet *regs = ctx->regs_set;
2161 H264eVepu510Frame *reg_frm = ®s->reg_frm;
2162 MppEncCfgSet *cfg = ctx->cfg;
2163 H264eSps *sps = ctx->sps;
2164 H264ePps *pps = ctx->pps;
2165 H264eSlice *slice = ctx->slice;
2166 EncRcTask *rc_task = task->rc_task;
2167 EncFrmStatus *frm = &rc_task->frm;
2168 MPP_RET ret = MPP_OK;
2169 EncFrmStatus *frm_status = &task->rc_task->frm;
2170
2171 hal_h264e_dbg_func("enter %p\n", hal);
2172 hal_h264e_dbg_detail("frame %d generate regs now", ctx->frms->seq_idx);
2173
2174 /* register setup */
2175 memset(regs, 0, sizeof(*regs));
2176
2177 setup_vepu510_normal(regs);
2178 ret = setup_vepu510_prep(regs, &ctx->cfg->prep);
2179 if (ret)
2180 return ret;
2181
2182 setup_vepu510_dual_core(ctx, slice->slice_type);
2183 setup_vepu510_codec(regs, sps, pps, slice);
2184 setup_vepu510_rdo_pred(ctx, sps, pps, slice);
2185 setup_vepu510_aq(ctx);
2186 setup_vepu510_anti_stripe(ctx);
2187 setup_vepu510_anti_ringing(ctx);
2188 setup_vepu510_anti_flicker(ctx);
2189 setup_vepu510_anti_smear(ctx);
2190 setup_vepu510_scaling_list(ctx);
2191
2192 setup_vepu510_rc_base(regs, ctx, rc_task);
2193 setup_vepu510_io_buf(regs, ctx->offsets, task);
2194 setup_vepu510_recn_refr(ctx, regs);
2195
2196 reg_frm->common.meiw_addr = task->md_info ? mpp_buffer_get_fd(task->md_info) : 0;
2197 reg_frm->common.enc_pic.mei_stor = task->md_info ? 1 : 0;
2198
2199 reg_frm->common.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
2200 reg_frm->common.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
2201
2202 setup_vepu510_split(regs, cfg);
2203 setup_vepu510_me(ctx);
2204
2205 if (frm_status->is_i_refresh)
2206 setup_vepu510_intra_refresh(regs, ctx, frm_status->seq_idx % cfg->rc.gop);
2207
2208 setup_vepu510_l2(ctx, &cfg->hw);
2209 setup_vepu510_ext_line_buf(regs, ctx);
2210 if (ctx->roi_data)
2211 vepu510_set_roi(&ctx->regs_set->reg_rc_roi.roi_cfg, ctx->roi_data,
2212 ctx->cfg->prep.width, ctx->cfg->prep.height);
2213
2214 vepu510_h264e_tune_reg_patch(ctx->tune, task);
2215
2216 /* two pass register patch */
2217 if (frm->save_pass1)
2218 vepu510_h264e_save_pass1_patch(regs, ctx);
2219
2220 if (frm->use_pass1)
2221 vepu510_h264e_use_pass1_patch(regs, ctx);
2222
2223 ctx->frame_cnt++;
2224
2225 hal_h264e_dbg_func("leave %p\n", hal);
2226 return MPP_OK;
2227 }
2228
hal_h264e_vepu510_start(void * hal,HalEncTask * task)2229 static MPP_RET hal_h264e_vepu510_start(void *hal, HalEncTask *task)
2230 {
2231 MPP_RET ret = MPP_OK;
2232 HalH264eVepu510Ctx *ctx = (HalH264eVepu510Ctx *)hal;
2233 HalVepu510RegSet *regs = ctx->regs_set;
2234
2235 (void) task;
2236
2237 hal_h264e_dbg_func("enter %p\n", hal);
2238
2239 do {
2240 MppDevRegWrCfg wr_cfg;
2241 MppDevRegRdCfg rd_cfg;
2242
2243 wr_cfg.reg = ®s->reg_ctl;
2244 wr_cfg.size = sizeof(regs->reg_ctl);
2245 wr_cfg.offset = VEPU510_CTL_OFFSET;
2246 #if DUMP_REG
2247 {
2248 RK_U32 i;
2249 RK_U32 *reg = (RK_U32)wr_cfg.reg;
2250 for ( i = 0; i < sizeof(regs->reg_ctl) / sizeof(RK_U32); i++) {
2251 mpp_log("reg[%d] = 0x%08x\n", i, reg[i]);
2252 }
2253
2254 }
2255 #endif
2256 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
2257 if (ret) {
2258 mpp_err_f("set register write failed %d\n", ret);
2259 break;
2260 }
2261
2262 wr_cfg.reg = ®s->reg_frm;
2263 wr_cfg.size = sizeof(regs->reg_frm);
2264 wr_cfg.offset = VEPU510_FRAME_OFFSET;
2265
2266 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
2267 if (ret) {
2268 mpp_err_f("set register write failed %d\n", ret);
2269 break;
2270 }
2271
2272 wr_cfg.reg = ®s->reg_rc_roi;
2273 wr_cfg.size = sizeof(regs->reg_rc_roi);
2274 wr_cfg.offset = VEPU510_RC_ROI_OFFSET;
2275
2276 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
2277 if (ret) {
2278 mpp_err_f("set register write failed %d\n", ret);
2279 break;
2280 }
2281
2282 wr_cfg.reg = ®s->reg_param;
2283 wr_cfg.size = sizeof(regs->reg_param);
2284 wr_cfg.offset = VEPU510_PARAM_OFFSET;
2285
2286 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
2287 if (ret) {
2288 mpp_err_f("set register write failed %d\n", ret);
2289 break;
2290 }
2291
2292 wr_cfg.reg = ®s->reg_sqi;
2293 wr_cfg.size = sizeof(regs->reg_sqi);
2294 wr_cfg.offset = VEPU510_SQI_OFFSET;
2295
2296 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
2297 if (ret) {
2298 mpp_err_f("set register write failed %d\n", ret);
2299 break;
2300 }
2301
2302 wr_cfg.reg = ®s->reg_scl;
2303 wr_cfg.size = sizeof(regs->reg_scl);
2304 wr_cfg.offset = VEPU510_SCL_OFFSET ;
2305
2306 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
2307 if (ret) {
2308 mpp_err_f("set register write failed %d\n", ret);
2309 break;
2310 }
2311
2312 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFS, ctx->offsets);
2313 if (ret) {
2314 mpp_err_f("set register offsets failed %d\n", ret);
2315 break;
2316 }
2317
2318 rd_cfg.reg = ®s->reg_ctl.int_sta;
2319 rd_cfg.size = sizeof(RK_U32);
2320 rd_cfg.offset = VEPU510_REG_BASE_HW_STATUS;
2321 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
2322 if (ret) {
2323 mpp_err_f("set register read failed %d\n", ret);
2324 break;
2325 }
2326
2327 rd_cfg.reg = ®s->reg_st;
2328 rd_cfg.size = sizeof(regs->reg_st);
2329 rd_cfg.offset = VEPU510_STATUS_OFFSET;
2330
2331 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
2332 if (ret) {
2333 mpp_err_f("set register read failed %d\n", ret);
2334 break;
2335 }
2336
2337 /* send request to hardware */
2338 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
2339 if (ret) {
2340 mpp_err_f("send cmd failed %d\n", ret);
2341 break;
2342 }
2343 } while (0);
2344
2345 hal_h264e_dbg_func("leave %p\n", hal);
2346
2347 return ret;
2348 }
2349
hal_h264e_vepu510_status_check(HalVepu510RegSet * regs)2350 static MPP_RET hal_h264e_vepu510_status_check(HalVepu510RegSet *regs)
2351 {
2352 MPP_RET ret = MPP_OK;
2353
2354 if (regs->reg_ctl.int_sta.lkt_node_done_sta)
2355 hal_h264e_dbg_detail("lkt_done finish");
2356
2357 if (regs->reg_ctl.int_sta.enc_done_sta)
2358 hal_h264e_dbg_detail("enc_done finish");
2359
2360 if (regs->reg_ctl.int_sta.vslc_done_sta)
2361 hal_h264e_dbg_detail("enc_slice finsh");
2362
2363 if (regs->reg_ctl.int_sta.sclr_done_sta)
2364 hal_h264e_dbg_detail("safe clear finsh");
2365
2366 if (regs->reg_ctl.int_sta.vbsf_oflw_sta) {
2367 mpp_err_f("bit stream overflow");
2368 ret = MPP_NOK;
2369 }
2370
2371 if (regs->reg_ctl.int_sta.vbuf_lens_sta) {
2372 mpp_err_f("bus write full");
2373 ret = MPP_NOK;
2374 }
2375
2376 if (regs->reg_ctl.int_sta.enc_err_sta) {
2377 mpp_err_f("bus error");
2378 ret = MPP_NOK;
2379 }
2380
2381 if (regs->reg_ctl.int_sta.wdg_sta) {
2382 mpp_err_f("wdg timeout");
2383 ret = MPP_NOK;
2384 }
2385
2386 return ret;
2387 }
2388
hal_h264e_vepu510_wait(void * hal,HalEncTask * task)2389 static MPP_RET hal_h264e_vepu510_wait(void *hal, HalEncTask *task)
2390 {
2391 MPP_RET ret = MPP_OK;
2392 HalH264eVepu510Ctx *ctx = (HalH264eVepu510Ctx *)hal;
2393 HalVepu510RegSet *regs = &ctx->regs_sets[task->flags.reg_idx];
2394 RK_U32 split_out = ctx->cfg->split.split_out;
2395 MppPacket pkt = task->packet;
2396 RK_S32 offset = mpp_packet_get_length(pkt);
2397 H264NaluType type = task->rc_task->frm.is_idr ? H264_NALU_TYPE_IDR : H264_NALU_TYPE_SLICE;
2398 MppEncH264HwCfg *hw_cfg = &ctx->cfg->h264.hw_cfg;
2399 RK_S32 i;
2400
2401 hal_h264e_dbg_func("enter %p\n", hal);
2402
2403 /* if pass1 mode, it will disable split mode and the split out need to be disable */
2404 if (task->rc_task->frm.save_pass1)
2405 split_out = 0;
2406
2407 /* update split_out in hw_cfg */
2408 hw_cfg->hw_split_out = split_out;
2409
2410 if (split_out) {
2411 EncOutParam param;
2412 RK_U32 slice_len;
2413 RK_U32 slice_last;
2414 MppDevPollCfg *poll_cfg = (MppDevPollCfg *)((char *)ctx->poll_cfgs +
2415 task->flags.reg_idx * ctx->poll_cfg_size);
2416 param.task = task;
2417 param.base = mpp_packet_get_data(task->packet);
2418
2419 do {
2420 poll_cfg->poll_type = 0;
2421 poll_cfg->poll_ret = 0;
2422 poll_cfg->count_max = ctx->poll_slice_max;
2423 poll_cfg->count_ret = 0;
2424
2425 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, poll_cfg);
2426
2427 for (i = 0; i < poll_cfg->count_ret; i++) {
2428 slice_last = poll_cfg->slice_info[i].last;
2429 slice_len = poll_cfg->slice_info[i].length;
2430
2431 mpp_packet_add_segment_info(pkt, type, offset, slice_len);
2432 offset += slice_len;
2433
2434 if (split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) {
2435 param.length = slice_len;
2436
2437 if (slice_last)
2438 ctx->output_cb->cmd = ENC_OUTPUT_FINISH;
2439 else
2440 ctx->output_cb->cmd = ENC_OUTPUT_SLICE;
2441
2442 mpp_callback(ctx->output_cb, ¶m);
2443 }
2444 }
2445 } while (!slice_last);
2446
2447 ret = hal_h264e_vepu510_status_check(regs);
2448 if (!ret)
2449 task->hw_length += regs->reg_st.bs_lgth_l32;
2450 } else {
2451 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
2452 if (ret) {
2453 mpp_err_f("poll cmd failed %d\n", ret);
2454 ret = MPP_ERR_VPUHW;
2455 } else {
2456 ret = hal_h264e_vepu510_status_check(regs);
2457 if (!ret)
2458 task->hw_length += regs->reg_st.bs_lgth_l32;
2459 }
2460
2461 mpp_packet_add_segment_info(pkt, type, offset, regs->reg_st.bs_lgth_l32);
2462 }
2463
2464 if (!(split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) && !ret) {
2465 HalH264eVepuStreamAmend *amend = &ctx->amend_sets[task->flags.reg_idx];
2466
2467 if (amend->enable) {
2468 amend->old_length = task->hw_length;
2469 amend->slice->is_multi_slice = (ctx->cfg->split.split_mode > 0);
2470 h264e_vepu_stream_amend_proc(amend, &ctx->cfg->h264.hw_cfg);
2471 task->hw_length = amend->new_length;
2472 } else if (amend->prefix) {
2473 /* check prefix value */
2474 amend->old_length = task->hw_length;
2475 h264e_vepu_stream_amend_sync_ref_idc(amend);
2476 }
2477 }
2478
2479 hal_h264e_dbg_func("leave %p ret %d\n", hal, ret);
2480
2481 return ret;
2482 }
2483
hal_h264e_vepu510_ret_task(void * hal,HalEncTask * task)2484 static MPP_RET hal_h264e_vepu510_ret_task(void * hal, HalEncTask * task)
2485 {
2486 HalH264eVepu510Ctx *ctx = (HalH264eVepu510Ctx *)hal;
2487 HalVepu510RegSet *regs = &ctx->regs_sets[task->flags.reg_idx];
2488 EncRcTaskInfo *rc_info = &task->rc_task->info;
2489 Vepu510H264Fbk *fb = &ctx->feedback;
2490 Vepu510Status *reg_st = ®s->reg_st;
2491 RK_U32 mb_w = ctx->sps->pic_width_in_mbs;
2492 RK_U32 mb_h = ctx->sps->pic_height_in_mbs;
2493 RK_U32 mbs = mb_w * mb_h;
2494
2495 hal_h264e_dbg_func("enter %p\n", hal);
2496
2497 fb->st_mb_num = mbs;
2498 fb->st_smear_cnt[0] = reg_st->st_smear_cnt.rdo_smear_cnt0 * 4;
2499 fb->st_smear_cnt[1] = reg_st->st_smear_cnt.rdo_smear_cnt1 * 4;
2500 fb->st_smear_cnt[2] = reg_st->st_smear_cnt.rdo_smear_cnt2 * 4;
2501 fb->st_smear_cnt[3] = reg_st->st_smear_cnt.rdo_smear_cnt3 * 4;
2502 fb->st_smear_cnt[4] = fb->st_smear_cnt[0] + fb->st_smear_cnt[1] +
2503 fb->st_smear_cnt[2] + fb->st_smear_cnt[3];
2504 fb->frame_type = ctx->slice->slice_type;
2505
2506 // update total hardware length
2507 task->length += task->hw_length;
2508
2509 // setup bit length for rate control
2510 rc_info->bit_real = task->hw_length * 8;
2511 rc_info->quality_real = regs->reg_st.qp_sum / mbs;
2512 rc_info->iblk4_prop = (regs->reg_st.st_pnum_i4.pnum_i4 +
2513 regs->reg_st.st_pnum_i8.pnum_i8 +
2514 regs->reg_st.st_pnum_i16.pnum_i16) * 256 / mbs;
2515
2516 rc_info->sse = ((RK_S64)regs->reg_st.sse_h32 << 16) +
2517 (regs->reg_st.st_sse_bsl.sse_l16 & 0xffff);
2518 rc_info->lvl16_inter_num = regs->reg_st.st_pnum_p16.pnum_p16;
2519 rc_info->lvl8_inter_num = regs->reg_st.st_pnum_p8.pnum_p8;
2520 rc_info->lvl16_intra_num = regs->reg_st.st_pnum_i16.pnum_i16;
2521 rc_info->lvl8_intra_num = regs->reg_st.st_pnum_i8.pnum_i8;
2522 rc_info->lvl4_intra_num = regs->reg_st.st_pnum_i4.pnum_i4;
2523
2524 ctx->hal_rc_cfg.bit_real = rc_info->bit_real;
2525 ctx->hal_rc_cfg.quality_real = rc_info->quality_real;
2526 ctx->hal_rc_cfg.iblk4_prop = rc_info->iblk4_prop;
2527
2528 task->hal_ret.data = &ctx->hal_rc_cfg;
2529 task->hal_ret.number = 1;
2530
2531 mpp_dev_multi_offset_reset(ctx->offsets);
2532
2533 if (ctx->dpb) {
2534 h264e_dpb_hal_end(ctx->dpb, task->flags.curr_idx);
2535 h264e_dpb_hal_end(ctx->dpb, task->flags.refr_idx);
2536 }
2537
2538 vepu510_h264e_tune_stat_update(ctx->tune, task);
2539
2540 hal_h264e_dbg_func("leave %p\n", hal);
2541
2542 return MPP_OK;
2543 }
2544
2545 const MppEncHalApi hal_h264e_vepu510 = {
2546 .name = "hal_h264e_vepu510",
2547 .coding = MPP_VIDEO_CodingAVC,
2548 .ctx_size = sizeof(HalH264eVepu510Ctx),
2549 .flag = 0,
2550 .init = hal_h264e_vepu510_init,
2551 .deinit = hal_h264e_vepu510_deinit,
2552 .prepare = hal_h264e_vepu510_prepare,
2553 .get_task = hal_h264e_vepu510_get_task,
2554 .gen_regs = hal_h264e_vepu510_gen_regs,
2555 .start = hal_h264e_vepu510_start,
2556 .wait = hal_h264e_vepu510_wait,
2557 .part_start = NULL,
2558 .part_wait = NULL,
2559 .ret_task = hal_h264e_vepu510_ret_task,
2560 };
2561