1 /** @file mlan_pcie.h 2 * 3 * @brief This file contains definitions for PCIE interface. 4 * driver. 5 * 6 * 7 * Copyright 2008-2021 NXP 8 * 9 * This software file (the File) is distributed by NXP 10 * under the terms of the GNU General Public License Version 2, June 1991 11 * (the License). You may use, redistribute and/or modify the File in 12 * accordance with the terms and conditions of the License, a copy of which 13 * is available by writing to the Free Software Foundation, Inc., 14 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 15 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 16 * 17 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 19 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 20 * this warranty disclaimer. 21 * 22 */ 23 24 /******************************************************** 25 Change log: 26 02/01/2012: initial version 27 ********************************************************/ 28 29 #ifndef _MLAN_PCIE_H_ 30 #define _MLAN_PCIE_H_ 31 /** Tx DATA */ 32 #define ADMA_TX_DATA 0 33 /** Rx DATA */ 34 #define ADMA_RX_DATA 1 35 /** EVENT */ 36 #define ADMA_EVENT 2 37 /** CMD */ 38 #define ADMA_CMD 3 39 /** CMD RESP */ 40 #define ADMA_CMDRESP 4 41 /** ADMA direction */ 42 #define ADMA_HOST_TO_DEVICE 0 43 /** ADMA direction Rx */ 44 #define ADMA_DEVICE_TO_HOST 1 45 /** Direct Program mode */ 46 #define DMA_MODE_DIRECT 0 47 /** Single descriptor mode */ 48 #define DMA_MODE_SINGLE_DESC 1 49 /** dual discriptor mode */ 50 #define DMA_MODE_DUAL_DESC 2 51 /** descriptor mode: ring mode */ 52 #define DESC_MODE_RING 0 53 /** descriptor mode: chain mode */ 54 #define DESC_MODE_CHAIN 1 55 /** DMA size start bit */ 56 #define DMA_SIZE_BIT 16 57 /** DMA size mask */ 58 #define DMA_SIZE_MASK 0xffff0000 59 /** Descriptor mode */ 60 #define DESC_MODE_MASK 0x0004 61 /** DMA MODE MASK */ 62 #define DMA_MODE_MASK 0x0003 63 /** Dest Num Descriptor start bits */ 64 #define DST_NUM_DESC_BIT 12 65 /** Destination Num of Descriptor mask */ 66 #define DST_NUM_DESC_MASK 0xf000 67 /** Src Num Descriptor start bits */ 68 #define SRC_NUM_DESC_BIT 8 69 /** Destination Num of Descriptor mask */ 70 #define SRC_NUM_DESC_MASK 0x0f00 71 /** Virtual Q priority mask */ 72 #define Q_PRIO_WEIGHT_MASK 0x00f0 73 /** DMA cfg register offset*/ 74 #define ADMA_DMA_CFG 0x0000 75 /** source base low */ 76 #define ADMA_SRC_LOW 0x0004 77 /** source base high */ 78 #define ADMA_SRC_HIGH 0x0008 79 /** destination base low */ 80 #define ADMA_DST_LOW 0x000C 81 /** destination base high */ 82 #define ADMA_DST_HIGH 0x0010 83 /** source rd/wr pointer */ 84 #define ADMA_SRC_RW_PTR 0x0014 85 /** destination rd/wr pointer */ 86 #define ADMA_DST_RW_PTR 0x0018 87 /** interrupt direction mapping reg, for each virtual Q, used for 88 * dual-descriptor only, only valid for Q0 */ 89 #define ADMA_INT_MAPPING 0x001C 90 /** destination interrupt to device */ 91 #define DEST_INT_TO_DEVICE MBIT(0) 92 /** destination interrupt to host */ 93 #define DEST_INT_TO_HOST MBIT(1) 94 /** interrupt pending status for each virtual Q, only valid for Q0 */ 95 #define ADMA_INT_PENDING 0x0020 96 /** Default ADMA INT mask, We only enable dma done */ 97 #define DEF_ADMA_INT_MASK MBIT(0) 98 /** source interrupt status mask reg */ 99 #define ADMA_SRC_INT_STATUS_MASK 0x0024 100 /** source interrupt mask reg */ 101 #define ADMA_SRC_INT_MASK 0x0028 102 /** source interrupt status reg */ 103 #define ADMA_SRC_INT_STATUS 0x002C 104 /** destination interrupt status mask reg */ 105 #define ADMA_DST_INT_STATUS_MASK 0x0030 106 /** destination interrupt mask reg */ 107 #define ADMA_DST_INT_MASK 0x0034 108 /** destination interrupt status reg */ 109 #define ADMA_DST_INT_STATUS 0x0038 110 /** DMA cfg2 register */ 111 #define ADMA_DMA_CFG2 0x003C 112 /** ADMA_MSI_LEGACY_DST_DMA_DONE_INT_BYPASS_EN */ 113 #define ADMA_MSI_LEGACY_DST_DMA_DONE_INT_BYPASS_EN MBIT(22) 114 /** ADMA_MSI_LEGACY_SRC_DMA_DONE_INT_BYPASS_EN */ 115 #define ADMA_MSI_LEGACY_SRC_DMA_DONE_INT_BYPASS_EN MBIT(21) 116 /* If this bit is set, MSIX trigger event will be from DST, other wise MSIX 117 * trigger event will be from SRC */ 118 #define ADMA_MSIX_INT_SRC_DST_SEL MBIT(20) 119 /** Enable MSI/Legacy for this Queue */ 120 #define ADMA_MSI_LEGACY_ENABLE MBIT(19) 121 /** Enable MSIX for this queue */ 122 #define ADMA_MSIX_ENABLE MBIT(18) 123 /** ADMA_DST_DMA_DONE_INT_BYPASS_EN */ 124 #define ADMA_DST_DMA_DONE_INT_BYPASS_EN MBIT(17) 125 /** SRC_DMA_DONE_INT_BYPASS_EN */ 126 #define ADMA_SRC_DMA_DONE_INT_BYPASS_EN MBIT(16) 127 /* Destination Read Pointer Memory Copy Enable */ 128 #define ADMA_DST_RPTR_MEM_COPY_EN MBIT(11) 129 /* Source Read Pointer Memory Copy Enable */ 130 #define ADMA_SRC_RPTR_MEM_COPY_EN MBIT(10) 131 /** Destination address is host */ 132 #define ADMA_DST_ADDR_IS_HOST MBIT(2) 133 /** Source address is host */ 134 #define ADMA_SRC_ADDR_IS_HOST MBIT(1) 135 136 /** DMA cfg3 register */ 137 #define ADMA_DMA_CFG3 0x0040 138 /** ADMA Queue pointer clear */ 139 #define ADMA_Q_PTR_CLR MBIT(0) 140 /** source rd ptr address low */ 141 #define ADMA_SRC_RD_PTR_LOW 0x0044 142 /** source rd ptr address high */ 143 #define ADMA_SRC_RD_PTR_HIGH 0x0048 144 /** destination rd ptr address low */ 145 #define ADMA_DST_RD_PTR_LOW 0x004C 146 /** destination rd ptr address high */ 147 #define ADMA_DST_RD_PTR_HIGH 0x0050 148 /** source active interrupt mask */ 149 #define ADMA_SRC_ACTV_INT_MASK 0x0054 150 /** destination active interrupt mask */ 151 #define ADMA_DST_ACTV_INT_MASK 0x0058 152 /** Read pointer start from bit 16 */ 153 #define ADMA_RPTR_START 16 154 /** write pointer start from bit 0 */ 155 #define ADMA_WPTR_START 0 156 /** Tx/Rx Read/Write pointer's mask */ 157 #define TXRX_RW_PTR_MASK (ADMA_MAX_TXRX_BD - 1) 158 /** Tx/Rx Read/Write pointer's rollover indicate bit */ 159 #define TXRX_RW_PTR_ROLLOVER_IND ADMA_MAX_TXRX_BD 160 /** Start of packet flag */ 161 #define ADMA_BD_FLAG_SOP MBIT(0) 162 /** End of packet flag */ 163 #define ADMA_BD_FLAG_EOP MBIT(1) 164 /** interrupt enable flag */ 165 #define ADMA_BD_FLAG_INT_EN MBIT(2) 166 /** Source address is host side flag */ 167 #define ADMA_BD_FLAG_SRC_HOST MBIT(3) 168 /** Destination address is host side flag */ 169 #define ADMA_BD_FLAG_DST_HOST MBIT(4) 170 /** ADMA MIN PKT SIZE */ 171 #define ADMA_MIN_PKT_SIZE 128 172 /** ADMA dual descriptor mode requir 8 bytes alignment in buf size */ 173 #define ADMA_ALIGN_SIZE 8 174 /** ADMA RW_PTR wrap mask */ 175 #define ADMA_RW_PTR_WRAP_MASK 0x00001FFF 176 /** ADMA MSIX DOORBEEL DATA */ 177 #define ADMA_MSIX_DOORBELL_DATA 0x0064 178 /** MSIX VECTOR MASK: BIT 0-10 */ 179 #define ADMA_MSIX_VECTOR_MASK 0x3f 180 /** PF mask: BIT 24-28 */ 181 #define ADMA_MSIX_PF_MASK 0x1f000000 182 /** PF start bit */ 183 #define ADMA_MSIX_PF_BIT 24 184 185 #if defined(PCIE9098) || defined(PCIE9097) || defined(PCIENW62X) 186 /** PCIE9098 dev_id/vendor id reg */ 187 #define PCIE9098_DEV_ID_REG 0x0000 188 /** PCIE revision ID register */ 189 #define PCIE9098_REV_ID_REG 0x0008 190 /** PCIE IP revision register */ 191 #define PCIE9098_IP_REV_REG 0x1000 192 /** PCIE CPU interrupt events */ 193 #define PCIE9098_CPU_INT_EVENT 0x1C20 194 /** PCIE CPU interrupt status */ 195 #define PCIE9098_CPU_INT_STATUS 0x1C24 196 /** PCIe CPU Interrupt Status Mask */ 197 #define PCIE9098_CPU_INT2ARM_ISM 0x1C28 198 /** PCIE host interrupt status */ 199 #define PCIE9098_HOST_INT_STATUS 0x1C44 200 /** PCIE host interrupt mask */ 201 #define PCIE9098_HOST_INT_MASK 0x1C48 202 /** PCIE host interrupt clear select*/ 203 #define PCIE9098_HOST_INT_CLR_SEL 0x1C4C 204 /** PCIE host interrupt status mask */ 205 #define PCIE9098_HOST_INT_STATUS_MASK 0x1C50 206 /** PCIE host interrupt status */ 207 #define PCIE9097_B0_HOST_INT_STATUS 0x3C44 208 /** PCIE host interrupt mask */ 209 #define PCIE9097_B0_HOST_INT_MASK 0x3C48 210 /** PCIE host interrupt clear select*/ 211 #define PCIE9097_B0_HOST_INT_CLR_SEL 0x3C4C 212 /** PCIE host interrupt status mask */ 213 #define PCIE9097_B0_HOST_INT_STATUS_MASK 0x3C50 214 /** PCIE host interrupt select*/ 215 #define PCIE9098_HOST_INT_SEL 0x1C58 216 /** PCIE data exchange register 0 */ 217 #define PCIE9098_SCRATCH_0_REG 0x1C60 218 /** PCIE data exchange register 1 */ 219 #define PCIE9098_SCRATCH_1_REG 0x1C64 220 /** PCIE data exchange register 2 */ 221 #define PCIE9098_SCRATCH_2_REG 0x1C68 222 /** PCIE data exchange register 3 */ 223 #define PCIE9098_SCRATCH_3_REG 0x1C6C 224 /** PCIE data exchange register 4 */ 225 #define PCIE9098_SCRATCH_4_REG 0x1C70 226 /** PCIE data exchange register 5 */ 227 #define PCIE9098_SCRATCH_5_REG 0x1C74 228 /** PCIE data exchange register 6 */ 229 #define PCIE9098_SCRATCH_6_REG 0x1C78 230 /** PCIE data exchange register 7 */ 231 #define PCIE9098_SCRATCH_7_REG 0x1C7C 232 /** PCIE data exchange register 8 */ 233 #define PCIE9098_SCRATCH_8_REG 0x1C80 234 /** PCIE data exchange register 9 */ 235 #define PCIE9098_SCRATCH_9_REG 0x1C84 236 /** PCIE data exchange register 10 */ 237 #define PCIE9098_SCRATCH_10_REG 0x1C88 238 /** PCIE data exchange register 11 */ 239 #define PCIE9098_SCRATCH_11_REG 0x1C8C 240 /** PCIE data exchange register 12 */ 241 #define PCIE9098_SCRATCH_12_REG 0x1C90 242 /** PCIE data exchange register 13 */ 243 #define PCIE9098_SCRATCH_13_REG 0x1C94 244 /** PCIE data exchange register 14 */ 245 #define PCIE9098_SCRATCH_14_REG 0x1C98 246 /** PCIE data exchange register 15 */ 247 #define PCIE9098_SCRATCH_15_REG 0x1C9C 248 /** ADMA CHAN0_Q0 start address, Tx Data */ 249 #define ADMA_CHAN0_Q0 0x10000 250 /** ADMA CHAN1_Q0 start address, Rx Data */ 251 #define ADMA_CHAN1_Q0 0x10800 252 /** ADMA CHAN1_Q1 start address, Rx Event */ 253 #define ADMA_CHAN1_Q1 0x10880 254 /** ADMA CHAN2_Q0 start address, Tx Command */ 255 #define ADMA_CHAN2_Q0 0x11000 256 /** ADMA CHAN2_Q1 start address, Command Resp */ 257 #define ADMA_CHAN2_Q1 0x11080 258 /** CH0-Q0' src rd/wr ptr */ 259 #define ADMA_SRC_PTR_CH0_Q0 (ADMA_CHAN0_Q0 + ADMA_SRC_RW_PTR) 260 /** CH1-Q1' dest rd/wr ptr */ 261 #define ADMA_DST_PTR_CH1_Q0 (ADMA_CHAN1_Q0 + ADMA_DST_RW_PTR) 262 /** CH1-Q1' dest rd/wr ptr */ 263 #define ADMA_DST_PTR_CH1_Q1 (ADMA_CHAN1_Q1 + ADMA_DST_RW_PTR) 264 /* TX buffer description read pointer */ 265 #define PCIE9098_TXBD_RDPTR ADMA_SRC_PTR_CH0_Q0 266 /* TX buffer description write pointer */ 267 #define PCIE9098_TXBD_WRPTR ADMA_SRC_PTR_CH0_Q0 268 /* RX buffer description read pointer */ 269 #define PCIE9098_RXBD_RDPTR ADMA_DST_PTR_CH1_Q0 270 /* RX buffer description write pointer */ 271 #define PCIE9098_RXBD_WRPTR ADMA_DST_PTR_CH1_Q0 272 /* Event buffer description read pointer */ 273 #define PCIE9098_EVTBD_RDPTR ADMA_DST_PTR_CH1_Q1 274 /* Event buffer description write pointer */ 275 #define PCIE9098_EVTBD_WRPTR ADMA_DST_PTR_CH1_Q1 276 /* Driver ready signature write pointer */ 277 #define PCIE9098_DRV_READY PCIE9098_SCRATCH_12_REG 278 279 /** interrupt bit define for ADMA CHAN0 Q0, For Tx DATA */ 280 #define ADMA_INT_CHAN0_Q0 MBIT(0) 281 /** interrupt bit define for ADMA CHAN1 Q0, For Rx Data */ 282 #define AMDA_INT_CHAN1_Q0 MBIT(16) 283 /** interrupt bit define for ADMA CHAN1 Q1, For Rx Event */ 284 #define AMDA_INT_CHAN1_Q1 MBIT(17) 285 /** interrupt bit define for ADMA CHAN2 Q0, For Tx Command */ 286 #define AMDA_INT_CHAN2_Q0 MBIT(24) 287 /** interrupt bit define for ADMA CHAN2 Q1, For Rx Command Resp */ 288 #define AMDA_INT_CHAN2_Q1 MBIT(25) 289 290 /** interrupt vector number for ADMA CHAN0 Q0, For Tx DATA */ 291 #define ADMA_VECTOR_CHAN0_Q0 0 292 /** interrupt vector number for ADMA CHAN1 Q0, For Rx Data */ 293 #define AMDA_VECTOR_CHAN1_Q0 16 294 /** interrupt vector number for ADMA CHAN1 Q1, For Rx Event */ 295 #define AMDA_VECTOR_CHAN1_Q1 17 296 /** interrupt vector number for ADMA CHAN2 Q0, For Tx Command */ 297 #define AMDA_VECTOR_CHAN2_Q0 24 298 /** interrupt vector number for ADMA CHAN2 Q1, For Rx Command Resp */ 299 #define AMDA_VECTOR_CHAN2_Q1 25 300 301 /** Data sent interrupt for host */ 302 #define PCIE9098_HOST_INTR_DNLD_DONE ADMA_INT_CHAN0_Q0 303 /** Data receive interrupt for host */ 304 #define PCIE9098_HOST_INTR_UPLD_RDY AMDA_INT_CHAN1_Q0 305 /** Command sent interrupt for host */ 306 #define PCIE9098_HOST_INTR_CMD_DONE AMDA_INT_CHAN2_Q1 307 /** Event ready interrupt for host */ 308 #define PCIE9098_HOST_INTR_EVENT_RDY AMDA_INT_CHAN1_Q1 309 /** CMD sent interrupt for host */ 310 #define PCIE9098_HOST_INTR_CMD_DNLD MBIT(7) 311 312 /** Interrupt mask for host */ 313 #define PCIE9098_HOST_INTR_MASK \ 314 (PCIE9098_HOST_INTR_DNLD_DONE | PCIE9098_HOST_INTR_UPLD_RDY | \ 315 PCIE9098_HOST_INTR_CMD_DONE | PCIE9098_HOST_INTR_CMD_DNLD | \ 316 PCIE9098_HOST_INTR_EVENT_RDY) 317 318 /** Interrupt select mask for host */ 319 #define PCIE9098_HOST_INTR_SEL_MASK \ 320 (PCIE9098_HOST_INTR_DNLD_DONE | PCIE9098_HOST_INTR_UPLD_RDY | \ 321 PCIE9098_HOST_INTR_CMD_DONE | PCIE9098_HOST_INTR_EVENT_RDY) 322 #endif 323 324 #if defined(PCIE8997) || defined(PCIE8897) 325 /* PCIE INTERNAL REGISTERS */ 326 /** PCIE data exchange register 0 */ 327 #define PCIE_SCRATCH_0_REG 0x0C10 328 /** PCIE data exchange register 1 */ 329 #define PCIE_SCRATCH_1_REG 0x0C14 330 /** PCIE CPU interrupt events */ 331 #define PCIE_CPU_INT_EVENT 0x0C18 332 /** PCIE CPU interrupt status */ 333 #define PCIE_CPU_INT_STATUS 0x0C1C 334 335 /** PCIe CPU Interrupt Status Mask */ 336 #define PCIE_CPU_INT2ARM_ISM 0x0C28 337 /** PCIE host interrupt status */ 338 #define PCIE_HOST_INT_STATUS 0x0C30 339 /** PCIE host interrupt mask */ 340 #define PCIE_HOST_INT_MASK 0x0C34 341 /** PCIE host interrupt status mask */ 342 #define PCIE_HOST_INT_STATUS_MASK 0x0C3C 343 /** PCIE data exchange register 2 */ 344 #define PCIE_SCRATCH_2_REG 0x0C40 345 /** PCIE data exchange register 3 */ 346 #define PCIE_SCRATCH_3_REG 0x0C44 347 348 #define PCIE_IP_REV_REG 0x0C48 349 350 /** PCIE data exchange register 4 */ 351 #define PCIE_SCRATCH_4_REG 0x0CD0 352 /** PCIE data exchange register 5 */ 353 #define PCIE_SCRATCH_5_REG 0x0CD4 354 /** PCIE data exchange register 6 */ 355 #define PCIE_SCRATCH_6_REG 0x0CD8 356 /** PCIE data exchange register 7 */ 357 #define PCIE_SCRATCH_7_REG 0x0CDC 358 /** PCIE data exchange register 8 */ 359 #define PCIE_SCRATCH_8_REG 0x0CE0 360 /** PCIE data exchange register 9 */ 361 #define PCIE_SCRATCH_9_REG 0x0CE4 362 /** PCIE data exchange register 10 */ 363 #define PCIE_SCRATCH_10_REG 0x0CE8 364 /** PCIE data exchange register 11 */ 365 #define PCIE_SCRATCH_11_REG 0x0CEC 366 /** PCIE data exchange register 12 */ 367 #define PCIE_SCRATCH_12_REG 0x0CF0 368 #endif 369 370 #ifdef PCIE8997 371 /* PCIE read data pointer for queue 0 and 1 */ 372 #define PCIE8997_RD_DATA_PTR_Q0_Q1 0xC1A4 /* 0x8000C1A4 */ 373 /* PCIE read data pointer for queue 2 and 3 */ 374 #define PCIE8997_RD_DATA_PTR_Q2_Q3 0xC1A8 /* 0x8000C1A8 */ 375 /* PCIE write data pointer for queue 0 and 1 */ 376 #define PCIE8997_WR_DATA_PTR_Q0_Q1 0xC174 /* 0x8000C174 */ 377 /* PCIE write data pointer for queue 2 and 3 */ 378 #define PCIE8997_WR_DATA_PTR_Q2_Q3 0xC178 /* 0x8000C178 */ 379 #endif 380 #ifdef PCIE8897 381 /* PCIE read data pointer for queue 0 and 1 */ 382 #define PCIE8897_RD_DATA_PTR_Q0_Q1 0xC08C /* 0x8000C08C */ 383 /* PCIE read data pointer for queue 2 and 3 */ 384 #define PCIE8897_RD_DATA_PTR_Q2_Q3 0xC090 /* 0x8000C090 */ 385 /* PCIE write data pointer for queue 0 and 1 */ 386 #define PCIE8897_WR_DATA_PTR_Q0_Q1 0xC05C /* 0x8000C05C */ 387 /* PCIE write data pointer for queue 2 and 3 */ 388 #define PCIE8897_WR_DATA_PTR_Q2_Q3 0xC060 /* 0x8000C060 */ 389 #endif 390 391 /** Download ready interrupt for CPU */ 392 #define CPU_INTR_DNLD_RDY MBIT(0) 393 /** Command ready interrupt for CPU */ 394 #define CPU_INTR_DOOR_BELL MBIT(1) 395 /** Confirmation that sleep confirm message has been processed. 396 Device will enter sleep after receiving this interrupt */ 397 #define CPU_INTR_SLEEP_CFM_DONE MBIT(2) 398 /** Reset interrupt for CPU */ 399 #define CPU_INTR_RESET MBIT(3) 400 /** Set Event Done interupt to the FW*/ 401 #define CPU_INTR_EVENT_DONE MBIT(5) 402 403 #if defined(PCIE8997) || defined(PCIE8897) 404 /** Data sent interrupt for host */ 405 #define HOST_INTR_DNLD_DONE MBIT(0) 406 /** Data receive interrupt for host */ 407 #define HOST_INTR_UPLD_RDY MBIT(1) 408 /** Command sent interrupt for host */ 409 #define HOST_INTR_CMD_DONE MBIT(2) 410 /** Event ready interrupt for host */ 411 #define HOST_INTR_EVENT_RDY MBIT(3) 412 /** Interrupt mask for host */ 413 #define HOST_INTR_MASK \ 414 (HOST_INTR_DNLD_DONE | HOST_INTR_UPLD_RDY | HOST_INTR_CMD_DONE | \ 415 HOST_INTR_EVENT_RDY) 416 417 /** Lower 32bits command address holding register */ 418 #define REG_CMD_ADDR_LO PCIE_SCRATCH_0_REG 419 /** Upper 32bits command address holding register */ 420 #define REG_CMD_ADDR_HI PCIE_SCRATCH_1_REG 421 /** Command length holding register */ 422 #define REG_CMD_SIZE PCIE_SCRATCH_2_REG 423 424 /** Lower 32bits command response address holding register */ 425 #define REG_CMDRSP_ADDR_LO PCIE_SCRATCH_4_REG 426 /** Upper 32bits command response address holding register */ 427 #define REG_CMDRSP_ADDR_HI PCIE_SCRATCH_5_REG 428 429 /** TxBD's Read/Write pointer start from bit 16 */ 430 #define TXBD_RW_PTR_START 16 431 /** RxBD's Read/Write pointer start from bit 0 */ 432 #define RXBD_RW_PTR_STRAT 0 433 434 #define MLAN_BD_FLAG_SOP MBIT(0) 435 #define MLAN_BD_FLAG_EOP MBIT(1) 436 #define MLAN_BD_FLAG_XS_SOP MBIT(2) 437 #define MLAN_BD_FLAG_XS_EOP MBIT(3) 438 439 /* Event buffer description write pointer */ 440 #define REG_EVTBD_WRPTR PCIE_SCRATCH_10_REG 441 /* Event buffer description read pointer */ 442 #define REG_EVTBD_RDPTR PCIE_SCRATCH_11_REG 443 /* Driver ready signature write pointer */ 444 #define REG_DRV_READY PCIE_SCRATCH_12_REG 445 446 /** Event Read/Write pointer mask */ 447 #define EVT_RW_PTR_MASK 0x0f 448 /** Event Read/Write pointer rollover bit */ 449 #define EVT_RW_PTR_ROLLOVER_IND MBIT(7) 450 #endif 451 452 /* Define PCIE block size for firmware download */ 453 #define MLAN_PCIE_BLOCK_SIZE_FW_DNLD 256 454 455 /** Extra added macros **/ 456 #define MLAN_EVENT_HEADER_LEN 8 457 458 /** Max interrupt status register read limit */ 459 #define MAX_READ_REG_RETRY 10000 460 461 extern mlan_adapter_operations mlan_pcie_ops; 462 463 /* Get pcie device from card type */ 464 mlan_status wlan_get_pcie_device(pmlan_adapter pmadapter); 465 466 /** Set PCIE host buffer configurations */ 467 mlan_status wlan_set_pcie_buf_config(mlan_private *pmpriv); 468 469 /** Init write pointer */ 470 mlan_status wlan_pcie_init_fw(pmlan_adapter pmadapter); 471 472 #if defined(PCIE8997) || defined(PCIE8897) 473 /** Prepare command PCIE host buffer config */ 474 mlan_status wlan_cmd_pcie_host_buf_cfg(pmlan_private pmpriv, 475 pHostCmd_DS_COMMAND cmd, 476 t_u16 cmd_action, t_pvoid pdata_buf); 477 #endif 478 479 /** Wakeup PCIE card */ 480 mlan_status wlan_pcie_wakeup(pmlan_adapter pmadapter); 481 482 /** Set DRV_READY register */ 483 mlan_status wlan_set_drv_ready_reg(mlan_adapter *pmadapter, t_u32 val); 484 /** PCIE init */ 485 mlan_status wlan_pcie_init(mlan_adapter *pmadapter); 486 487 /** Read interrupt status */ 488 mlan_status wlan_process_msix_int(mlan_adapter *pmadapter); 489 /** Transfer data to card */ 490 mlan_status wlan_pcie_host_to_card(pmlan_private pmpriv, t_u8 type, 491 mlan_buffer *mbuf, mlan_tx_param *tx_param); 492 /** Ring buffer allocation function */ 493 mlan_status wlan_alloc_pcie_ring_buf(pmlan_adapter pmadapter); 494 /** Ring buffer deallocation function */ 495 mlan_status wlan_free_pcie_ring_buf(pmlan_adapter pmadapter); 496 /** Ring buffer cleanup function, e.g. on deauth */ 497 mlan_status wlan_clean_pcie_ring_buf(pmlan_adapter pmadapter); 498 mlan_status wlan_alloc_ssu_pcie_buf(pmlan_adapter pmadapter); 499 mlan_status wlan_free_ssu_pcie_buf(pmlan_adapter pmadapter); 500 501 #endif /* _MLAN_PCIE_H_ */ 502