1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2008-2010 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// file mdrv_frc.h 97 /// @brief Driver Interface 98 /// @author MStar Semiconductor Inc. 99 /////////////////////////////////////////////////////////////////////////////////////////////////// 100 101 #ifndef _MDRV_FRC_H_ 102 #define _MDRV_FRC_H_ 103 #include "mhal_frc.h" 104 //------------------------------------------------------------------------------------------------- 105 // Macro and Define 106 //------------------------------------------------------------------------------------------------- 107 #if 0 108 typedef struct MST_PANEL_INFO_s 109 { 110 // Basic 111 MS_U16 u16HStart; //ursa scaler 112 MS_U16 u16VStart; //ursa scaler 113 MS_U16 u16Width; //ursa scaler 114 MS_U16 u16Height; //ursa scaler 115 MS_U16 u16HTotal; //ursa scaler 116 MS_U16 u16VTotal; //ursa scaler 117 118 MS_U16 u16DE_VStart; 119 120 MS_U16 u16DefaultVFreq; 121 122 // LPLL 123 MS_U16 u16LPLL_InputDiv; 124 MS_U16 u16LPLL_LoopDiv; 125 MS_U16 u16LPLL_OutputDiv; 126 127 MS_U8 u8LPLL_Type; 128 MS_U8 u8LPLL_Mode; 129 130 // sync 131 MS_U8 u8HSyncWidth; 132 MS_BOOL bPnlDblVSync; 133 134 // output control 135 MS_U16 u16OCTRL; 136 MS_U16 u16OSTRL; 137 MS_U16 u16ODRV; 138 MS_U16 u16DITHCTRL; 139 140 // MOD 141 MS_U16 u16MOD_CTRL0; // BIT2: tiMode, BIT5: lvdsSwapPol, BIT6: lvdsSwapCh 142 MS_U8 u8MOD_CTRL2; 143 MS_U16 u16MOD_CTRL9; 144 MS_U16 u16MOD_CTRLA; // BIT2: invertDE, BIT3: invertVS, BIT12: invertHS 145 MS_U8 u8MOD_CTRLB; // BIT0~1: panelBitNums 146 147 MS_U8 u8MOD_CTRL77; //pre-emphasis level 148 MS_U8 u8MOD_CTRL78; 149 //LGE [vivakjh] 2008/11/12 Add for DVB PDP Panel 150 //Additional Info.(V Total) 151 MS_U16 u16VTotal60Hz; //ursa scaler 152 MS_U16 u16VTotal50Hz; //ursa scaler 153 MS_U16 u16VTotal48Hz; //ursa scaler 154 //[vivakjh] 2008/12/23 Add for adjusting the MRE in PDP S6 155 MS_U16 u16VStart60Hz; 156 MS_U16 u16VStart50Hz; 157 MS_U16 u16VStart48Hz; 158 MS_U16 u16VBackPorch60Hz; 159 MS_U16 u16VBackPorch50Hz; 160 MS_U16 u16VBackPorch48Hz; 161 162 /*Panel Option 163 0: LCD 164 1: PDP 165 2: LCD_NO_FRC 166 3: LCD_TCON 167 */ 168 MS_U8 u8LCDorPDP; 169 170 MS_U32 u32LimitD5d6d7; //thchen 20081216 171 MS_U16 u16LimitOffset; //thchen 20081216 172 MS_U8 u8LvdsSwingUp; 173 MS_BOOL bTTL_10BIT; 174 MS_BOOL bOD_DataPath; 175 176 //------------------------------------------------------------------------------------------------- 177 // FRC Control 178 //------------------------------------------------------------------------------------------------- 179 MS_BOOL bFRC; 180 MS_U16 u16MOD_SwingLevel; 181 MS_U16 u16MOD_SwingCLK; 182 MS_U16 u16output_cfg_10; 183 MS_U16 u16output_cfg_11; 184 MS_U16 u16output_cfg_12; 185 MS_U8 u8output_cfg_13; 186 MS_U8 u8PanelNoiseDith; 187 MS_U8 u8lvdsSwapCh; 188 MS_U8 u8FRC3DPanelType; 189 190 MS_BOOL bdither6Bits; 191 MS_BOOL blvdsShiftPair; 192 MS_BOOL blvdsSwapPair; 193 194 // TGEN 195 MS_U16 u16HSyncStart; 196 MS_U16 u16HSyncEnd; 197 MS_U16 u16VSyncStart; 198 MS_U16 u16VSyncEnd; 199 MS_U16 u16VTrigX; 200 MS_U16 u16VTrigY; 201 202 // EPI 203 MS_BOOL bepiLRSwap; 204 MS_BOOL bepiLMirror; 205 MS_BOOL bepiRMirror; 206 207 } MST_PANEL_INFO_t, *PMST_PANEL_INFO_t; 208 #endif 209 typedef struct 210 { 211 //------------------------------------------------------------------------------------------------- 212 // FRC Control 213 //------------------------------------------------------------------------------------------------- 214 MS_U16 u16MOD_SwingLevel; 215 MS_U16 u16MOD_SwingCLK; 216 MS_U8 u8PanelNoiseDith; 217 MS_U8 u8lvdsSwapCh; 218 MS_BOOL bdither6Bits; 219 MS_BOOL blvdsShiftPair; 220 MS_BOOL blvdsSwapPair; 221 222 // EPI 223 MS_BOOL bepiLRSwap; 224 MS_BOOL bepiLMirror; 225 MS_BOOL bepiRMirror; 226 } MST_PANEL_FRC_INFO_t, *PMST_PANEL_FRC_INFO_t; 227 228 229 typedef struct 230 { 231 MS_PHY u32MfcBase; 232 MS_U32 u32MfcSize; 233 234 MS_PHY u32IpYcoutBase; 235 MS_U32 u32IpYcoutSize; 236 MS_PHY u32IpMrBase; 237 MS_U32 u32IpMrSize; 238 239 MS_PHY u32GammaBase; 240 MS_U32 u32GammaSize; 241 242 MS_PHY u32OdBase; 243 MS_U32 u32OdSize; 244 MS_PHY u32OdLsbBase; 245 MS_U32 u32OdLsbSize; 246 247 MS_U32 u32AutoBist; 248 249 MS_U8 u8MfcMode; 250 MS_U8 u8IpMode; 251 MS_U8 u8GammaMode; 252 MS_U8 u8OdMode; 253 }MST_MFC_MiuBaseAddr_t, *PMST_MFC_MiuBaseAddr_t; 254 255 typedef struct MST_FRC_SYS_INFO_s 256 { 257 //PMST_PANEL_INFO_t pPanelInfo; // panel information 258 MS_U16 u16HStart; //ursa scaler 259 MS_U16 u16VStart; //ursa scaler 260 MS_U16 u16Width; //ursa scaler 261 MS_U16 u16Height; //ursa scaler 262 MS_U16 u16HTotal; //ursa scaler 263 MS_U16 u16VTotal; //ursa scaler 264 265 //titania to URSA 266 MS_U8 u8LVDSTxChannel; //Single, Dual 267 MS_U8 u8LVDSTxBitNum; //8bits, 10 bits 268 MS_U8 u8LVDSTxTiMode; //Thin/Ti mode scaler 40-bit2 269 MS_U8 u8LVDSTxSwapMsbLsb; //ursa scaler 270 MS_U8 u8LVDSTxSwap_P_N; //ursa scaler 271 MS_U8 u8LVDSTxSwapOddEven; //ursa scaler 272 273 //URSA to Panel info 274 MS_U8 u8PanelVfreq; //Panel frame rate 60Hz, 120Hz, 240Hz 275 MS_U8 u8PanelChannel; //Single, Dual, Quad, Quad_LR 276 MS_U8 u8PanelLVDSSwapCH; //LVDS chenel swap ABCD 277 MS_U8 u8PanelBitNum; //Panel bit number 278 MS_U8 u8PanelLVDSShiftPair; //ursa scaler 279 MS_U8 u8PanelLVDSTiMode; //Panel TI/Thin mode 280 MS_U8 u8PanelLVDSSwapPol; //Panel LVDS polarity swap 281 MS_U8 u8PanelLVDSSwapPair; //Panel LVDS pair swap 282 283 MS_U16 u16MFCMemoryClk; //MFC memory clock MHz 284 MS_U16 u16MFCMemoryType; //MFC memory type 285 MS_U8 u8PanelIncVtotalFor50Hz; //Change Vtotal for DCLK 286 MS_U8 u8PanelType; //TTL, Mini_LVDS, LVDS 287 MS_U8 u8PanelDither; 288 MS_U8 u8PanelBlankCPVC; //Panel Mini LVDS use 289 MS_U8 u8PanelBlankOEC; //Panel Mini LVDS use 290 MS_U8 u8PanelBlankTPC; //Panel Mini LVDS use 291 MS_U8 u8PanelBlankSTHC; //Panel Mini LVDS use 292 MS_U8 u8PanelCSC; //LVDS CSC enable/disable 293 MS_U8 u8PanelGAMMA; //Panel GAMMA enable/disable 294 MS_U8 u8UseMPIF; 295 }MST_FRC_SYS_INFO_t, *PMST_FRC_SYS_INFO_t; 296 297 typedef struct __attribute__((packed)) 298 { 299 MS_PHY PhyAddr; 300 MS_U16 u16MaxCmdCnt; 301 MS_BOOL bEnable; 302 }MS_AutoDownLoad_Info; 303 304 typedef struct 305 { 306 MS_U32 u32B; 307 MS_U32 u32G; 308 MS_U32 u32R; 309 MS_U32 u32Enable; 310 } MS_FRC_ADLG_TBL; 311 312 typedef enum 313 { 314 E_FRC_PNL_TYPE_2D = 0, 315 E_FRC_PNL_TYPE_PASSIVE, 316 E_FRC_PNL_TYPE_ACTIVE, 317 E_FRC_PNL_TYPE_PDP, 318 E_FRC_PANEL_3D_TYPE_ACTIVE_240_1920_540 =9, 319 } E_FRC_3D_PANEL_TYPE; 320 321 typedef enum 322 { 323 E_FRC_INPUT_2D = 0, // 2D 324 E_FRC_INPUT_3D_SBS = 1, // side by side 325 E_FRC_INPUT_3D_TD = 2, // Top-Down 326 E_FRC_INPUT_3D_CB = 3, // Check Board 327 E_FRC_INPUT_3D_FI = 4, // Frame Interleave 328 E_FRC_INPUT_3D_LA = 6, // Line Alternative 329 E_FRC_INPUT_3D_FPP = 7, // Frame Packing 330 }E_FRC_3D_INPUT_FMT; 331 332 typedef enum 333 { 334 E_FRC_3D_CFG_NORMAL = 0, // normal 3D 335 E_FRC_3D_CFG_LR_SWAP, // L/R swap 336 E_FRC_3D_CFG_L_ONLY, // Only L side 337 E_FRC_3D_CFG_R_ONLY, // Only R side 338 }E_FRC_3D_MODE_CFG; 339 340 typedef enum 341 { 342 E_FRC_COLOR_PATH_RGB_444 = 0, 343 E_FRC_COLOR_PATH_RGB_422, 344 } E_FRC_COLOR_PATH; 345 346 typedef struct 347 { 348 MS_U16 u16RedGain; 349 MS_U16 u16GreenGain; 350 MS_U16 u16BlueGain; 351 352 MS_U16 u16RedOffset; 353 MS_U16 u16GreenOffset; 354 MS_U16 u16BlueOffset; 355 }MS_FRC_RGBGAINOFFSET_INFO; 356 357 #define FRC_NOTSUPPORT_MODE 0xFFFF 358 359 //------------------------------------------------------------------------------------------------- 360 // Function and Variable 361 //------------------------------------------------------------------------------------------------- 362 void MDrv_FRC_ByPass_Enable(void *pInstance, MS_BOOL bEnable); 363 364 void MDrv_FRC_Tx_SetTgen(void *pInstance, PMST_PANEL_INFO_t pPanelInfo); 365 void MDrv_FRC_TGEN_SetHTotal(void *pInstance, MS_U16 u16HTotal); 366 void MDrv_FRC_TGEN_SetVTotal(void *pInstance, MS_U16 u16VTotal); 367 368 void MDrv_FRC_SetMemFormat(void *pInstance, PFRC_INFO_t pFRCInfo); 369 void MDrv_FRC_IPM_Init(void *pInstance, PMST_PANEL_INFO_t pPanelInfo, PFRC_INFO_t pFRCInfo); 370 void MDrv_FRC_IPM_SetOffset(void *pInstance, MS_U16 offset); 371 void MDrv_FRC_IPM_SetFetchNum(void *pInstance, MS_U16 fetch); 372 void MDrv_FRC_OPM_Init(void *pInstance); 373 void MDrv_FRC_OPM_SetOffset(void *pInstance, MS_U16 offset); 374 void MDrv_FRC_OPM_SetFetchNum(void *pInstance, MS_U16 fetch); 375 void MDrv_FRC_Init(void *pInstance, PMST_PANEL_INFO_t pPanelInfo, PFRC_INFO_t pFRCInfo); 376 void MDrv_FRC_Set_3D_QMap(void *pInstance, MS_U8 u8FRC3DPanelType, MS_U16 u16sc_in_3dformat, MS_U16 u16sc_out_3dformat, MS_U8 u83D_FI_out); 377 void MDrv_FRC_AutoDownLoad_init(MS_PHY PhyAddr, MS_U32 u32BufByteLen); //NO_USE 378 void MDrv_FRC_ADLG_Trigger(FRC_CLIENT_TABLE client,MS_PHY startAddr, MS_U16 u16CmdCnt); //NO_USE 379 void MDrv_FRC_ADLG_WritetoDRAM(FRC_CLIENT_TABLE client,MS_U8 *pR, MS_U8 *pG, MS_U8 *pB, MS_U16 u16Count, MS_U16 *pMaxGammaValue); //NO_USE 380 void MDrv_FRC_SetGammaTbl(MS_U8* pu8GammaTab[3]); //NO_USE 381 void MDrv_FRC_ADLG_Fire(FRC_CLIENT_TABLE client,MS_U8 *pR, MS_U8 *pG, MS_U8 *pB, MS_U16 u16Count, MS_U16 *pMaxGammaValue); //NO_USE 382 void MDrv_FRC_OPM_SetBaseOfset(void *pInstance, FRC_INFO_t *FRCInfo, E_XC_3D_OUTPUT_MODE u16out_3dformat); 383 384 MS_BOOL MDrv_XC_SendCmdToFRC(void *pInstance, MS_U8 u8Cmd, MS_U8 count, FRC_R2_CMD_PARAMETER_t pFRC_R2_Para ); 385 MS_BOOL MDrv_XC_GetMsgFromFRC(void *pInstance, MS_U8* pu8Cmd, MS_U8* pu8ParaCount, MS_U8* pu8Para); 386 387 void MDrv_XC_set_OC_Reg(void *pInstance, PMST_PANEL_INFO_t pPanelInfo); 388 389 void MDrv_FRC_OP2_ColorMatrixEn(void *pInstance, MS_BOOL bEnable); 390 void MDrv_FRC_OP2_CscDitherEn(void *pInstance, MS_BOOL bEnable); 391 void MDrv_FRC_OP2_BrightnessEn(void *pInstance, MS_BOOL bEnable); 392 void MDrv_FRC_OP2_ContrastEn(void *pInstance, MS_BOOL bEnable); 393 void MDrv_FRC_OP2_NoiseRoundEn(void *pInstance, MS_BOOL bEnable); 394 void MDrv_FRC_OP2_SetRGBGain(void *pInstance, MS_U16 u16RedGain, MS_U16 u16GreenGain, MS_U16 u16BlueGain); 395 void MDrv_FRC_OP2_SetRGBOffset(void *pInstance, MS_U16 u16RedOffset, MS_U16 u16GreenOffset, MS_U16 u16BlueOffset); 396 void MDrv_FRC_OP2_SetDither(void *pInstance, MS_U16 u16dither); 397 void MDrv_FRC_HSU_SetScalingSize(void *pInstance, MS_U16 input, MS_U16 output); 398 void MDrv_FRC_VSU_SetScalingSize(void *pInstance, MS_U16 input, MS_U16 output); 399 void MDrv_FRC_CSC_SelectPath(void *pInstance, MS_U8 type); 400 401 void MDrv_FRC_PNLInfo_Transform(void *pInstance, XC_PANEL_INFO *XC_PNLInfo, XC_PREINIT_INFO_t *XC_PNLInfo_Adv, MST_PANEL_INFO_t *PanelInfo); 402 void MDrv_XC_FRC_SetWindow(void *pInstance, E_XC_3D_INPUT_MODE e3dInputMode, E_XC_3D_OUTPUT_MODE e3dOutputMode, E_XC_3D_PANEL_TYPE e3dPanelType); 403 void MDrv_FRC_Mute(void *pInstance, MS_BOOL bEnable); 404 MS_BOOL MDrv_XC_Set_FRC_InputTiming(void *pInstance, E_XC_FRC_InputTiming enFRC_InputTiming); 405 void MDrv_FRC_UpdateMDE(void *pInstance, MS_WINDOW_TYPE stDisplayWin); 406 void MDrv_XC_FRC_Set_Input3DFormat(void *pInstance, E_XC_3D_INPUT_MODE enFrcInput3DType); 407 MS_BOOL MDrv_XC_FRC_R2_Set_InputFrameSize(void *pInstance, MS_U16 u16HSize, MS_U16 u16VSize ); 408 MS_BOOL MDrv_XC_FRC_R2_Set_OutputFrameSize(void *pInstance, MS_U16 u16HSize, MS_U16 u16VSize ); 409 MS_BOOL MDrv_FRC_IsDdr4Dram(void *pInstance,PFRC_INFO_t pFRCInfo); 410 void MDrv_FRC_SetMemoryAddress(void *pInstance, PXC_FRC_ADDRESS_INFO pFRCAddrInfo); 411 412 #endif 413