1 /*
2 * Copyright (C) 2010-2017 ARM Limited. All rights reserved.
3 *
4 * This program is free software and is provided to you under the terms of the GNU General Public License version 2
5 * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
6 *
7 * A copy of the licence is included with the program, and can also be obtained from Free Software
8 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
9 */
10
11 /**
12 * @file mali_pmu.c
13 * Mali driver functions for Mali 400 PMU hardware
14 */
15 #include "mali_hw_core.h"
16 #include "mali_pmu.h"
17 #include "mali_pp.h"
18 #include "mali_kernel_common.h"
19 #include "mali_osk.h"
20 #include "mali_pm.h"
21 #include "mali_osk_mali.h"
22
23 struct mali_pmu_core *mali_global_pmu_core = NULL;
24
25 static _mali_osk_errcode_t mali_pmu_wait_for_command_finish(
26 struct mali_pmu_core *pmu);
27
mali_pmu_create(_mali_osk_resource_t * resource)28 struct mali_pmu_core *mali_pmu_create(_mali_osk_resource_t *resource)
29 {
30 struct mali_pmu_core *pmu;
31
32 MALI_DEBUG_ASSERT(NULL == mali_global_pmu_core);
33 MALI_DEBUG_PRINT(2, ("Mali PMU: Creating Mali PMU core\n"));
34
35 pmu = (struct mali_pmu_core *)_mali_osk_malloc(
36 sizeof(struct mali_pmu_core));
37 if (NULL != pmu) {
38 pmu->registered_cores_mask = 0; /* to be set later */
39
40 if (_MALI_OSK_ERR_OK == mali_hw_core_create(&pmu->hw_core,
41 resource, PMU_REGISTER_ADDRESS_SPACE_SIZE)) {
42
43 pmu->switch_delay = _mali_osk_get_pmu_switch_delay();
44
45 mali_global_pmu_core = pmu;
46
47 return pmu;
48 }
49 _mali_osk_free(pmu);
50 }
51
52 return NULL;
53 }
54
mali_pmu_delete(struct mali_pmu_core * pmu)55 void mali_pmu_delete(struct mali_pmu_core *pmu)
56 {
57 MALI_DEBUG_ASSERT_POINTER(pmu);
58 MALI_DEBUG_ASSERT(pmu == mali_global_pmu_core);
59
60 MALI_DEBUG_PRINT(2, ("Mali PMU: Deleting Mali PMU core\n"));
61
62 mali_global_pmu_core = NULL;
63
64 mali_hw_core_delete(&pmu->hw_core);
65 _mali_osk_free(pmu);
66 }
67
mali_pmu_set_registered_cores_mask(struct mali_pmu_core * pmu,u32 mask)68 void mali_pmu_set_registered_cores_mask(struct mali_pmu_core *pmu, u32 mask)
69 {
70 pmu->registered_cores_mask = mask;
71 }
72
mali_pmu_reset(struct mali_pmu_core * pmu)73 void mali_pmu_reset(struct mali_pmu_core *pmu)
74 {
75 MALI_DEBUG_ASSERT_POINTER(pmu);
76 MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0);
77
78 /* Setup the desired defaults */
79 mali_hw_core_register_write_relaxed(&pmu->hw_core,
80 PMU_REG_ADDR_MGMT_INT_MASK, 0);
81 mali_hw_core_register_write_relaxed(&pmu->hw_core,
82 PMU_REG_ADDR_MGMT_SW_DELAY, pmu->switch_delay);
83 }
84
mali_pmu_power_up_all(struct mali_pmu_core * pmu)85 void mali_pmu_power_up_all(struct mali_pmu_core *pmu)
86 {
87 u32 stat;
88
89 MALI_DEBUG_ASSERT_POINTER(pmu);
90 MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0);
91
92 mali_pm_exec_lock();
93
94 mali_pmu_reset(pmu);
95
96 /* Now simply power up the domains which are marked as powered down */
97 stat = mali_hw_core_register_read(&pmu->hw_core,
98 PMU_REG_ADDR_MGMT_STATUS);
99 mali_pmu_power_up(pmu, stat);
100
101 mali_pm_exec_unlock();
102 }
103
mali_pmu_power_down_all(struct mali_pmu_core * pmu)104 void mali_pmu_power_down_all(struct mali_pmu_core *pmu)
105 {
106 u32 stat;
107
108 MALI_DEBUG_ASSERT_POINTER(pmu);
109 MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0);
110
111 mali_pm_exec_lock();
112
113 /* Now simply power down the domains which are marked as powered up */
114 stat = mali_hw_core_register_read(&pmu->hw_core,
115 PMU_REG_ADDR_MGMT_STATUS);
116 mali_pmu_power_down(pmu, (~stat) & pmu->registered_cores_mask);
117
118 mali_pm_exec_unlock();
119 }
120
mali_pmu_power_down(struct mali_pmu_core * pmu,u32 mask)121 _mali_osk_errcode_t mali_pmu_power_down(struct mali_pmu_core *pmu, u32 mask)
122 {
123 u32 stat;
124 _mali_osk_errcode_t err;
125
126 MALI_DEBUG_ASSERT_POINTER(pmu);
127 MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0);
128 MALI_DEBUG_ASSERT(mask <= pmu->registered_cores_mask);
129 MALI_DEBUG_ASSERT(0 == (mali_hw_core_register_read(&pmu->hw_core,
130 PMU_REG_ADDR_MGMT_INT_RAWSTAT) &
131 PMU_REG_VAL_IRQ));
132
133 MALI_DEBUG_PRINT(3,
134 ("PMU power down: ...................... [%s]\n",
135 mali_pm_mask_to_string(mask)));
136
137 stat = mali_hw_core_register_read(&pmu->hw_core,
138 PMU_REG_ADDR_MGMT_STATUS);
139
140 /*
141 * Assert that we are not powering down domains which are already
142 * powered down.
143 */
144 MALI_DEBUG_ASSERT(0 == (stat & mask));
145
146 mask &= ~(0x1 << MALI_DOMAIN_INDEX_DUMMY);
147
148 if (0 == mask || 0 == ((~stat) & mask)) return _MALI_OSK_ERR_OK;
149
150 mali_hw_core_register_write(&pmu->hw_core,
151 PMU_REG_ADDR_MGMT_POWER_DOWN, mask);
152
153 /*
154 * Do not wait for interrupt on Mali-300/400 if all domains are
155 * powered off by our power down command, because the HW will simply
156 * not generate an interrupt in this case.
157 */
158 if (mali_is_mali450() || mali_is_mali470() || pmu->registered_cores_mask != (mask | stat)) {
159 err = mali_pmu_wait_for_command_finish(pmu);
160 if (_MALI_OSK_ERR_OK != err) {
161 return err;
162 }
163 } else {
164 mali_hw_core_register_write(&pmu->hw_core,
165 PMU_REG_ADDR_MGMT_INT_CLEAR, PMU_REG_VAL_IRQ);
166 }
167
168 #if defined(DEBUG)
169 /* Verify power status of domains after power down */
170 stat = mali_hw_core_register_read(&pmu->hw_core,
171 PMU_REG_ADDR_MGMT_STATUS);
172 MALI_DEBUG_ASSERT(mask == (stat & mask));
173 #endif
174
175 return _MALI_OSK_ERR_OK;
176 }
177
mali_pmu_power_up(struct mali_pmu_core * pmu,u32 mask)178 _mali_osk_errcode_t mali_pmu_power_up(struct mali_pmu_core *pmu, u32 mask)
179 {
180 u32 stat;
181 _mali_osk_errcode_t err;
182 #if !defined(CONFIG_MALI_PMU_PARALLEL_POWER_UP)
183 u32 current_domain;
184 #endif
185
186 MALI_DEBUG_ASSERT_POINTER(pmu);
187 MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0);
188 MALI_DEBUG_ASSERT(mask <= pmu->registered_cores_mask);
189 MALI_DEBUG_ASSERT(0 == (mali_hw_core_register_read(&pmu->hw_core,
190 PMU_REG_ADDR_MGMT_INT_RAWSTAT) &
191 PMU_REG_VAL_IRQ));
192
193 MALI_DEBUG_PRINT(3,
194 ("PMU power up: ........................ [%s]\n",
195 mali_pm_mask_to_string(mask)));
196
197 stat = mali_hw_core_register_read(&pmu->hw_core,
198 PMU_REG_ADDR_MGMT_STATUS);
199 stat &= pmu->registered_cores_mask;
200
201 mask &= ~(0x1 << MALI_DOMAIN_INDEX_DUMMY);
202 if (0 == mask || 0 == (stat & mask)) return _MALI_OSK_ERR_OK;
203
204 /*
205 * Assert that we are only powering up domains which are currently
206 * powered down.
207 */
208 MALI_DEBUG_ASSERT(mask == (stat & mask));
209
210 #if defined(CONFIG_MALI_PMU_PARALLEL_POWER_UP)
211 mali_hw_core_register_write(&pmu->hw_core,
212 PMU_REG_ADDR_MGMT_POWER_UP, mask);
213
214 err = mali_pmu_wait_for_command_finish(pmu);
215 if (_MALI_OSK_ERR_OK != err) {
216 return err;
217 }
218 #else
219 for (current_domain = 1;
220 current_domain <= pmu->registered_cores_mask;
221 current_domain <<= 1) {
222 if (current_domain & mask & stat) {
223 mali_hw_core_register_write(&pmu->hw_core,
224 PMU_REG_ADDR_MGMT_POWER_UP,
225 current_domain);
226
227 err = mali_pmu_wait_for_command_finish(pmu);
228 if (_MALI_OSK_ERR_OK != err) {
229 return err;
230 }
231 }
232 }
233 #endif
234
235 #if defined(DEBUG)
236 /* Verify power status of domains after power up */
237 stat = mali_hw_core_register_read(&pmu->hw_core,
238 PMU_REG_ADDR_MGMT_STATUS);
239 MALI_DEBUG_ASSERT(0 == (stat & mask));
240 #endif /* defined(DEBUG) */
241
242 return _MALI_OSK_ERR_OK;
243 }
244
mali_pmu_wait_for_command_finish(struct mali_pmu_core * pmu)245 static _mali_osk_errcode_t mali_pmu_wait_for_command_finish(
246 struct mali_pmu_core *pmu)
247 {
248 u32 rawstat;
249 u32 timeout = MALI_REG_POLL_COUNT_SLOW;
250
251 MALI_DEBUG_ASSERT(pmu);
252
253 /* Wait for the command to complete */
254 do {
255 rawstat = mali_hw_core_register_read(&pmu->hw_core,
256 PMU_REG_ADDR_MGMT_INT_RAWSTAT);
257 --timeout;
258 } while (0 == (rawstat & PMU_REG_VAL_IRQ) && 0 < timeout);
259
260 MALI_DEBUG_ASSERT(0 < timeout);
261
262 if (0 == timeout) {
263 return _MALI_OSK_ERR_TIMEOUT;
264 }
265
266 mali_hw_core_register_write(&pmu->hw_core,
267 PMU_REG_ADDR_MGMT_INT_CLEAR, PMU_REG_VAL_IRQ);
268
269 return _MALI_OSK_ERR_OK;
270 }
271