1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Dingxian Wen <shawn.wen@rock-chips.com> 6 */ 7 8 #ifndef _LT8619C_H 9 #define _LT8619C_H 10 11 /* --------------- configuration -------------------- */ 12 #define CLK_SRC XTAL_CLK 13 #define REF_RESISTANCE EXT_RESISTANCE 14 #define CP_CONVERT_MODE HDPC 15 #define YUV_COLORDEPTH OUTPUT_16BIT_LOW 16 #define BT_TX_SYNC_POL BT_TX_SYNC_POSITIVE 17 18 /* -------------------------------------------------- */ 19 #define LT8619C_CHIPID 0x1604B0 20 21 #define EDID_NUM_BLOCKS_MAX 2 22 #define EDID_BLOCK_SIZE 128 23 #define POLL_INTERVAL_MS 1000 24 #define lt8619c_PIXEL_RATE 400000000 25 26 #define BANK_REG 0xff 27 #define BANK_60 0x60 28 #define BANK_80 0x80 29 #define CHIPID_REG_H 0x00 30 #define CHIPID_REG_M 0x01 31 #define CHIPID_REG_L 0x02 32 #define LT8619C_MAX_REGISTER 0xff 33 34 #define WAIT_MAX_TIMES 10 35 36 #define BT656_OUTPUT 0x04 37 #define BT1120_OUTPUT 0x03 38 #define BT1120_8BIT_OUTPUT 0x05 39 40 #define BT_TX_SYNC_POSITIVE 0x30 41 #define BT_TX_SYNC_NEGATIVE 0x00 42 43 #define PROGRESSIVE_INDICATOR 0x00 44 #define INTERLACE_INDICATOR 0x08 45 46 /* 0x08: Use xtal clk; 0x18: Use internal clk */ 47 #define XTAL_CLK 0x08 48 #define INT_CLK 0x18 49 50 /* internal resistance */ 51 #define INT_RESISTANCE 0x88 52 /* external resistance(Pin 16 - REXT, 2K resistance) */ 53 #define EXT_RESISTANCE 0x80 54 55 #define CLK_SDRMODE 0 56 /* CLK divided by 2 */ 57 #define CLK_DDRMODE 1 58 59 #define SDTV 0x00 60 #define SDPC 0x10 61 #define HDTV 0x20 62 #define HDPC 0x30 63 64 /* 65 * enable 66 * D0 ~ D7 Y ; D8 ~ D15 C 67 * D8 ~ D15 Y ; D16 ~ D23 C 68 */ 69 #define YC_SWAP_EN 0x08 70 /* 71 * disable 72 * D0 ~ D7 C ; D8 ~ D15 Y 73 * D8 ~ D15 C ; D16 ~ D23 Y 74 */ 75 #define YC_SWAP_DIS 0x00 76 77 /* 78 * BT1120 24bit / BT656 12bit 79 * when YC_SWAP_EN: 80 * BT656 12bit D0 ~ D11 81 * BT1120 24bit : D0 ~ D11 Y ; D12 ~ D23 C 82 * when YC_SWAP_DIS: 83 * BT656 12bit D12 ~ D23 84 * BT1120 24bit : D0 ~ D11 C ; D12 ~ D23 Y 85 */ 86 #define OUTPUT_24BIT 0x00 87 88 /* 89 * BT1120 20bit / BT656 10bit 90 * when YC_SWAP_EN: 91 * BT656 10bit D4 ~ D13 92 * BT1120 20bit : D4 ~ D13 Y ; D14 ~ D23 C 93 * when YC_SWAP_DIS: 94 * BT656 10bit D14 ~ D23 95 * BT1120 20bit : D4 ~ D13 C ; D14 ~ D23 Y 96 */ 97 #define OUTPUT_20BIT_HIGH 0x04 98 /* 99 * when YC_SWAP_EN: 100 * BT656 10bit D0 ~ D9 101 * BT1120 20bit : D0 ~ D9 Y ; D10 ~ D19 C 102 * when YC_SWAP_DIS: 103 * BT656 10bit D10 ~ D19 104 * BT1120 20bit : D0 ~ D9 C ; D10 ~ D19 Y 105 */ 106 #define OUTPUT_20BIT_LOW 0x05 107 108 /* 109 * BT1120 16bit / BT656 8bit 110 * when YC_SWAP_EN: 111 * BT656 8bit D8 ~ D15 112 * BT1120 16bit : D8 ~ D15 Y ; D16 ~ D23 C 113 * when YC_SWAP_DIS: 114 * BT656 8bit D16 ~ D23 115 * BT1120 16bit : D8 ~ D15 C ; D16 ~ D23 Y 116 */ 117 #define OUTPUT_16BIT_HIGH 0x06 118 /* 119 * when YC_SWAP_EN: 120 * BT656 8bit D0 ~ D7 121 * BT1120 16bit : D0 ~ D7 Y ; D8 ~ D15 C 122 * when YC_SWAP_DIS: 123 * BT656 8bit D8 ~ D15 124 * BT1120 16bit : D0 ~ D7 C ; D8 ~ D15 Y 125 */ 126 #define OUTPUT_16BIT_LOW 0x07 127 128 /* ---------------- regs ----------------- */ 129 /* reg: 0x60_60 */ 130 #define SYNC_POL_MASK GENMASK(5, 4) 131 #define IP_SEL_MASK GENMASK(3, 3) 132 #define OUTPUT_MODE_MASK GENMASK(2, 0) 133 134 /* reg: 0x80_05 */ 135 #define RGD_HS_POL_ADJ_MASK GENMASK(5, 5) 136 #define RGD_VS_POL_ADJ_MASK GENMASK(4, 4) 137 138 /* reg: 0x80_17 */ 139 #define RGOD_VID_HSPOL BIT(7) 140 #define RGOD_VID_VSPOL BIT(6) 141 142 #endif 143