xref: /rk3399_ARM-atf/plat/ti/k3low/common/drivers/k3-ddrss/lpddr4_16bit_sanity.h (revision 6c0c3a74dda68e7ffc8bd6c156918ddbfea7e03a)
1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*
3  * Cadence DDR Driver
4  *
5  * Copyright (C) 2012-2026 Cadence Design Systems, Inc.
6  * Copyright (C) 2018-2026 Texas Instruments Incorporated - https://www.ti.com/
7  */
8 
9 #ifndef LPDDR4_16BIT_SANITY_H
10 #define LPDDR4_16BIT_SANITY_H
11 
12 #include <errno.h>
13 #include <inttypes.h>
14 #include <lpddr4_if.h>
15 
ti_lpddr4_intr_ctlint_sf(const ti_lpddr4_privatedata * pd,const ti_lpddr4_intr_ctlinterrupt intr,const bool * irqstatus)16 static inline uint32_t ti_lpddr4_intr_ctlint_sf(const ti_lpddr4_privatedata *pd,
17 						 const ti_lpddr4_intr_ctlinterrupt intr,
18 						 const bool *irqstatus)
19 {
20 	uint32_t ret = 0;
21 
22 	if (pd == NULL) {
23 		return (uint32_t)EINVAL;
24 	} else if (irqstatus == NULL) {
25 		return (uint32_t)EINVAL;
26 	} else if ((uint32_t)intr > (uint32_t)LPDDR4_INTR_LOR_BITS) {
27 		return (uint32_t)EINVAL;
28 	}
29 
30 	return ret;
31 }
32 
ti_lpddr4_intr_ack_ctlint_sf(const ti_lpddr4_privatedata * pd,const ti_lpddr4_intr_ctlinterrupt intr)33 static inline uint32_t ti_lpddr4_intr_ack_ctlint_sf(const ti_lpddr4_privatedata *pd,
34 						     const ti_lpddr4_intr_ctlinterrupt intr)
35 {
36 	uint32_t ret = 0;
37 
38 	if (pd == NULL) {
39 		return (uint32_t)EINVAL;
40 	} else if ((uint32_t)intr > (uint32_t)LPDDR4_INTR_LOR_BITS) {
41 		return (uint32_t)EINVAL;
42 	}
43 
44 	return ret;
45 }
46 
ti_lpddr4_intr_phyint_sf(const ti_lpddr4_privatedata * pd,const ti_lpddr4_intr_phyindepinterrupt intr,const bool * irqstatus)47 static inline uint32_t ti_lpddr4_intr_phyint_sf(const ti_lpddr4_privatedata *pd,
48 						 const ti_lpddr4_intr_phyindepinterrupt intr,
49 						 const bool *irqstatus)
50 {
51 	uint32_t ret = 0;
52 
53 	if (pd == NULL) {
54 		return (uint32_t)EINVAL;
55 	} else if (irqstatus == NULL) {
56 		return (uint32_t)EINVAL;
57 	} else if ((uint32_t)intr > (uint32_t)LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT) {
58 		return (uint32_t)EINVAL;
59 	}
60 
61 	return ret;
62 }
63 
ti_lpddr4_intr_ack_phyint_sf(const ti_lpddr4_privatedata * pd,const ti_lpddr4_intr_phyindepinterrupt intr)64 static inline uint32_t ti_lpddr4_intr_ack_phyint_sf(const ti_lpddr4_privatedata *pd,
65 						     const ti_lpddr4_intr_phyindepinterrupt intr)
66 {
67 	uint32_t ret = 0;
68 
69 	if (pd == NULL) {
70 		return (uint32_t)EINVAL;
71 	} else if ((uint32_t)intr > (uint32_t)LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT) {
72 		return (uint32_t)EINVAL;
73 	}
74 
75 	return ret;
76 }
77 
78 #endif  /* LPDDR4_16BIT_SANITY_H */
79