1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 #ifndef __IAM20680_H 6 #define __IAM20680_H 7 8 #include <linux/ioctl.h> 9 /**add***/ 10 #define IAM20680_PRECISION 16 11 #define IAM20680_RANGE 2000000 12 13 #define IAM20680_SMPLRT_DIV 0x19 14 #define IAM20680_CONFIG 0x1A 15 #define IAM20680_GYRO_CONFIG 0x1B 16 #define IAM20680_ACCEL_CONFIG 0x1C 17 #define IAM20680_ACCEL_CONFIG2 0x1D 18 #define IAM20680_LP_ACCEL_ODR 0x1E 19 #define IAM20680_WOM_THRESH 0x1F 20 #define IAM20680_FIFO_EN 0x23 21 #define IAM20680_INT_PIN_CFG 0x37 22 #define IAM20680_INT_ENABLE 0x38 23 #define IAM20680_DMP_INT_STATUS 0x39 24 #define IAM20680_INT_STATUS 0x3A 25 #define IAM20680_ACCEL_XOUT_H 0x3B 26 #define IAM20680_TEMP_OUT_H 0x41 27 #define IAM20680_GYRO_XOUT_H 0x43 28 #define IAM20680_ACCEL_INTEL_CTRL 0x69 29 #define IAM20680_USER_CTRL 0x6A 30 #define IAM20680_PWR_MGMT_1 0x6B 31 #define IAM20680_PWR_MGMT_2 0x6C 32 #define IAM20680_PRGM_STRT_ADDRH 0x70 33 #define IAM20680_FIFO_COUNTH 0x72 34 #define IAM20680_FIFO_R_W 0x74 35 #define IAM20680_WHOAMI 0x75 36 37 #define IAM20680_DEVICE_ID 0xA9 38 /* 39 * IAM20680_CONFIG 40 */ 41 #define DLPF_CFG_250HZ 0x00 42 #define DLPF_CFG_184HZ 0x01 43 #define DLPF_CFG_98HZ 0x02 44 #define DLPF_CFG_41HZ 0x03 45 #define DLPF_CFG_20HZ 0x04 46 #define DLPF_CFG_10HZ 0x05 47 #define DLPF_CFG_5HZ 0x06 48 #define DLPF_CFG_3600HZ 0x07 49 #define EXT_SYNC_SET_TEMP 0x08 50 #define EXT_SYNC_SET_GYRO_X 0x10 51 #define EXT_SYNC_SET_GYRO_Y 0x18 52 #define EXT_SYNC_SET_GYRO_Z 0x20 53 #define EXT_SYNC_SET_ACCEL_X 0x28 54 #define EXT_SYNC_SET_ACCEL_Y 0x30 55 #define EXT_SYNC_SET_ACCEL_Z 0x38 56 57 58 /* 59 * IAM20680_GYRO_CONFIG 60 */ 61 #define GFSR_250DPS (0<<3) 62 #define GFSR_500DPS (1<<3) 63 #define GFSR_1000DPS (2<<3) 64 #define GFSR_2000DPS (3<<3) 65 66 /* 67 * IAM20680_ACCEL_CONFIG 68 */ 69 #define AFSR_2G (0<<3) 70 #define AFSR_4G (1<<3) 71 #define AFSR_8G (2<<3) 72 #define AFSR_16G (3<<3) 73 74 75 /* 76 * IAM20680_ACCEL_CONFIG2 77 */ 78 #define A_DLPF_CFG_460HZ 0x00 79 #define A_DLPF_CFG_184HZ 0x01 80 #define A_DLPF_CFG_92HZ 0x02 81 #define A_DLPF_CFG_41HZ 0x03 82 #define A_DLPF_CFG_20HZ 0x04 83 #define A_DLPF_CFG_10HZ 0x05 84 #define A_DLPF_CFG_5HZ 0x06 85 //#define A_DLPF_CFG_460HZ 0x07 86 #define BIT_FIFO_SIZE_1K 0x40 87 #define BIT_ACCEL_FCHOICE_B 0x08 88 89 90 /* 91 * IAM20680_LP_ACCEL_ODR 92 */ 93 #define LPA_CLK_P24HZ 0x0 94 #define LPA_CLK_P49HZ 0x1 95 #define LPA_CLK_P98HZ 0x2 96 #define LPA_CLK_1P95HZ 0x3 97 #define LPA_CLK_3P91HZ 0x4 98 #define LPA_CLK_7P81HZ 0x5 99 #define LPA_CLK_15P63HZ 0x6 100 #define LPA_CLK_31P25HZ 0x7 101 #define LPA_CLK_62P50HZ 0x8 102 #define LPA_CLK_125HZ 0x9 103 #define LPA_CLK_250HZ 0xa 104 #define LPA_CLK_500HZ 0xb 105 106 107 /* 108 * IAM20680_PWR_MGMT_1 109 */ 110 #define BIT_H_RESET (1<<7) 111 #define BIT_SLEEP (1<<6) 112 #define BIT_CYCLE (1<<5) 113 #define BIT_GYRO_STANDBY (1<<4) 114 #define BIT_PD_PTAT (1<<3) 115 #define BIT_CLKSEL (1<<0) 116 117 #define CLKSEL_INTERNAL 0 118 #define CLKSEL_PLL 1 119 120 /* 121 * IAM20680_PWR_MGMT_2 122 */ 123 #define BIT_ACCEL_STBY 0x38 124 #define BIT_GYRO_STBY 0x07 125 #define BITS_LPA_WAKE_CTRL 0xC0 126 #define BITS_LPA_WAKE_1HZ 0x00 127 #define BITS_LPA_WAKE_2HZ 0x40 128 #define BITS_LPA_WAKE_20HZ 0x80 129 130 #define IAM20680_PWRM1_SLEEP 0x40 131 #define IAM20680_PWRM1_GYRO_STANDBY 0x10 132 #define IAM20680_PWRM2_ACCEL_DISABLE 0x38 133 #define IAM20680_PWRM2_GYRO_DISABLE 0x07 134 135 /* 136 * IAM20680_ACCEL_INTEL_CTRL 137 */ 138 #define BIT_ACCEL_INTEL_EN 0x80 139 #define BIT_ACCEL_INTEL_MODE 0x40 140 141 142 /* 143 * IAM20680_USER_CTRL 144 */ 145 #define BIT_FIFO_RST 0x04 146 #define BIT_DMP_RST 0x08 147 #define BIT_I2C_MST_EN 0x20 148 #define BIT_FIFO_EN 0x40 149 #define BIT_DMP_EN 0x80 150 151 152 /* 153 * IAM20680_FIFO_EN 154 */ 155 #define BIT_ACCEL_OUT 0x08 156 #define BITS_GYRO_OUT 0x70 157 158 159 /* 160 * IAM20680_INT_PIN_CFG 161 */ 162 #define BIT_BYPASS_EN 0x2 163 164 /* 165 * IAM20680_INT_EN/INT_STATUS 166 */ 167 #define BIT_FIFO_OVERLOW 0x80 168 #define BIT_MOT_INT 0x40 169 #define BIT_MPU_RDY 0x04 170 #define BIT_DMP_INT 0x02 171 #define BIT_RAW_RDY 0x01 172 173 174 #define DMP_START_ADDR 0x400 175 176 177 178 #define AXIS_NUM 3 179 #define AXIS_ADC_BYTE 2 180 #define SENSOR_PACKET (AXIS_NUM * AXIS_ADC_BYTE) 181 182 183 184 185 186 /* 187 * self-test parameter 188 */ 189 190 #define DEF_ST_PRECISION 1000 191 #define DEF_ST_IAM20680_ACCEL_LPF 2 192 #define DEF_STABLE_TIME_ST 50 193 #define DEF_SELFTEST_GYRO_FS (0 << 3) 194 #define DEF_SELFTEST_ACCEL_FS (2 << 3) 195 #define DEF_SELFTEST_6500_ACCEL_FS (0 << 3) 196 #define DEF_SW_SELFTEST_GYRO_FS GFSR_2000DPS 197 #define DEF_SW_SELFTEST_SENSITIVITY ((2000*DEF_ST_PRECISION)/32768) 198 199 #define DEF_SW_SELFTEST_SAMPLE_COUNT 75 200 #define DEF_SW_SELFTEST_SAMPLE_TIME 75 201 #define DEF_SW_ACCEL_CAL_SAMPLE_TIME 50 202 #define DEF_SW_SKIP_COUNT 10 203 204 #define DEF_ST_6500_STABLE_TIME 20 205 #define BYTES_PER_SENSOR (6) 206 #define DEF_SELFTEST_SAMPLE_RATE 0 207 #define DEF_GYRO_WAIT_TIME 50 208 #define THREE_AXIS (3) 209 #define INIT_ST_SAMPLES 200 210 #define FIFO_COUNT_BYTE (2) 211 #define DEF_ST_TRY_TIMES 2 212 #define REG_6500_XG_ST_DATA 0x0 213 #define REG_6500_XA_ST_DATA 0xD 214 #define BITS_SELF_TEST_EN 0xE0 215 216 #define DEF_ST_SCALE (1L << 15) 217 218 /*---- IAM20680 Self Test Pass/Fail Criteria ----*/ 219 /* Gyro Offset Max Value (dps) */ 220 #define DEF_GYRO_OFFSET_MAX 20 221 /* Gyro Self Test Absolute Limits ST_AL (dps) */ 222 #define DEF_GYRO_ST_AL 60 223 /* Accel Self Test Absolute Limits ST_AL (mg) */ 224 #define DEF_ACCEL_ST_AL_MIN 225 225 #define DEF_ACCEL_ST_AL_MAX 675 226 #define DEF_6500_ACCEL_ST_SHIFT_DELTA 500 227 #define DEF_6500_GYRO_CT_SHIFT_DELTA 500 228 #define DEF_ST_IAM20680_ACCEL_LPF 2 229 #define DEF_ST_6500_ACCEL_FS_MG 2000UL 230 #define DEF_SELFTEST_6500_ACCEL_FS (0 << 3) 231 232 #define DEF_SELFTEST_GYRO_SENS (32768 / 250) 233 234 235 #define GSENSOR_DEV_PATH "/dev/mma8452_daemon" 236 237 #endif 238 239