1 /*
2 * Copyright (c) 2025, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef IDTE3_H
8 #define IDTE3_H
9
10 #ifdef IMAGE_BL31
11 #include <bl31/sync_handle.h>
12 #include <context.h>
13 #include <lib/el3_runtime/cpu_data.h>
14 #define ESR_ELx_ISS(esr) ((esr) & 0x01ffffff)
15
16 /* ISS layout for trapped AArch64 system-register access (ESR_EL3.ISS)
17 *
18 * [21:20] Op0
19 * [19:17] Op2
20 * [16:14] Op1
21 * [13:10] CRn
22 * [9:5] Rt
23 * [4:1] CRm
24 * [0] DIR
25 */
26 #define ISS_SYS64_OP0_SHIFT U(20)
27 #define ISS_SYS64_OP2_SHIFT U(17)
28 #define ISS_SYS64_OP1_SHIFT U(14)
29 #define ISS_SYS64_CRN_SHIFT U(10)
30 #define ISS_SYS64_RT_SHIFT U(5)
31 #define ISS_SYS64_CRM_SHIFT U(1)
32 #define ISS_SYS64_DIR_SHIFT U(0)
33
34 #define ISS_SYS64_OP0_MASK U(0x3)
35 #define ISS_SYS64_OP1_MASK U(0x7)
36 #define ISS_SYS64_OP2_MASK U(0x7)
37 #define ISS_SYS64_CRN_MASK U(0xf)
38 #define ISS_SYS64_RT_MASK ULL(0x1f)
39 #define ISS_SYS64_CRM_MASK U(0xf)
40 #define ISS_SYS64_DIR_MASK U(0x1)
41
42 /* Field extractors */
43 #define ISS_SYS64_OP0(iss) (((iss) >> ISS_SYS64_OP0_SHIFT) & \
44 ISS_SYS64_OP0_MASK)
45
46 #define ISS_SYS64_OP1(iss) (((iss) >> ISS_SYS64_OP1_SHIFT) & \
47 ISS_SYS64_OP1_MASK)
48
49 #define ISS_SYS64_OP2(iss) (((iss) >> ISS_SYS64_OP2_SHIFT) & \
50 ISS_SYS64_OP2_MASK)
51
52 #define ISS_SYS64_CRN(iss) (((iss) >> ISS_SYS64_CRN_SHIFT) & \
53 ISS_SYS64_CRN_MASK)
54
55 #define ISS_SYS64_RT(iss) (((iss) >> ISS_SYS64_RT_SHIFT) & \
56 ISS_SYS64_RT_MASK)
57
58 #define ISS_SYS64_CRM(iss) (((iss) >> ISS_SYS64_CRM_SHIFT) & \
59 ISS_SYS64_CRM_MASK)
60
61 #define ISS_SYS64_DIR(iss) (((iss) >> ISS_SYS64_DIR_SHIFT) & \
62 ISS_SYS64_DIR_MASK)
63
64 #define SYSREG_ESR(op0, op1, crn, crm, op2) \
65 ((UL(op0) << ISS_SYS64_OP0_SHIFT) | \
66 (UL(op1) << ISS_SYS64_OP1_SHIFT) | \
67 (UL(crn) << ISS_SYS64_CRN_SHIFT) | \
68 (UL(crm) << ISS_SYS64_CRM_SHIFT) | \
69 (UL(op2) << ISS_SYS64_OP2_SHIFT))
70
71 #define ESR_EL3_SYSREG_MASK SYSREG_ESR(3, 7, 15, 15, 7)
72
73 #define ESR_EL3_IDREG_ID_PFR0_EL1 SYSREG_ESR(3, 0, 0, 1, 0)
74 #define ESR_EL3_IDREG_ID_PFR1_EL1 SYSREG_ESR(3, 0, 0, 1, 1)
75 #define ESR_EL3_IDREG_ID_DFR0_EL1 SYSREG_ESR(3, 0, 0, 1, 2)
76 #define ESR_EL3_IDREG_ID_AFR0_EL1 SYSREG_ESR(3, 0, 0, 1, 3)
77 #define ESR_EL3_IDREG_ID_MMFR0_EL1 SYSREG_ESR(3, 0, 0, 1, 4)
78 #define ESR_EL3_IDREG_ID_MMFR1_EL1 SYSREG_ESR(3, 0, 0, 1, 5)
79 #define ESR_EL3_IDREG_ID_MMFR2_EL1 SYSREG_ESR(3, 0, 0, 1, 6)
80 #define ESR_EL3_IDREG_ID_MMFR3_EL1 SYSREG_ESR(3, 0, 0, 1, 7)
81
82 #define ESR_EL3_IDREG_ID_ISAR0_EL1 SYSREG_ESR(3, 0, 0, 2, 0)
83 #define ESR_EL3_IDREG_ID_ISAR1_EL1 SYSREG_ESR(3, 0, 0, 2, 1)
84 #define ESR_EL3_IDREG_ID_ISAR2_EL1 SYSREG_ESR(3, 0, 0, 2, 2)
85 #define ESR_EL3_IDREG_ID_ISAR3_EL1 SYSREG_ESR(3, 0, 0, 2, 3)
86 #define ESR_EL3_IDREG_ID_ISAR4_EL1 SYSREG_ESR(3, 0, 0, 2, 4)
87 #define ESR_EL3_IDREG_ID_ISAR5_EL1 SYSREG_ESR(3, 0, 0, 2, 5)
88 #define ESR_EL3_IDREG_ID_MMFR4_EL1 SYSREG_ESR(3, 0, 0, 2, 6)
89 #define ESR_EL3_IDREG_ID_ISAR6_EL1 SYSREG_ESR(3, 0, 0, 2, 7)
90
91 #define ESR_EL3_IDREG_MVFR0_EL1 SYSREG_ESR(3, 0, 0, 3, 0)
92 #define ESR_EL3_IDREG_MVFR1_EL1 SYSREG_ESR(3, 0, 0, 3, 1)
93 #define ESR_EL3_IDREG_MVFR2_EL1 SYSREG_ESR(3, 0, 0, 3, 2)
94 #define ESR_EL3_IDREG_ID_PFR2_EL1 SYSREG_ESR(3, 0, 0, 3, 4)
95 #define ESR_EL3_IDREG_ID_DFR1_EL1 SYSREG_ESR(3, 0, 0, 3, 5)
96 #define ESR_EL3_IDREG_ID_MMFR5_EL1 SYSREG_ESR(3, 0, 0, 3, 6)
97
98 #define ESR_EL3_IDREG_ID_AA64PFR0_EL1 SYSREG_ESR(3, 0, 0, 4, 0)
99 #define ESR_EL3_IDREG_ID_AA64PFR1_EL1 SYSREG_ESR(3, 0, 0, 4, 1)
100 #define ESR_EL3_IDREG_ID_AA64PFR2_EL1 SYSREG_ESR(3, 0, 0, 4, 2)
101 #define ESR_EL3_IDREG_ID_AA64ZFR0_EL1 SYSREG_ESR(3, 0, 0, 4, 4)
102 #define ESR_EL3_IDREG_ID_AA64SMFR0_EL1 SYSREG_ESR(3, 0, 0, 4, 5)
103 #define ESR_EL3_IDREG_ID_AA64FPFR0_EL1 SYSREG_ESR(3, 0, 0, 4, 7)
104
105 #define ESR_EL3_IDREG_ID_AA64DFR0_EL1 SYSREG_ESR(3, 0, 0, 5, 0)
106 #define ESR_EL3_IDREG_ID_AA64DFR1_EL1 SYSREG_ESR(3, 0, 0, 5, 1)
107 #define ESR_EL3_IDREG_ID_AA64DFR2_EL1 SYSREG_ESR(3, 0, 0, 5, 2)
108 #define ESR_EL3_IDREG_ID_AA64AFR0_EL1 SYSREG_ESR(3, 0, 0, 5, 4)
109 #define ESR_EL3_IDREG_ID_AA64AFR1_EL1 SYSREG_ESR(3, 0, 0, 5, 5)
110
111 #define ESR_EL3_IDREG_ID_AA64ISAR0_EL1 SYSREG_ESR(3, 0, 0, 6, 0)
112 #define ESR_EL3_IDREG_ID_AA64ISAR1_EL1 SYSREG_ESR(3, 0, 0, 6, 1)
113 #define ESR_EL3_IDREG_ID_AA64ISAR2_EL1 SYSREG_ESR(3, 0, 0, 6, 2)
114 #define ESR_EL3_IDREG_ID_AA64ISAR3_EL1 SYSREG_ESR(3, 0, 0, 6, 3)
115 #define ESR_EL3_IDREG_ID_AA64MMFR0_EL1 SYSREG_ESR(3, 0, 0, 7, 0)
116
117 #define ESR_EL3_IDREG_ID_AA64MMFR1_EL1 SYSREG_ESR(3, 0, 0, 7, 1)
118 #define ESR_EL3_IDREG_ID_AA64MMFR2_EL1 SYSREG_ESR(3, 0, 0, 7, 2)
119 #define ESR_EL3_IDREG_ID_AA64MMFR3_EL1 SYSREG_ESR(3, 0, 0, 7, 3)
120 #define ESR_EL3_IDREG_ID_AA64MMFR4_EL1 SYSREG_ESR(3, 0, 0, 7, 4)
121
122 /* Group 5 ID Registers trapped*/
123 #define ESR_EL3_IDREG_GMID_EL1 SYSREG_ESR(3, 1, 0, 0, 4)
124
125 #if ENABLE_FEAT_IDTE3
126 void idte3_enable(cpu_context_t *ctx);
127 int handle_idreg_trap(uint64_t esr_el3, cpu_context_t *ctx,
128 u_register_t flags);
129 void idte3_init_cached_idregs_per_world(size_t security_state);
130 void idte3_init_percpu_once_regs(size_t security_state);
131 #else
idte3_enable(cpu_context_t * ctx)132 static inline void idte3_enable(cpu_context_t *ctx)
133 {
134 }
handle_idreg_trap(uint64_t esr_el3,cpu_context_t * ctx,u_register_t flags)135 static inline int handle_idreg_trap(uint64_t esr_el3, cpu_context_t *ctx,
136 u_register_t flags)
137 {
138 return TRAP_RET_UNHANDLED;
139 }
idte3_init_percpu_once_regs(size_t security_state)140 static inline void idte3_init_percpu_once_regs(size_t security_state)
141 {
142 }
idte3_init_cached_idregs_per_world(size_t security_state)143 static inline void idte3_init_cached_idregs_per_world(size_t security_state)
144 {
145 }
146 #endif /* ENABLE_FEAT_IDTE3 */
147 #endif /* IMAGE_BL31 */
148 #endif /* IDTE3_H */
149