1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_EL1_H 8 #define CONTEXT_EL1_H 9 10 #include <lib/extensions/sysreg128.h> 11 12 #ifndef __ASSEMBLER__ 13 14 /******************************************************************************* 15 * EL1 Registers: 16 * AArch64 EL1 system register context structure for preserving the 17 * architectural state during world switches. 18 ******************************************************************************/ 19 20 typedef struct el1_common_regs { 21 uint64_t spsr_el1; 22 uint64_t elr_el1; 23 24 #if (!ERRATA_SPECULATIVE_AT) 25 uint64_t sctlr_el1; 26 uint64_t tcr_el1; 27 #endif /* ERRATA_SPECULATIVE_AT=0 */ 28 29 uint64_t cpacr_el1; 30 uint64_t csselr_el1; 31 uint64_t sp_el1; 32 uint64_t esr_el1; 33 uint64_t mair_el1; 34 uint64_t amair_el1; 35 uint64_t actlr_el1; 36 uint64_t tpidr_el1; 37 uint64_t tpidr_el0; 38 uint64_t tpidrro_el0; 39 uint64_t far_el1; 40 uint64_t afsr0_el1; 41 uint64_t afsr1_el1; 42 uint64_t contextidr_el1; 43 uint64_t vbar_el1; 44 uint64_t mdccint_el1; 45 uint64_t mdscr_el1; 46 sysreg_t par_el1; 47 sysreg_t ttbr0_el1; 48 sysreg_t ttbr1_el1; 49 } el1_common_regs_t; 50 51 typedef struct el1_aarch32_regs { 52 uint64_t spsr_abt; 53 uint64_t spsr_und; 54 uint64_t spsr_irq; 55 uint64_t spsr_fiq; 56 uint64_t dacr32_el2; 57 uint64_t ifsr32_el2; 58 } el1_aarch32_regs_t; 59 60 typedef struct el1_arch_timer_regs { 61 #if NS_TIMER_SWITCH 62 uint64_t cntp_ctl_el0; 63 uint64_t cntp_cval_el0; 64 uint64_t cntv_ctl_el0; 65 uint64_t cntv_cval_el0; 66 #endif 67 uint64_t cntkctl_el1; 68 } el1_arch_timer_regs_t; 69 70 typedef struct el1_mte2_regs { 71 uint64_t tfsre0_el1; 72 uint64_t tfsr_el1; 73 uint64_t rgsr_el1; 74 uint64_t gcr_el1; 75 } el1_mte2_regs_t; 76 77 typedef struct el1_ras_regs { 78 uint64_t disr_el1; 79 } el1_ras_regs_t; 80 81 typedef struct el1_s1pie_regs { 82 uint64_t pire0_el1; 83 uint64_t pir_el1; 84 } el1_s1pie_regs_t; 85 86 typedef struct el1_s1poe_regs { 87 uint64_t por_el1; 88 } el1_s1poe_regs_t; 89 90 typedef struct el1_s2poe_regs { 91 uint64_t s2por_el1; 92 } el1_s2poe_regs_t; 93 94 typedef struct el1_tcr2_regs { 95 uint64_t tcr2_el1; 96 } el1_tcr2_regs_t; 97 98 typedef struct el1_trf_regs { 99 uint64_t trfcr_el1; 100 } el1_trf_regs_t; 101 102 typedef struct el1_csv2_2_regs { 103 uint64_t scxtnum_el0; 104 uint64_t scxtnum_el1; 105 } el1_csv2_2_regs_t; 106 107 typedef struct el1_gcs_regs { 108 uint64_t gcscr_el1; 109 uint64_t gcscre0_el1; 110 uint64_t gcspr_el1; 111 uint64_t gcspr_el0; 112 } el1_gcs_regs_t; 113 114 typedef struct el1_the_regs { 115 sysreg_t rcwmask_el1; 116 sysreg_t rcwsmask_el1; 117 } el1_the_regs_t; 118 119 typedef struct el1_sctlr2_regs { 120 uint64_t sctlr2_el1; 121 } el1_sctlr2_regs_t; 122 123 typedef struct el1_ls64_regs { 124 uint64_t accdata_el1; 125 } el1_ls64_regs_t; 126 127 typedef struct el1_sysregs { 128 129 el1_common_regs_t common; 130 el1_arch_timer_regs_t arch_timer; 131 132 #if CTX_INCLUDE_AARCH32_REGS 133 el1_aarch32_regs_t el1_aarch32; 134 #endif 135 136 #if ENABLE_FEAT_MTE2 137 el1_mte2_regs_t mte2; 138 #endif 139 140 #if ENABLE_FEAT_RAS 141 el1_ras_regs_t ras; 142 #endif 143 144 #if ENABLE_FEAT_S1PIE 145 el1_s1pie_regs_t s1pie; 146 #endif 147 148 #if ENABLE_FEAT_S1POE 149 el1_s1poe_regs_t s1poe; 150 #endif 151 152 #if ENABLE_FEAT_S2POE 153 el1_s2poe_regs_t s2poe; 154 #endif 155 156 #if ENABLE_FEAT_TCR2 157 el1_tcr2_regs_t tcr2; 158 #endif 159 160 #if ENABLE_TRF_FOR_NS 161 el1_trf_regs_t trf; 162 #endif 163 164 #if ENABLE_FEAT_CSV2_2 165 el1_csv2_2_regs_t csv2_2; 166 #endif 167 168 #if ENABLE_FEAT_GCS 169 el1_gcs_regs_t gcs; 170 #endif 171 172 #if ENABLE_FEAT_THE 173 el1_the_regs_t the; 174 #endif 175 176 #if ENABLE_FEAT_SCTLR2 177 el1_sctlr2_regs_t sctlr2; 178 #endif 179 180 #if ENABLE_FEAT_LS64_ACCDATA 181 el1_ls64_regs_t ls64; 182 #endif 183 } el1_sysregs_t; 184 185 186 /* 187 * Macros to access members related to individual features of the el1_sysregs_t 188 * structures. 189 */ 190 191 #define read_el1_ctx_common(ctx, reg) (((ctx)->common).reg) 192 193 #define write_el1_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \ 194 = (uint64_t) (val)) 195 196 #define write_el1_ctx_common_sysreg128(ctx, reg, val) ((((ctx)->common).reg) \ 197 = (sysreg_t) (val)) 198 199 #define read_el1_ctx_arch_timer(ctx, reg) (((ctx)->arch_timer).reg) 200 #define write_el1_ctx_arch_timer(ctx, reg, val) ((((ctx)->arch_timer).reg) \ 201 = (uint64_t) (val)) 202 203 #if CTX_INCLUDE_AARCH32_REGS 204 #define read_el1_ctx_aarch32(ctx, reg) (((ctx)->el1_aarch32).reg) 205 #define write_el1_ctx_aarch32(ctx, reg, val) ((((ctx)->el1_aarch32).reg) \ 206 = (uint64_t) (val)) 207 #else 208 #define read_el1_ctx_aarch32(ctx, reg) ULL(0) 209 #define write_el1_ctx_aarch32(ctx, reg, val) 210 #endif /* CTX_INCLUDE_AARCH32_REGS */ 211 212 #if ENABLE_FEAT_MTE2 213 #define read_el1_ctx_mte2(ctx, reg) (((ctx)->mte2).reg) 214 #define write_el1_ctx_mte2(ctx, reg, val) ((((ctx)->mte2).reg) \ 215 = (uint64_t) (val)) 216 #else 217 #define read_el1_ctx_mte2(ctx, reg) ULL(0) 218 #define write_el1_ctx_mte2(ctx, reg, val) 219 #endif /* ENABLE_FEAT_MTE2 */ 220 221 #if ENABLE_FEAT_RAS 222 #define read_el1_ctx_ras(ctx, reg) (((ctx)->ras).reg) 223 #define write_el1_ctx_ras(ctx, reg, val) ((((ctx)->ras).reg) \ 224 = (uint64_t) (val)) 225 #else 226 #define read_el1_ctx_ras(ctx, reg) ULL(0) 227 #define write_el1_ctx_ras(ctx, reg, val) 228 #endif /* ENABLE_FEAT_RAS */ 229 230 #if ENABLE_FEAT_S1PIE 231 #define read_el1_ctx_s1pie(ctx, reg) (((ctx)->s1pie).reg) 232 #define write_el1_ctx_s1pie(ctx, reg, val) ((((ctx)->s1pie).reg) \ 233 = (uint64_t) (val)) 234 #else 235 #define read_el1_ctx_s1pie(ctx, reg) ULL(0) 236 #define write_el1_ctx_s1pie(ctx, reg, val) 237 #endif /* ENABLE_FEAT_S1PIE */ 238 239 #if ENABLE_FEAT_S1POE 240 #define read_el1_ctx_s1poe(ctx, reg) (((ctx)->s1poe).reg) 241 #define write_el1_ctx_s1poe(ctx, reg, val) ((((ctx)->s1poe).reg) \ 242 = (uint64_t) (val)) 243 #else 244 #define read_el1_ctx_s1poe(ctx, reg) ULL(0) 245 #define write_el1_ctx_s1poe(ctx, reg, val) 246 #endif /* ENABLE_FEAT_S1POE */ 247 248 #if ENABLE_FEAT_S2POE 249 #define read_el1_ctx_s2poe(ctx, reg) (((ctx)->s2poe).reg) 250 #define write_el1_ctx_s2poe(ctx, reg, val) ((((ctx)->s2poe).reg) \ 251 = (uint64_t) (val)) 252 #else 253 #define read_el1_ctx_s2poe(ctx, reg) ULL(0) 254 #define write_el1_ctx_s2poe(ctx, reg, val) 255 #endif /* ENABLE_FEAT_S2POE */ 256 257 #if ENABLE_FEAT_TCR2 258 #define read_el1_ctx_tcr2(ctx, reg) (((ctx)->tcr2).reg) 259 #define write_el1_ctx_tcr2(ctx, reg, val) ((((ctx)->tcr2).reg) \ 260 = (uint64_t) (val)) 261 #else 262 #define read_el1_ctx_tcr2(ctx, reg) ULL(0) 263 #define write_el1_ctx_tcr2(ctx, reg, val) 264 #endif /* ENABLE_FEAT_TCR2 */ 265 266 #if ENABLE_TRF_FOR_NS 267 #define read_el1_ctx_trf(ctx, reg) (((ctx)->trf).reg) 268 #define write_el1_ctx_trf(ctx, reg, val) ((((ctx)->trf).reg) \ 269 = (uint64_t) (val)) 270 #else 271 #define read_el1_ctx_trf(ctx, reg) ULL(0) 272 #define write_el1_ctx_trf(ctx, reg, val) 273 #endif /* ENABLE_TRF_FOR_NS */ 274 275 #if ENABLE_FEAT_CSV2_2 276 #define read_el1_ctx_csv2_2(ctx, reg) (((ctx)->csv2_2).reg) 277 #define write_el1_ctx_csv2_2(ctx, reg, val) ((((ctx)->csv2_2).reg) \ 278 = (uint64_t) (val)) 279 #else 280 #define read_el1_ctx_csv2_2(ctx, reg) ULL(0) 281 #define write_el1_ctx_csv2_2(ctx, reg, val) 282 #endif /* ENABLE_FEAT_CSV2_2 */ 283 284 #if ENABLE_FEAT_GCS 285 #define read_el1_ctx_gcs(ctx, reg) (((ctx)->gcs).reg) 286 #define write_el1_ctx_gcs(ctx, reg, val) ((((ctx)->gcs).reg) \ 287 = (uint64_t) (val)) 288 #else 289 #define read_el1_ctx_gcs(ctx, reg) ULL(0) 290 #define write_el1_ctx_gcs(ctx, reg, val) 291 #endif /* ENABLE_FEAT_GCS */ 292 293 #if ENABLE_FEAT_THE 294 #define read_el1_ctx_the(ctx, reg) (((ctx)->the).reg) 295 #define write_el1_ctx_the_sysreg128(ctx, reg, val) ((((ctx)->the).reg) \ 296 = (sysreg_t) (val)) 297 #else 298 #define read_el1_ctx_the(ctx, reg) ULL(0) 299 #define write_el1_ctx_the_sysreg128(ctx, reg, val) 300 #endif /* ENABLE_FEAT_THE */ 301 302 #if ENABLE_FEAT_SCTLR2 303 #define read_el1_ctx_sctlr2(ctx, reg) (((ctx)->sctlr2).reg) 304 #define write_el1_ctx_sctlr2(ctx, reg, val) ((((ctx)->sctlr2).reg) \ 305 = (uint64_t) (val)) 306 #else 307 #define read_el1_ctx_sctlr2(ctx, reg) ULL(0) 308 #define write_el1_ctx_sctlr2(ctx, reg, val) 309 #endif /* ENABLE_FEAT_SCTLR2 */ 310 311 #if ENABLE_FEAT_LS64_ACCDATA 312 #define read_el1_ctx_ls64(ctx, reg) (((ctx)->ls64).reg) 313 #define write_el1_ctx_ls64(ctx, reg, val) ((((ctx)->ls64).reg) \ 314 = (uint64_t) (val)) 315 #else 316 #define read_el1_ctx_ls64(ctx, reg) ULL(0) 317 #define write_el1_ctx_ls64(ctx, reg, val) 318 #endif /* ENABLE_FEAT_LS64_ACCDATA */ 319 /******************************************************************************/ 320 #endif /* __ASSEMBLER__ */ 321 322 #endif /* CONTEXT_EL1_H */ 323