1/* 2 * Copyright (c) 2025-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <veymont.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Veymont must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Veymont supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_prologue veymont 25 26cpu_reset_func_start veymont 27 /* ---------------------------------------------------- 28 * Disable speculative loads 29 * ---------------------------------------------------- 30 */ 31 msr SSBS, xzr 32 enable_mpmm 33cpu_reset_func_end veymont 34 35func veymont_core_pwr_dwn 36 /* 37 * When software running at lower ELs requests power down without first 38 * disabling SME, the CME connected to it will reject its power down 39 * request. Skip setting the PWRDN_EN bit, downgrading the powerdown 40 * request to a simple WFI wait, to get a minimal amount of power saving 41 * rather than an instant pabandon. 42 */ 43#if ENABLE_SME_FOR_NS 44#if ENABLE_SME_FOR_NS == 2 45 is_feat_sme_present_asm x1 46 beq 1f 47#endif 48 mrs x0, SVCR 49 cbnz x0, veymont_skip_pwr_dwn 501: 51#endif 52 53 /* --------------------------------------------------- 54 * Flip CPU power down bit in power control register. 55 * It will be set on powerdown and cleared on wakeup 56 * --------------------------------------------------- 57 */ 58 sysreg_bit_toggle VEYMONT_IMP_CPUPWRCTLR_EL1, \ 59 VEYMONT_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 60 isb 61veymont_skip_pwr_dwn: 62 signal_pabandon_handled 63 ret 64endfunc veymont_core_pwr_dwn 65 66.section .rodata.veymont_regs, "aS" 67veymont_regs: /* The ASCII list of register names to be reported */ 68 .asciz "cpuectlr_el1", "" 69 70func veymont_cpu_reg_dump 71 adr x6, veymont_regs 72 mrs x8, VEYMONT_IMP_CPUECTLR_EL1 73 ret 74endfunc veymont_cpu_reg_dump 75 76declare_cpu_ops veymont, VEYMONT_MIDR, \ 77 veymont_reset_func, \ 78 veymont_core_pwr_dwn 79