1/* 2 * Copyright (c) 2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <rosillo.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Rosillo must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Rosillo supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_prologue rosillo 25 26cpu_reset_func_start rosillo 27 /* ---------------------------------------------------- 28 * Disable speculative loads 29 * ---------------------------------------------------- 30 */ 31 msr SSBS, xzr 32 enable_mpmm 33cpu_reset_func_end rosillo 34 35func rosillo_core_pwr_dwn 36 /* 37 * When software running at lower ELs requests power down without first 38 * disabling SME, the CME connected to it will reject its power down 39 * request. Skip setting the PWRDN_EN bit, downgrading the powerdown 40 * request to a simple WFI wait, to get a minimal amount of power saving 41 * rather than an instant pabandon. 42 */ 43 mrs x0, SVCR 44 cbnz x0, rosillo_skip_pwr_dwn 45 46 /* --------------------------------------------------- 47 * Flip CPU power down bit in power control register. 48 * It will be set on powerdown and cleared on wakeup 49 * --------------------------------------------------- 50 */ 51 sysreg_bit_toggle ROSILLO_IMP_CPUPWRCTLR_EL1, \ 52 ROSILLO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 53 isb 54rosillo_skip_pwr_dwn: 55 signal_pabandon_handled 56 ret 57endfunc rosillo_core_pwr_dwn 58 59.section .rodata.rosillo_regs, "aS" 60rosillo_regs: /* The ASCII list of register names to be reported */ 61 .asciz "cpuectlr_el1", "" 62 63func rosillo_cpu_reg_dump 64 adr x6, rosillo_regs 65 mrs x8, ROSILLO_IMP_CPUECTLR_EL1 66 ret 67endfunc rosillo_cpu_reg_dump 68 69declare_cpu_ops rosillo, ROSILLO_MIDR, \ 70 rosillo_reset_func, \ 71 rosillo_core_pwr_dwn 72