1/* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <cpu_macros.S> 9#include <qemu_max.h> 10 11cpu_reset_prologue qemu_max 12 13func qemu_max_core_pwr_dwn 14 /* --------------------------------------------- 15 * Flush L1 cache to L2. 16 * --------------------------------------------- 17 */ 18 mov x18, lr 19 mov x0, #DCCISW 20 bl dcsw_op_level1 21 mov lr, x18 22 ret 23endfunc qemu_max_core_pwr_dwn 24 25func qemu_max_cluster_pwr_dwn 26 /* --------------------------------------------- 27 * Flush all caches to PoC. 28 * --------------------------------------------- 29 */ 30 mov x0, #DCCISW 31 b dcsw_op_all 32endfunc qemu_max_cluster_pwr_dwn 33 34cpu_reset_func_start qemu_max 35cpu_reset_func_end qemu_max 36 37 /* --------------------------------------------- 38 * This function provides cpu specific 39 * register information for crash reporting. 40 * It needs to return with x6 pointing to 41 * a list of register names in ascii and 42 * x8 - x15 having values of registers to be 43 * reported. 44 * --------------------------------------------- 45 */ 46.section .rodata.qemu_max_regs, "aS" 47qemu_max_regs: /* The ascii list of register names to be reported */ 48 .asciz "" /* no registers to report */ 49 50func qemu_max_cpu_reg_dump 51 adr x6, qemu_max_regs 52 ret 53endfunc qemu_max_cpu_reg_dump 54 55 56/* cpu_ops for QEMU MAX */ 57declare_cpu_ops qemu_max, QEMU_MAX_MIDR, qemu_max_reset_func, \ 58 qemu_max_core_pwr_dwn, \ 59 qemu_max_cluster_pwr_dwn 60