1/* 2 * Copyright (c) 2021-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v2.h> 11#include "wa_cve_2022_23960_bhb_vector.S" 12 13#include <cpu_macros.S> 14#include <wa_cve_2025_0647_cpprctx.h> 15 16#include <plat_macros.S> 17 18/* Hardware handled coherency */ 19#if HW_ASSISTED_COHERENCY == 0 20#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" 21#endif 22 23/* 64-bit only core */ 24#if CTX_INCLUDE_AARCH32_REGS == 1 25#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 26#endif 27 28.global check_erratum_neoverse_v2_3701771 29 30cpu_reset_prologue neoverse_v2 31 32workaround_reset_start neoverse_v2, ERRATUM(2618597), ERRATA_V2_2618597 33 /* Disable retention control for WFI and WFE. */ 34 mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 35 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \ 36 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH 37 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \ 38 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH 39 msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0 40workaround_reset_end neoverse_v2, ERRATUM(2618597) 41 42/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */ 43add_erratum_entry neoverse_v2, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960 44 45check_erratum_ls neoverse_v2, ERRATUM(ARCH_WORKAROUND_3), CPU_REV(0, 0) 46 47check_erratum_ls neoverse_v2, ERRATUM(2618597), CPU_REV(0, 1) 48 49workaround_reset_start neoverse_v2, ERRATUM(2662553), ERRATA_V2_2662553 50 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL, \ 51 NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH 52workaround_reset_end neoverse_v2, ERRATUM(2662553) 53 54check_erratum_ls neoverse_v2, ERRATUM(2662553), CPU_REV(0, 1) 55 56workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105 57 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 58workaround_reset_end neoverse_v2, ERRATUM(2719105) 59 60check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) 61 62workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011 63 sysreg_lazy_start NEOVERSE_V2_CPUACTLR5_EL1 64 sysreg_lazy_set NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 65 sysreg_lazy_clear NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 66 sysreg_lazy_commit NEOVERSE_V2_CPUACTLR5_EL1 67workaround_reset_end neoverse_v2, ERRATUM(2743011) 68 69check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1) 70 71workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510 72 sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 73workaround_reset_end neoverse_v2, ERRATUM(2779510) 74 75check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1) 76 77workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 78 /* dsb before isb of power down sequence */ 79 dsb sy 80workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 81 82check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1) 83 84workaround_reset_start neoverse_v2, ERRATUM(3442699), ERRATA_V2_3442699 85 sysreg_bit_set NEOVERSE_V2_CPUACTLR_EL1, NEOVERSE_V2_CPUACTLR_EL1_BIT_36 86workaround_reset_end neoverse_v2, ERRATUM(3442699) 87 88check_erratum_ls neoverse_v2, ERRATUM(3442699), CPU_REV(0, 2) 89 90add_erratum_entry neoverse_v2, ERRATUM(3701771), ERRATA_V2_3701771 91 92check_erratum_ls neoverse_v2, ERRATUM(3701771), CPU_REV(0, 2) 93 94workaround_reset_start neoverse_v2, ERRATUM(3841324), ERRATA_V2_3841324 95 sysreg_bit_set NEOVERSE_V2_CPUACTLR_EL1, BIT(1) 96workaround_reset_end neoverse_v2, ERRATUM(3841324) 97 98check_erratum_ls neoverse_v2, ERRATUM(3841324), CPU_REV(0, 1) 99 100workaround_reset_start neoverse_v2, ERRATUM(3888126), ERRATA_V2_3888126 101 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, BIT(22) 102workaround_reset_end neoverse_v2, ERRATUM(3888126) 103 104check_erratum_ls neoverse_v2, ERRATUM(3888126), CPU_REV(0, 2) 105 106workaround_reset_start neoverse_v2, ERRATUM(4302968), ERRATA_V2_4302968 107 sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, BIT(50) 108workaround_reset_end neoverse_v2, ERRATUM(4302968) 109 110check_erratum_ls neoverse_v2, ERRATUM(4302968), CPU_REV(0, 2) 111 112workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 113#if IMAGE_BL31 114 /* 115 * The Neoverse-V2 generic vectors are overridden to apply errata 116 * mitigation on exception entry from lower ELs. 117 */ 118 override_vector_table wa_cve_vbar_neoverse_v2 119#endif /* IMAGE_BL31 */ 120workaround_reset_end neoverse_v2, CVE(2022, 23960) 121 122check_erratum_ls neoverse_v2, CVE(2022, 23960), CPU_REV(0, 0) 123 124/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 125workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 126 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46) 127workaround_reset_end neoverse_v2, CVE(2024, 5660) 128 129check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2) 130 131#if WORKAROUND_CVE_2022_23960 132 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 133#endif /* WORKAROUND_CVE_2022_23960 */ 134 135 /* ---------------------------------------------------------------- 136 * CVE-2024-7881 is mitigated for Neoverse-V2 using erratum 3696445 137 * workaround by disabling the affected prefetcher setting 138 * CPUACTLR6_EL1[41]. 139 * ---------------------------------------------------------------- 140 */ 141workaround_reset_start neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 142 sysreg_bit_set NEOVERSE_V2_CPUACTLR6_EL1, BIT(41) 143workaround_reset_end neoverse_v2, CVE(2024, 7881) 144 145check_erratum_ls neoverse_v2, CVE(2024, 7881), CPU_REV(0, 2) 146 147 /* 148 * Instruction patch sequence to trap 'cpp rctx' instructions to EL3. 149 * Enables mitigation for CVE-2025-0647. 150 */ 151workaround_reset_start neoverse_v2, CVE(2025, 647), WORKAROUND_CVE_2025_0647 152#if IMAGE_BL31 153 mov x0, #WA_PATCH_SLOT(3) 154 bl wa_cve_2025_0647_instruction_patch 155#endif /* IMAGE_BL31 */ 156workaround_reset_end neoverse_v2, CVE(2025, 647) 157 158check_erratum_chosen neoverse_v2, CVE(2025, 647), WORKAROUND_CVE_2025_0647 159 160#if WORKAROUND_CVE_2025_0647 161func neoverse_v2_impl_defined_el3_handler 162 mov x0, #WA_LS_RCG_EN 163 164 /* See if this call came from trap handler. */ 165 cmp x1, #EC_IMP_DEF_EL3 166 bne wa_cve_2025_0647_do_cpp_wa 167 orr x0, x0, #WA_IS_TRAP_HANDLER 168 b wa_cve_2025_0647_do_cpp_wa 169endfunc neoverse_v2_impl_defined_el3_handler 170#endif 171 172 /* ---------------------------------------------------- 173 * HW will do the cache maintenance while powering down 174 * ---------------------------------------------------- 175 */ 176func neoverse_v2_core_pwr_dwn 177 /* --------------------------------------------------- 178 * Enable CPU power down bit in power control register 179 * --------------------------------------------------- 180 */ 181 sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 182 apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 183 184 isb 185 ret 186endfunc neoverse_v2_core_pwr_dwn 187 188cpu_reset_func_start neoverse_v2 189 /* Disable speculative loads */ 190 msr SSBS, xzr 191 192#if NEOVERSE_Vx_EXTERNAL_LLC 193 /* Some systems may have External LLC, core needs to be made aware */ 194 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT 195#endif 196cpu_reset_func_end neoverse_v2 197 198 /* --------------------------------------------- 199 * This function provides Neoverse V2- 200 * specific register information for crash 201 * reporting. It needs to return with x6 202 * pointing to a list of register names in ascii 203 * and x8 - x15 having values of registers to be 204 * reported. 205 * --------------------------------------------- 206 */ 207.section .rodata.neoverse_v2_regs, "aS" 208neoverse_v2_regs: /* The ascii list of register names to be reported */ 209 .asciz "cpuectlr_el1", "" 210 211func neoverse_v2_cpu_reg_dump 212 adr x6, neoverse_v2_regs 213 mrs x8, NEOVERSE_V2_CPUECTLR_EL1 214 ret 215endfunc neoverse_v2_cpu_reg_dump 216 217#if WORKAROUND_CVE_2025_0647 && IMAGE_BL31 218declare_cpu_ops_eh neoverse_v2, NEOVERSE_V2_MIDR, \ 219 neoverse_v2_reset_func, \ 220 neoverse_v2_impl_defined_el3_handler, \ 221 neoverse_v2_core_pwr_dwn 222#else 223declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \ 224 neoverse_v2_reset_func, \ 225 neoverse_v2_core_pwr_dwn 226#endif 227 228