1/* 2 * Copyright (c) 2021-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78c.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20#if WORKAROUND_CVE_2022_23960 21 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c 22#endif /* WORKAROUND_CVE_2022_23960 */ 23 24cpu_reset_prologue cortex_a78c 25 26workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430 27 /* Disable allocation of splintered pages in the L2 TLB */ 28 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN 29workaround_reset_end cortex_a78c, ERRATUM(1827430) 30 31check_erratum_ls cortex_a78c, ERRATUM(1827430), CPU_REV(0, 0) 32 33workaround_reset_start cortex_a78c, ERRATUM(1827440), ERRATA_A78C_1827440 34 /* Force Atomic Store to WB memory be done in L1 data cache */ 35 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(2) 36workaround_reset_end cortex_a78c, ERRATUM(1827440) 37 38check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0) 39 40workaround_reset_start cortex_a78c, ERRATUM(1941499), ERRATA_A78C_1941499 41 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, BIT(8) 42workaround_reset_end cortex_a78c, ERRATUM(1941499) 43 44check_erratum_ls cortex_a78c, ERRATUM(1941499), CPU_REV(0, 0) 45 46workaround_reset_start cortex_a78c, ERRATUM(1951501), ERRATA_A78C_1951501 47 ldr x0,=0x0 48 msr s3_6_c15_c8_0, x0 49 ldr x0, =0x10e3900002 50 msr s3_6_c15_c8_2, x0 51 ldr x0, =0x10fff00083 52 msr s3_6_c15_c8_3, x0 53 ldr x0, =0x2001003ff 54 msr s3_6_c15_c8_1, x0 55 56 ldr x0,=0x1 57 msr s3_6_c15_c8_0, x0 58 ldr x0, =0x10e3800082 59 msr s3_6_c15_c8_2, x0 60 ldr x0, =0x10fff00083 61 msr s3_6_c15_c8_3, x0 62 ldr x0, =0x2001003ff 63 msr s3_6_c15_c8_1, x0 64 65 ldr x0, =0x2 66 msr s3_6_c15_c8_0, x0 67 ldr x0, =0x10e3800200 68 msr s3_6_c15_c8_2, x0 69 ldr x0, =0x10fff003e0 70 msr s3_6_c15_c8_3, x0 71 ldr x0, =0x2001003ff 72 msr s3_6_c15_c8_1, x0 73workaround_reset_end cortex_a78c, ERRATUM(1951501) 74 75check_erratum_ls cortex_a78c, ERRATUM(1951501), CPU_REV(0, 0) 76 77workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638 78 ldr x0, =0x5 79 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 80 ldr x0, =0x10F600E000 81 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 82 ldr x0, =0x10FF80E000 83 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 84 ldr x0, =0x80000000003FF 85 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 86workaround_reset_end cortex_a78c, ERRATUM(2242638) 87 88check_erratum_range cortex_a78c, ERRATUM(2242638), CPU_REV(0, 1), CPU_REV(0, 2) 89 90workaround_reset_start cortex_a78c, ERRATUM(2376746), ERRATA_A78C_2376746 91 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(0) 92workaround_reset_end cortex_a78c, ERRATUM(2376746) 93 94check_erratum_chosen cortex_a78c, ERRATUM(2376746), ERRATA_A78C_2376746 95 96workaround_reset_start cortex_a78c, ERRATUM(2376749), ERRATA_A78C_2376749 97 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_0 98workaround_reset_end cortex_a78c, ERRATUM(2376749) 99 100check_erratum_range cortex_a78c, ERRATUM(2376749), CPU_REV(0, 1), CPU_REV(0, 2) 101 102workaround_reset_start cortex_a78c, ERRATUM(2395407), ERRATA_A78C_2395407 103 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(40) 104workaround_reset_end cortex_a78c, ERRATUM(2395407) 105 106check_erratum_chosen cortex_a78c, ERRATUM(2395407), ERRATA_A78C_2395407 107 108workaround_reset_start cortex_a78c, ERRATUM(2395411), ERRATA_A78C_2395411 109 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_40 110workaround_reset_end cortex_a78c, ERRATUM(2395411) 111 112check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2) 113 114workaround_reset_start cortex_a78c, ERRATUM(2478780), ERRATA_A78C_2478780 115 ldr x0, =0x3 116 msr s3_6_c15_c8_0, x0 117 ldr x0, =0xee010f10 118 msr s3_6_c15_c8_2, x0 119 ldr x0, =0xff1f0ffe 120 msr s3_6_c15_c8_3, x0 121 ldr x0, =0x100000004003ff 122 msr s3_6_c15_c8_1, x0 123 isb 124workaround_reset_end cortex_a78c, ERRATUM(2478780) 125 126check_erratum_chosen cortex_a78c, ERRATUM(2478780), ERRATA_A78C_2478780 127 128workaround_reset_start cortex_a78c, ERRATUM(2683027), ERRATA_A78C_2683027 129 ldr x0, =0x3 130 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 131 ldr x0, =0xEE010F10 132 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 133 ldr x0, =0xFF1F0FFE 134 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 135 ldr x0, =0x100000004003FF 136 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 137workaround_reset_end cortex_a78c, ERRATUM(2683027) 138 139check_erratum_range cortex_a78c, ERRATUM(2683027), CPU_REV(0, 1), CPU_REV(0, 2) 140 141workaround_reset_start cortex_a78c, ERRATUM(2743232), ERRATA_A78C_2743232 142 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 143 sysreg_lazy_start CORTEX_A78C_ACTLR5_EL1 144 sysreg_lazy_set BIT(55) 145 sysreg_lazy_clear BIT(56) 146 sysreg_lazy_commit CORTEX_A78C_ACTLR5_EL1 147workaround_reset_end cortex_a78c, ERRATUM(2743232) 148 149check_erratum_range cortex_a78c, ERRATUM(2743232), CPU_REV(0, 1), CPU_REV(0, 2) 150 151workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 152 /* dsb before isb of power down sequence */ 153 dsb sy 154workaround_runtime_end cortex_a78c, ERRATUM(2772121) 155 156check_erratum_ls cortex_a78c, ERRATUM(2772121), CPU_REV(0, 2) 157 158workaround_reset_start cortex_a78c, ERRATUM(2779483), ERRATA_A78C_2779483 159 sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47) 160workaround_reset_end cortex_a78c, ERRATUM(2779483) 161 162check_erratum_chosen cortex_a78c, ERRATUM(2779483), ERRATA_A78C_2779483 163 164workaround_reset_start cortex_a78c, ERRATUM(2779484), ERRATA_A78C_2779484 165 sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47) 166workaround_reset_end cortex_a78c, ERRATUM(2779484) 167 168check_erratum_range cortex_a78c, ERRATUM(2779484), CPU_REV(0, 1), CPU_REV(0, 2) 169 170workaround_reset_start cortex_a78c, ERRATUM(3888019), ERRATA_A78C_3888019 171 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(22) 172workaround_reset_end cortex_a78c, ERRATUM(3888019) 173 174check_erratum_chosen cortex_a78c, ERRATUM(3888019), ERRATA_A78C_3888019 175 176workaround_reset_start cortex_a78c, ERRATUM(4302974), ERRATA_A78C_4302974 177 sysreg_bit_set CORTEX_A78C_ACTLR5_EL1, BIT(50) 178workaround_reset_end cortex_a78c, ERRATUM(4302974) 179 180check_erratum_chosen cortex_a78c, ERRATUM(4302974), ERRATA_A78C_4302974 181 182check_erratum_chosen cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 183 184workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 185#if IMAGE_BL31 186 /* 187 * The Cortex-A78c generic vectors are overridden to apply errata 188 * mitigation on exception entry from lower ELs. 189 */ 190 override_vector_table wa_cve_vbar_cortex_a78c 191#endif /* IMAGE_BL31 */ 192workaround_reset_end cortex_a78c, CVE(2022, 23960) 193 194/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 195workaround_reset_start cortex_a78c, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 196 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, BIT(46) 197workaround_reset_end cortex_a78c, CVE(2024, 5660) 198 199check_erratum_chosen cortex_a78c, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 200 201cpu_reset_func_start cortex_a78c 202cpu_reset_func_end cortex_a78c 203 204 /* ---------------------------------------------------- 205 * HW will do the cache maintenance while powering down 206 * ---------------------------------------------------- 207 */ 208func cortex_a78c_core_pwr_dwn 209 /* --------------------------------------------------- 210 * Enable CPU power down bit in power control register 211 * --------------------------------------------------- 212 */ 213 sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 214 215 apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 216 217 isb 218 ret 219endfunc cortex_a78c_core_pwr_dwn 220 221 /* --------------------------------------------- 222 * This function provides cortex_a78c specific 223 * register information for crash reporting. 224 * It needs to return with x6 pointing to 225 * a list of register names in ascii and 226 * x8 - x15 having values of registers to be 227 * reported. 228 * --------------------------------------------- 229 */ 230.section .rodata.cortex_a78c_regs, "aS" 231cortex_a78c_regs: /* The ascii list of register names to be reported */ 232 .asciz "cpuectlr_el1", "" 233 234func cortex_a78c_cpu_reg_dump 235 adr x6, cortex_a78c_regs 236 mrs x8, CORTEX_A78C_CPUECTLR_EL1 237 ret 238endfunc cortex_a78c_cpu_reg_dump 239 240declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ 241 cortex_a78c_reset_func, \ 242 cortex_a78c_core_pwr_dwn 243