1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78c.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20#if WORKAROUND_CVE_2022_23960 21 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c 22#endif /* WORKAROUND_CVE_2022_23960 */ 23 24cpu_reset_prologue cortex_a78c 25 26workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430 27 /* Disable allocation of splintered pages in the L2 TLB */ 28 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN 29workaround_reset_end cortex_a78c, ERRATUM(1827430) 30 31check_erratum_ls cortex_a78c, ERRATUM(1827430), CPU_REV(0, 0) 32 33workaround_reset_start cortex_a78c, ERRATUM(1827440), ERRATA_A78C_1827440 34 /* Force Atomic Store to WB memory be done in L1 data cache */ 35 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(2) 36workaround_reset_end cortex_a78c, ERRATUM(1827440) 37 38check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0) 39 40workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638 41 ldr x0, =0x5 42 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 43 ldr x0, =0x10F600E000 44 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 45 ldr x0, =0x10FF80E000 46 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 47 ldr x0, =0x80000000003FF 48 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 49workaround_reset_end cortex_a78c, ERRATUM(2242638) 50 51check_erratum_range cortex_a78c, ERRATUM(2242638), CPU_REV(0, 1), CPU_REV(0, 2) 52 53workaround_reset_start cortex_a78c, ERRATUM(2376749), ERRATA_A78C_2376749 54 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_0 55workaround_reset_end cortex_a78c, ERRATUM(2376749) 56 57check_erratum_range cortex_a78c, ERRATUM(2376749), CPU_REV(0, 1), CPU_REV(0, 2) 58 59workaround_reset_start cortex_a78c, ERRATUM(2395411), ERRATA_A78C_2395411 60 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_40 61workaround_reset_end cortex_a78c, ERRATUM(2395411) 62 63check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2) 64 65workaround_reset_start cortex_a78c, ERRATUM(2683027), ERRATA_A78C_2683027 66 ldr x0, =0x3 67 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 68 ldr x0, =0xEE010F10 69 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 70 ldr x0, =0xFF1F0FFE 71 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 72 ldr x0, =0x100000004003FF 73 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 74workaround_reset_end cortex_a78c, ERRATUM(2683027) 75 76check_erratum_range cortex_a78c, ERRATUM(2683027), CPU_REV(0, 1), CPU_REV(0, 2) 77 78workaround_reset_start cortex_a78c, ERRATUM(2743232), ERRATA_A78C_2743232 79 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 80 sysreg_bit_set CORTEX_A78C_ACTLR5_EL1, BIT(55) 81 sysreg_bit_clear CORTEX_A78C_ACTLR5_EL1, BIT(56) 82workaround_reset_end cortex_a78c, ERRATUM(2743232) 83 84check_erratum_range cortex_a78c, ERRATUM(2743232), CPU_REV(0, 1), CPU_REV(0, 2) 85 86workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 87 /* dsb before isb of power down sequence */ 88 dsb sy 89workaround_runtime_end cortex_a78c, ERRATUM(2772121) 90 91check_erratum_ls cortex_a78c, ERRATUM(2772121), CPU_REV(0, 2) 92 93workaround_reset_start cortex_a78c, ERRATUM(2779484), ERRATA_A78C_2779484 94 sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47) 95workaround_reset_end cortex_a78c, ERRATUM(2779484) 96 97check_erratum_range cortex_a78c, ERRATUM(2779484), CPU_REV(0, 1), CPU_REV(0, 2) 98 99check_erratum_chosen cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 100 101workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 102#if IMAGE_BL31 103 /* 104 * The Cortex-A78c generic vectors are overridden to apply errata 105 * mitigation on exception entry from lower ELs. 106 */ 107 override_vector_table wa_cve_vbar_cortex_a78c 108#endif /* IMAGE_BL31 */ 109workaround_reset_end cortex_a78c, CVE(2022, 23960) 110 111/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 112workaround_reset_start cortex_a78c, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 113 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, BIT(46) 114workaround_reset_end cortex_a78c, CVE(2024, 5660) 115 116check_erratum_ls cortex_a78c, CVE(2024, 5660), CPU_REV(0, 2) 117 118cpu_reset_func_start cortex_a78c 119cpu_reset_func_end cortex_a78c 120 121 /* ---------------------------------------------------- 122 * HW will do the cache maintenance while powering down 123 * ---------------------------------------------------- 124 */ 125func cortex_a78c_core_pwr_dwn 126 /* --------------------------------------------------- 127 * Enable CPU power down bit in power control register 128 * --------------------------------------------------- 129 */ 130 sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 131 132 apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 133 134 isb 135 ret 136endfunc cortex_a78c_core_pwr_dwn 137 138 /* --------------------------------------------- 139 * This function provides cortex_a78c specific 140 * register information for crash reporting. 141 * It needs to return with x6 pointing to 142 * a list of register names in ascii and 143 * x8 - x15 having values of registers to be 144 * reported. 145 * --------------------------------------------- 146 */ 147.section .rodata.cortex_a78c_regs, "aS" 148cortex_a78c_regs: /* The ascii list of register names to be reported */ 149 .asciz "cpuectlr_el1", "" 150 151func cortex_a78c_cpu_reg_dump 152 adr x6, cortex_a78c_regs 153 mrs x8, CORTEX_A78C_CPUECTLR_EL1 154 ret 155endfunc cortex_a78c_cpu_reg_dump 156 157declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ 158 cortex_a78c_reset_func, \ 159 cortex_a78c_core_pwr_dwn 160