1/* 2 * Copyright (c) 2019-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20.globl cortex_a78_reset_func 21.globl cortex_a78_core_pwr_dwn 22 23#if WORKAROUND_CVE_2022_23960 24 wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78 25#endif /* WORKAROUND_CVE_2022_23960 */ 26 27cpu_reset_prologue cortex_a78 28 29workaround_reset_start cortex_a78, ERRATUM(1467580), ERRATA_A78_1467580 30 ldr x0,=0x7 31 msr s3_6_c15_c8_0,x0 32 ldr x0,=0xf3d08000 33 msr s3_6_c15_c8_2,x0 34 ldr x0,=0xfff0f0ff 35 msr s3_6_c15_c8_3,x0 36 ldr x0,=0x80000002003ff 37 msr s3_6_c15_c8_1,x0 38 isb 39workaround_reset_end cortex_a78, ERRATUM(1467580) 40 41check_erratum_ls cortex_a78, ERRATUM(1467580), CPU_REV(0, 0) 42 43workaround_reset_start cortex_a78, ERRATUM(1479939), ERRATA_A78_1479939 44 sysreg_bit_set CORTEX_A78_CPUACTLR_EL1, BIT(13) 45workaround_reset_end cortex_a78, ERRATUM(1479939) 46 47check_erratum_ls cortex_a78, ERRATUM(1479939), CPU_REV(0, 0) 48 49workaround_reset_start cortex_a78, ERRATUM(1492189), ERRATA_A78_1492189 50 sysreg_bit_set CORTEX_A78_ACTLR5_EL1, BIT(8) 51workaround_reset_end cortex_a78, ERRATUM(1492189) 52 53check_erratum_ls cortex_a78, ERRATUM(1492189), CPU_REV(0, 0) 54 55workaround_reset_start cortex_a78, ERRATUM(1503072), ERRATA_A78_1503072 56 ldr x0,=0x0 57 msr s3_6_c15_c8_0,x0 58 ldr x0,=0xee070f14 59 msr s3_6_c15_c8_2,x0 60 ldr x0,=0xffff0fff 61 msr s3_6_c15_c8_3,x0 62 ldr x0,=0x4005027ff 63 msr s3_6_c15_c8_1,x0 64 ldr x0,=0x1 65 msr s3_6_c15_c8_0,x0 66 ldr x0,=0x00e8400000 67 msr s3_6_c15_c8_2,x0 68 ldr x0,=0x00fff00000 69 msr s3_6_c15_c8_3,x0 70 ldr x0,=0x4001027ff 71 msr s3_6_c15_c8_1,x0 72 ldr x0,=0x2 73 msr s3_6_c15_c8_0,x0 74 ldr x0,=0x00e8c00040 75 msr s3_6_c15_c8_2,x0 76 ldr x0,=0x00fff00040 77 msr s3_6_c15_c8_3,x0 78 ldr x0,=0x4001027ff 79 msr s3_6_c15_c8_1,x0 80 ldr x0,=0x3 81 msr s3_6_c15_c8_0,x0 82 ldr x0,=0x00e8400000 83 msr s3_6_c15_c8_2,x0 84 ldr x0,=0x00fff00000 85 msr s3_6_c15_c8_3,x0 86 ldr x0,=0x4004027ff 87 msr s3_6_c15_c8_1,x0 88 ldr x0,=0x4 89 msr s3_6_c15_c8_0,x0 90 ldr x0,=0x00e8c00040 91 msr s3_6_c15_c8_2,x0 92 ldr x0,=0x00fff00040 93 msr s3_6_c15_c8_3,x0 94 ldr x0,=0x4004027ff 95 msr s3_6_c15_c8_1,x0 96 isb 97workaround_reset_end cortex_a78, ERRATUM(1503072) 98 99check_erratum_ls cortex_a78, ERRATUM(1503072), CPU_REV(0, 0) 100 101workaround_reset_start cortex_a78, ERRATUM(1515634), ERRATA_A78_1515634 102 sysreg_bit_set CORTEX_A78_CPUACTLR_EL1, BIT(11) 103workaround_reset_end cortex_a78, ERRATUM(1515634) 104 105check_erratum_ls cortex_a78, ERRATUM(1515634), CPU_REV(0, 0) 106 107workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305 108 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_1 109workaround_reset_end cortex_a78, ERRATUM(1688305) 110 111check_erratum_ls cortex_a78, ERRATUM(1688305), CPU_REV(1, 0) 112 113workaround_reset_start cortex_a78, ERRATUM(1821534), ERRATA_A78_1821534 114 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_2 115workaround_reset_end cortex_a78, ERRATUM(1821534) 116 117check_erratum_ls cortex_a78, ERRATUM(1821534), CPU_REV(1, 0) 118 119workaround_reset_start cortex_a78, ERRATUM(1827429), ERRATA_A78_1827429 120 sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, BIT(53) 121workaround_reset_end cortex_a78, ERRATUM(1827429) 122 123check_erratum_ls cortex_a78, ERRATUM(1827429), CPU_REV(1, 0) 124 125workaround_reset_start cortex_a78, ERRATUM(1941498), ERRATA_A78_1941498 126 sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, CORTEX_A78_CPUECTLR_EL1_BIT_8 127workaround_reset_end cortex_a78, ERRATUM(1941498) 128 129check_erratum_ls cortex_a78, ERRATUM(1941498), CPU_REV(1, 1) 130 131workaround_reset_start cortex_a78, ERRATUM(1951500), ERRATA_A78_1951500 132 msr S3_6_c15_c8_0, xzr 133 ldr x0, =0x10E3900002 134 msr S3_6_c15_c8_2, x0 135 ldr x0, =0x10FFF00083 136 msr S3_6_c15_c8_3, x0 137 ldr x0, =0x2001003FF 138 msr S3_6_c15_c8_1, x0 139 140 mov x0, #1 141 msr S3_6_c15_c8_0, x0 142 ldr x0, =0x10E3800082 143 msr S3_6_c15_c8_2, x0 144 ldr x0, =0x10FFF00083 145 msr S3_6_c15_c8_3, x0 146 ldr x0, =0x2001003FF 147 msr S3_6_c15_c8_1, x0 148 149 mov x0, #2 150 msr S3_6_c15_c8_0, x0 151 ldr x0, =0x10E3800200 152 msr S3_6_c15_c8_2, x0 153 ldr x0, =0x10FFF003E0 154 msr S3_6_c15_c8_3, x0 155 ldr x0, =0x2001003FF 156 msr S3_6_c15_c8_1, x0 157workaround_reset_end cortex_a78, ERRATUM(1951500) 158 159check_erratum_range cortex_a78, ERRATUM(1951500), CPU_REV(1, 0), CPU_REV(1, 1) 160 161workaround_reset_start cortex_a78, ERRATUM(1952683), ERRATA_A78_1952683 162 ldr x0,=0x5 163 msr S3_6_c15_c8_0,x0 164 ldr x0,=0xEEE10A10 165 msr S3_6_c15_c8_2,x0 166 ldr x0,=0xFFEF0FFF 167 msr S3_6_c15_c8_3,x0 168 ldr x0,=0x0010F000 169 msr S3_6_c15_c8_4,x0 170 ldr x0,=0x0010F000 171 msr S3_6_c15_c8_5,x0 172 ldr x0,=0x40000080023ff 173 msr S3_6_c15_c8_1,x0 174 ldr x0,=0x6 175 msr S3_6_c15_c8_0,x0 176 ldr x0,=0xEE640F34 177 msr S3_6_c15_c8_2,x0 178 ldr x0,=0xFFEF0FFF 179 msr S3_6_c15_c8_3,x0 180 ldr x0,=0x40000080023ff 181 msr S3_6_c15_c8_1,x0 182workaround_reset_end cortex_a78, ERRATUM(1952683) 183 184check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0) 185 186workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635 187 ldr x0, =0x5 188 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ 189 ldr x0, =0x10F600E000 190 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ 191 ldr x0, =0x10FF80E000 192 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ 193 ldr x0, =0x80000000003FF 194 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ 195workaround_reset_end cortex_a78, ERRATUM(2242635) 196 197check_erratum_range cortex_a78, ERRATUM(2242635), CPU_REV(1, 0), CPU_REV(1, 2) 198 199workaround_reset_start cortex_a78, ERRATUM(2376745), ERRATA_A78_2376745 200 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(0) 201workaround_reset_end cortex_a78, ERRATUM(2376745) 202 203check_erratum_ls cortex_a78, ERRATUM(2376745), CPU_REV(1, 2) 204 205workaround_reset_start cortex_a78, ERRATUM(2395406), ERRATA_A78_2395406 206 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(40) 207workaround_reset_end cortex_a78, ERRATUM(2395406) 208 209check_erratum_ls cortex_a78, ERRATUM(2395406), CPU_REV(1, 2) 210 211workaround_reset_start cortex_a78, ERRATUM(2742426), ERRATA_A78_2742426 212 /* Apply the workaround */ 213 mrs x1, CORTEX_A78_ACTLR5_EL1 214 bic x1, x1, #BIT(56) 215 orr x1, x1, #BIT(55) 216 msr CORTEX_A78_ACTLR5_EL1, x1 217workaround_reset_end cortex_a78, ERRATUM(2742426) 218 219check_erratum_ls cortex_a78, ERRATUM(2742426), CPU_REV(1, 2) 220 221workaround_runtime_start cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019 222 /* dsb before isb of power down sequence */ 223 dsb sy 224workaround_runtime_end cortex_a78, ERRATUM(2772019) 225 226check_erratum_ls cortex_a78, ERRATUM(2772019), CPU_REV(1, 2) 227 228workaround_reset_start cortex_a78, ERRATUM(2779479), ERRATA_A78_2779479 229 sysreg_bit_set CORTEX_A78_ACTLR3_EL1, BIT(47) 230workaround_reset_end cortex_a78, ERRATUM(2779479) 231 232check_erratum_ls cortex_a78, ERRATUM(2779479), CPU_REV(1, 2) 233 234workaround_reset_start cortex_a78, ERRATUM(3888017), ERRATA_A78_3888017 235 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(22) 236workaround_reset_end cortex_a78, ERRATUM(3888017) 237 238check_erratum_chosen cortex_a78, ERRATUM(3888017), ERRATA_A78_3888017 239 240workaround_reset_start cortex_a78, ERRATUM(4302972), ERRATA_A78_4302972 241 sysreg_bit_set CORTEX_A78_ACTLR5_EL1, BIT(50) 242workaround_reset_end cortex_a78, ERRATUM(4302972) 243 244check_erratum_chosen cortex_a78, ERRATUM(4302972), ERRATA_A78_4302972 245 246workaround_reset_start cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 247#if IMAGE_BL31 248 /* 249 * The Cortex-X1 generic vectors are overridden to apply errata 250 * mitigation on exception entry from lower ELs. 251 */ 252 override_vector_table wa_cve_vbar_cortex_a78 253#endif /* IMAGE_BL31 */ 254workaround_reset_end cortex_a78, CVE(2022, 23960) 255 256check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 257 258/* Disable hardware page aggregation.Enables mitigation for `CVE-2024-5660` */ 259workaround_reset_start cortex_a78, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 260 sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, BIT(46) 261workaround_reset_end cortex_a78, CVE(2024, 5660) 262 263check_erratum_chosen cortex_a78, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 264 265cpu_reset_func_start cortex_a78 266#if ENABLE_FEAT_AMU 267 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 268 sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT 269 270 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 271 sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT 272 273 /* Enable group0 counters */ 274 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 275 msr CPUAMCNTENSET0_EL0, x0 276 277 /* Enable group1 counters */ 278 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 279 msr CPUAMCNTENSET1_EL0, x0 280#endif 281cpu_reset_func_end cortex_a78 282 283 /* --------------------------------------------- 284 * HW will do the cache maintenance while powering down 285 * --------------------------------------------- 286 */ 287func cortex_a78_core_pwr_dwn 288 sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 289 290 apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019 291 292 isb 293 ret 294endfunc cortex_a78_core_pwr_dwn 295 296 /* --------------------------------------------- 297 * This function provides cortex_a78 specific 298 * register information for crash reporting. 299 * It needs to return with x6 pointing to 300 * a list of register names in ascii and 301 * x8 - x15 having values of registers to be 302 * reported. 303 * --------------------------------------------- 304 */ 305.section .rodata.cortex_a78_regs, "aS" 306cortex_a78_regs: /* The ascii list of register names to be reported */ 307 .asciz "cpuectlr_el1", "" 308 309func cortex_a78_cpu_reg_dump 310 adr x6, cortex_a78_regs 311 mrs x8, CORTEX_A78_CPUECTLR_EL1 312 ret 313endfunc cortex_a78_cpu_reg_dump 314 315declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \ 316 cortex_a78_reset_func, \ 317 cortex_a78_core_pwr_dwn 318