1/* 2 * Copyright (c) 2018-2026, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a77.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20cpu_reset_prologue cortex_a77 21 22/* 64-bit only core */ 23#if CTX_INCLUDE_AARCH32_REGS == 1 24#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 25#endif 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31workaround_reset_start cortex_a77, ERRATUM(1160841), ERRATA_A77_1160841 32 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, BIT(0) 33 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, BIT(15) 34workaround_reset_end cortex_a77, ERRATUM(1160841) 35 36check_erratum_ls cortex_a77, ERRATUM(1160841), CPU_REV(0, 0) 37 38workaround_reset_start cortex_a77, ERRATUM(1204882), ERRATA_A77_1204882 39 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, BIT(11) 40workaround_reset_end cortex_a77, ERRATUM(1204882) 41 42check_erratum_ls cortex_a77, ERRATUM(1204882), CPU_REV(0, 0) 43 44workaround_reset_start cortex_a77, ERRATUM(1220737), ERRATA_A77_1220737 45 sysreg_bitfield_insert CORTEX_A77_CPUECTLR_EL1, 3, 24, 2 46workaround_reset_end cortex_a77, ERRATUM(1220737) 47 48check_erratum_ls cortex_a77, ERRATUM(1220737), CPU_REV(0, 0) 49 50workaround_reset_start cortex_a77, ERRATUM(1253791), ERRATA_A77_1253791 51 sysreg_bit_set CORTEX_A77_CPUACTLR3_EL1, BIT(10) 52workaround_reset_end cortex_a77, ERRATUM(1253791) 53 54check_erratum_ls cortex_a77, ERRATUM(1253791), CPU_REV(0, 0) 55 56workaround_reset_start cortex_a77, ERRATUM(1273521), ERRATA_A77_1273521 57 sysreg_bit_set CORTEX_A77_CPUACTLR_EL1, BIT(13) 58workaround_reset_end cortex_a77, ERRATUM(1273521) 59 60check_erratum_ls cortex_a77, ERRATUM(1273521), CPU_REV(0, 0) 61 62workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412 63 /* move cpu revision in again and compare against r0p0 */ 64 mov x0, x7 65 cpu_rev_var_ls CPU_REV(0, 0) 66 cbz x0, 1f 67 68 ldr x0, =0x0 69 msr CORTEX_A77_CPUPSELR_EL3, x0 70 ldr x0, =0x00E8400000 71 msr CORTEX_A77_CPUPOR_EL3, x0 72 ldr x0, =0x00FFE00000 73 msr CORTEX_A77_CPUPMR_EL3, x0 74 ldr x0, =0x4004003FF 75 msr CORTEX_A77_CPUPCR_EL3, x0 76 ldr x0, =0x1 77 msr CORTEX_A77_CPUPSELR_EL3, x0 78 ldr x0, =0x00E8C00040 79 msr CORTEX_A77_CPUPOR_EL3, x0 80 ldr x0, =0x00FFE00040 81 msr CORTEX_A77_CPUPMR_EL3, x0 82 b 2f 831: 84 ldr x0, =0x0 85 msr CORTEX_A77_CPUPSELR_EL3, x0 86 ldr x0, =0x00E8400000 87 msr CORTEX_A77_CPUPOR_EL3, x0 88 ldr x0, =0x00FF600000 89 msr CORTEX_A77_CPUPMR_EL3, x0 90 ldr x0, =0x00E8E00080 91 msr CORTEX_A77_CPUPOR2_EL3, x0 92 ldr x0, =0x00FFE000C0 93 msr CORTEX_A77_CPUPMR2_EL3, x0 942: 95 ldr x0, =0x04004003FF 96 msr CORTEX_A77_CPUPCR_EL3, x0 97workaround_reset_end cortex_a77, ERRATUM(1508412) 98 99check_erratum_ls cortex_a77, ERRATUM(1508412), CPU_REV(1, 0) 100 101workaround_reset_start cortex_a77, ERRATUM(1515815), ERRATA_A77_1515815 102 sysreg_bit_set CORTEX_A77_CPUACTLR_EL1, BIT(11) 103workaround_reset_end cortex_a77, ERRATUM(1515815) 104 105check_erratum_ls cortex_a77, ERRATUM(1515815), CPU_REV(1, 0) 106 107workaround_reset_start cortex_a77, ERRATUM(1791578), ERRATA_A77_1791578 108 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_2 109workaround_reset_end cortex_a77, ERRATUM(1791578) 110 111check_erratum_ls cortex_a77, ERRATUM(1791578), CPU_REV(1, 1) 112 113workaround_reset_start cortex_a77, ERRATUM(1800714), ERRATA_A77_1800714 114 /* Disable allocation of splintered pages in the L2 TLB */ 115 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_53 116workaround_reset_end cortex_a77, ERRATUM(1800714) 117 118check_erratum_ls cortex_a77, ERRATUM(1800714), CPU_REV(1, 1) 119 120workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769 121 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8 122workaround_reset_end cortex_a77, ERRATUM(1925769) 123 124check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1) 125 126workaround_reset_start cortex_a77, ERRATUM(1946167), ERRATA_A77_1946167 127 ldr x0,=0x4 128 msr CORTEX_A77_CPUPSELR_EL3,x0 129 ldr x0,=0x10E3900002 130 msr CORTEX_A77_CPUPOR_EL3,x0 131 ldr x0,=0x10FFF00083 132 msr CORTEX_A77_CPUPMR_EL3,x0 133 ldr x0,=0x2001003FF 134 msr CORTEX_A77_CPUPCR_EL3,x0 135 136 ldr x0,=0x5 137 msr CORTEX_A77_CPUPSELR_EL3,x0 138 ldr x0,=0x10E3800082 139 msr CORTEX_A77_CPUPOR_EL3,x0 140 ldr x0,=0x10FFF00083 141 msr CORTEX_A77_CPUPMR_EL3,x0 142 ldr x0,=0x2001003FF 143 msr CORTEX_A77_CPUPCR_EL3,x0 144 145 ldr x0,=0x6 146 msr CORTEX_A77_CPUPSELR_EL3,x0 147 ldr x0,=0x10E3800200 148 msr CORTEX_A77_CPUPOR_EL3,x0 149 ldr x0,=0x10FFF003E0 150 msr CORTEX_A77_CPUPMR_EL3,x0 151 ldr x0,=0x2001003FF 152 msr CORTEX_A77_CPUPCR_EL3,x0 153workaround_reset_end cortex_a77, ERRATUM(1946167) 154 155check_erratum_ls cortex_a77, ERRATUM(1946167), CPU_REV(1, 1) 156 157workaround_reset_start cortex_a77, ERRATUM(2356587), ERRATA_A77_2356587 158 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_0 159workaround_reset_end cortex_a77, ERRATUM(2356587) 160 161check_erratum_ls cortex_a77, ERRATUM(2356587), CPU_REV(1, 1) 162 163workaround_runtime_start cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100 164 /* dsb before isb of power down sequence */ 165 dsb sy 166workaround_runtime_end cortex_a77, ERRATUM(2743100), NO_ISB 167 168check_erratum_ls cortex_a77, ERRATUM(2743100), CPU_REV(1, 1) 169 170workaround_reset_start cortex_a77, ERRATUM(3888015), ERRATA_A77_3888015 171 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, BIT(22) 172workaround_reset_end cortex_a77, ERRATUM(3888015) 173 174check_erratum_chosen cortex_a77, ERRATUM(3888015), ERRATA_A77_3888015 175 176workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 177#if IMAGE_BL31 178 /* 179 * The Cortex-A77 generic vectors are overridden to apply errata 180 * mitigation on exception entry from lower ELs. 181 */ 182 adr x0, wa_cve_vbar_cortex_a77 183 msr vbar_el3, x0 184#endif /* IMAGE_BL31 */ 185workaround_reset_end cortex_a77, CVE(2022, 23960) 186 187check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 188 189/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 190workaround_reset_start cortex_a77, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 191 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, BIT(46) 192workaround_reset_end cortex_a77, CVE(2024, 5660) 193 194check_erratum_chosen cortex_a77, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 195 196 /* ------------------------------------------------- 197 * The CPU Ops reset function for Cortex-A77. Must follow AAPCS. 198 * ------------------------------------------------- 199 */ 200cpu_reset_func_start cortex_a77 201cpu_reset_func_end cortex_a77 202 203 /* --------------------------------------------- 204 * HW will do the cache maintenance while powering down 205 * --------------------------------------------- 206 */ 207func cortex_a77_core_pwr_dwn 208 /* --------------------------------------------- 209 * Enable CPU power down bit in power control register 210 * --------------------------------------------- 211 */ 212 sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \ 213 CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 214 215 apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100 216 217 isb 218 ret 219endfunc cortex_a77_core_pwr_dwn 220 221 /* --------------------------------------------- 222 * This function provides Cortex-A77 specific 223 * register information for crash reporting. 224 * It needs to return with x6 pointing to 225 * a list of register names in ascii and 226 * x8 - x15 having values of registers to be 227 * reported. 228 * --------------------------------------------- 229 */ 230.section .rodata.cortex_a77_regs, "aS" 231cortex_a77_regs: /* The ascii list of register names to be reported */ 232 .asciz "cpuectlr_el1", "" 233 234func cortex_a77_cpu_reg_dump 235 adr x6, cortex_a77_regs 236 mrs x8, CORTEX_A77_CPUECTLR_EL1 237 ret 238endfunc cortex_a77_cpu_reg_dump 239 240declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ 241 cortex_a77_reset_func, \ 242 cortex_a77_core_pwr_dwn 243