1/* 2 * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cortex_a75.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13 14.global check_erratum_cortex_a75_764081 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21cpu_reset_prologue cortex_a75 22 23/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */ 24add_erratum_entry cortex_a75, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960 25 26check_erratum_chosen cortex_a75, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960 27 28workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081 29 sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT 30workaround_reset_end cortex_a75, ERRATUM(764081) 31 32check_erratum_ls cortex_a75, ERRATUM(764081), CPU_REV(0, 0) 33 34workaround_reset_start cortex_a75, ERRATUM(790748), ERRATA_A75_790748 35 sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, (1 << 13) 36workaround_reset_end cortex_a75, ERRATUM(790748) 37 38check_erratum_ls cortex_a75, ERRATUM(790748), CPU_REV(0, 0) 39 40workaround_reset_start cortex_a75, ERRATUM(798953), ERRATA_DSU_798953 41 errata_dsu_798953_wa_impl 42workaround_reset_end cortex_a75, ERRATUM(798953) 43 44check_erratum_custom_start cortex_a75, ERRATUM(798953) 45 check_errata_dsu_798953_impl 46 ret 47check_erratum_custom_end cortex_a75, ERRATUM(798953) 48 49workaround_reset_start cortex_a75, ERRATUM(936184), ERRATA_DSU_936184 50 errata_dsu_936184_wa_impl 51workaround_reset_end cortex_a75, ERRATUM(936184) 52 53check_erratum_custom_start cortex_a75, ERRATUM(936184) 54 check_errata_dsu_936184_impl 55 ret 56check_erratum_custom_end cortex_a75, ERRATUM(936184) 57 58workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 59#if IMAGE_BL31 60 override_vector_table wa_cve_2017_5715_bpiall_vbar 61#endif /* IMAGE_BL31 */ 62workaround_reset_end cortex_a75, CVE(2017, 5715) 63 64check_erratum_custom_start cortex_a75, CVE(2017, 5715) 65 cpu_check_csv2 x0, 1f 66#if WORKAROUND_CVE_2017_5715 67 mov x0, #ERRATA_APPLIES 68#else 69 mov x0, #ERRATA_MISSING 70#endif 71 ret 721: 73 mov x0, #ERRATA_NOT_APPLIES 74 ret 75check_erratum_custom_end cortex_a75, CVE(2017, 5715) 76 77workaround_reset_start cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 78 sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE 79workaround_reset_end cortex_a75, CVE(2018, 3639) 80 81check_erratum_chosen cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 82 83workaround_reset_start cortex_a75, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 84#if IMAGE_BL31 85 /* Skip installing vector table again if already done for CVE(2017, 5715) */ 86 adr x0, wa_cve_2017_5715_bpiall_vbar 87 mrs x1, vbar_el3 88 cmp x0, x1 89 b.eq 1f 90 msr vbar_el3, x0 911: 92#endif /* IMAGE_BL31 */ 93workaround_reset_end cortex_a75, CVE(2022, 23960) 94 95check_erratum_custom_start cortex_a75, CVE(2022, 23960) 96#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 97 cpu_check_csv2 x0, 1f 98 mov x0, #ERRATA_APPLIES 99 ret 1001: 101# if WORKAROUND_CVE_2022_23960 102 mov x0, #ERRATA_APPLIES 103# else 104 mov x0, #ERRATA_MISSING 105# endif /* WORKAROUND_CVE_2022_23960 */ 106 ret 107#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 108 mov x0, #ERRATA_MISSING 109 ret 110check_erratum_custom_end cortex_a75, CVE(2022, 23960) 111 112 /* ------------------------------------------------- 113 * The CPU Ops reset function for Cortex-A75. 114 * ------------------------------------------------- 115 */ 116 117cpu_reset_func_start cortex_a75 118#if ENABLE_FEAT_AMU 119 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 120 sysreg_bit_set actlr_el3, CORTEX_A75_ACTLR_AMEN_BIT 121 isb 122 123 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 124 sysreg_bit_set actlr_el2, CORTEX_A75_ACTLR_AMEN_BIT 125 isb 126 127 /* Enable group0 counters */ 128 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 129 msr CPUAMCNTENSET_EL0, x0 130 isb 131 132 /* Enable group1 counters */ 133 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 134 msr CPUAMCNTENSET_EL0, x0 135 /* isb included in cpu_reset_func_end macro */ 136#endif 137cpu_reset_func_end cortex_a75 138 139 /* --------------------------------------------- 140 * HW will do the cache maintenance while powering down 141 * --------------------------------------------- 142 */ 143func cortex_a75_core_pwr_dwn 144 /* --------------------------------------------- 145 * Enable CPU power down bit in power control register 146 * --------------------------------------------- 147 */ 148 sysreg_bit_set CORTEX_A75_CPUPWRCTLR_EL1, \ 149 CORTEX_A75_CORE_PWRDN_EN_MASK 150 isb 151 ret 152endfunc cortex_a75_core_pwr_dwn 153 154 /* --------------------------------------------- 155 * This function provides cortex_a75 specific 156 * register information for crash reporting. 157 * It needs to return with x6 pointing to 158 * a list of register names in ascii and 159 * x8 - x15 having values of registers to be 160 * reported. 161 * --------------------------------------------- 162 */ 163.section .rodata.cortex_a75_regs, "aS" 164cortex_a75_regs: /* The ascii list of register names to be reported */ 165 .asciz "cpuectlr_el1", "" 166 167func cortex_a75_cpu_reg_dump 168 adr x6, cortex_a75_regs 169 mrs x8, CORTEX_A75_CPUECTLR_EL1 170 ret 171endfunc cortex_a75_cpu_reg_dump 172 173declare_cpu_ops cortex_a75, CORTEX_A75_MIDR, \ 174 cortex_a75_reset_func, \ 175 cortex_a75_core_pwr_dwn 176