1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a725.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A725 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A725 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue cortex_a725 26 27.global check_erratum_cortex_a725_3699564 28 29#if ENABLE_SPE_FOR_NS 30workaround_reset_start cortex_a725, ERRATUM(2874943), ERRATA_A725_2874943 31 sysreg_bit_set CORTEX_A725_CPUACTLR_EL1, BIT(57) 32 sysreg_bit_set CORTEX_A725_CPUACTLR_EL1, BIT(58) 33workaround_reset_end cortex_a725, ERRATUM(2874943) 34 35check_erratum_ls cortex_a725, ERRATUM(2874943), CPU_REV(0, 0) 36#endif 37 38workaround_reset_start cortex_a725, ERRATUM(2900952), ERRATA_DSU_2900952 39 errata_dsu_2900952_wa_apply 40workaround_reset_end cortex_a725, ERRATUM(2900952) 41 42check_erratum_custom_start cortex_a725, ERRATUM(2900952) 43 check_errata_dsu_2900952_applies 44 ret 45check_erratum_custom_end cortex_a725, ERRATUM(2900952) 46 47workaround_reset_start cortex_a725, ERRATUM(2936490), ERRATA_A725_2936490 48 sysreg_bit_set CORTEX_A725_CPUACTLR2_EL1, BIT(37) 49workaround_reset_end cortex_a725, ERRATUM(2936490) 50 51check_erratum_ls cortex_a725, ERRATUM(2936490), CPU_REV(0, 0) 52 53workaround_runtime_start cortex_a725, ERRATUM(3456106), ERRATA_A725_3456106 54 speculation_barrier 55workaround_runtime_end cortex_a725, ERRATUM(3456106) 56 57/* Due to the nature of the errata it is applied unconditionally when chosen */ 58check_erratum_chosen cortex_a725, ERRATUM(3456106), ERRATA_A725_3456106 59 60add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564 61 62check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1) 63 64workaround_reset_start cortex_a725, ERRATUM(3711914), ERRATA_A725_3711914 65 mov x0, #5 66 msr CORTEX_A725_CPUPSELR_EL3, x0 67 isb 68 69 ldr x0, =0xd503329f 70 msr CORTEX_A725_CPUPOR_EL3, x0 71 ldr x0, =0xfffff3ff 72 msr CORTEX_A725_CPUPMR_EL3, x0 73 mov x1, #0 74 orr x1, x1, #(1<<0) 75 orr x1, x1, #(3<<4) 76 orr x1, x1, #(0xf<<6) 77 orr x1, x1, #(1<<22) 78 orr x1, x1, #(1<<32) 79 msr CORTEX_A725_CPUPCR_EL3, x1 80 isb 81workaround_reset_end cortex_a725, ERRATUM(3711914) 82 83check_erratum_ls cortex_a725, ERRATUM(3711914), CPU_REV(0, 1) 84 85cpu_reset_func_start cortex_a725 86 /* Disable speculative loads */ 87 msr SSBS, xzr 88 apply_erratum cortex_a725, ERRATUM(3456106), ERRATA_A725_3456106 89 enable_mpmm 90cpu_reset_func_end cortex_a725 91 92 /* ---------------------------------------------------- 93 * HW will do the cache maintenance while powering down 94 * ---------------------------------------------------- 95 */ 96func cortex_a725_core_pwr_dwn 97 /* --------------------------------------------------- 98 * Enable CPU power down bit in power control register 99 * --------------------------------------------------- 100 */ 101 sysreg_bit_set CORTEX_A725_CPUPWRCTLR_EL1, CORTEX_A725_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 102 isb 103 ret 104endfunc cortex_a725_core_pwr_dwn 105 106 /* --------------------------------------------- 107 * This function provides Cortex-A725 specific 108 * register information for crash reporting. 109 * It needs to return with x6 pointing to 110 * a list of register names in ascii and 111 * x8 - x15 having values of registers to be 112 * reported. 113 * --------------------------------------------- 114 */ 115.section .rodata.cortex_a725_regs, "aS" 116cortex_a725_regs: /* The ascii list of register names to be reported */ 117 .asciz "cpuectlr_el1", "" 118 119func cortex_a725_cpu_reg_dump 120 adr x6, cortex_a725_regs 121 mrs x8, CORTEX_A725_CPUECTLR_EL1 122 ret 123endfunc cortex_a725_cpu_reg_dump 124 125declare_cpu_ops cortex_a725, CORTEX_A725_MIDR, \ 126 cortex_a725_reset_func, \ 127 cortex_a725_core_pwr_dwn 128