1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a725.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A725 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A725 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue cortex_a725 26 27.global check_erratum_cortex_a725_3699564 28 29#if ENABLE_SPE_FOR_NS 30workaround_reset_start cortex_a725, ERRATUM(2874943), ERRATA_A725_2874943 31 sysreg_lazy_start CORTEX_A725_CPUACTLR_EL1 32 sysreg_lazy_set BIT(57) 33 sysreg_lazy_set BIT(58) 34 sysreg_lazy_commit CORTEX_A725_CPUACTLR_EL1 35workaround_reset_end cortex_a725, ERRATUM(2874943) 36 37check_erratum_ls cortex_a725, ERRATUM(2874943), CPU_REV(0, 0) 38#endif 39 40workaround_reset_start cortex_a725, ERRATUM(2900952), ERRATA_DSU_2900952 41 errata_dsu_2900952_wa_apply 42workaround_reset_end cortex_a725, ERRATUM(2900952) 43 44check_erratum_custom_start cortex_a725, ERRATUM(2900952) 45 check_errata_dsu_2900952_applies 46 ret 47check_erratum_custom_end cortex_a725, ERRATUM(2900952) 48 49workaround_reset_start cortex_a725, ERRATUM(2936490), ERRATA_A725_2936490 50 sysreg_bit_set CORTEX_A725_CPUACTLR2_EL1, BIT(37) 51workaround_reset_end cortex_a725, ERRATUM(2936490) 52 53check_erratum_ls cortex_a725, ERRATUM(2936490), CPU_REV(0, 0) 54 55workaround_runtime_start cortex_a725, ERRATUM(3456106), ERRATA_A725_3456106 56 speculation_barrier 57workaround_runtime_end cortex_a725, ERRATUM(3456106) 58 59/* Due to the nature of the errata it is applied unconditionally when chosen */ 60check_erratum_chosen cortex_a725, ERRATUM(3456106), ERRATA_A725_3456106 61 62add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564 63 64check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1) 65 66workaround_reset_start cortex_a725, ERRATUM(3711914), ERRATA_A725_3711914 67 mov x0, #5 68 msr CORTEX_A725_CPUPSELR_EL3, x0 69 isb 70 71 ldr x0, =0xd503329f 72 msr CORTEX_A725_CPUPOR_EL3, x0 73 ldr x0, =0xfffff3ff 74 msr CORTEX_A725_CPUPMR_EL3, x0 75 mov x1, #0 76 orr x1, x1, #(1<<0) 77 orr x1, x1, #(3<<4) 78 orr x1, x1, #(0xf<<6) 79 orr x1, x1, #(1<<22) 80 orr x1, x1, #(1<<32) 81 msr CORTEX_A725_CPUPCR_EL3, x1 82 isb 83workaround_reset_end cortex_a725, ERRATUM(3711914) 84 85check_erratum_ls cortex_a725, ERRATUM(3711914), CPU_REV(0, 1) 86 87cpu_reset_func_start cortex_a725 88 /* Disable speculative loads */ 89 msr SSBS, xzr 90 apply_erratum cortex_a725, ERRATUM(3456106), ERRATA_A725_3456106 91 enable_mpmm 92cpu_reset_func_end cortex_a725 93 94 /* ---------------------------------------------------- 95 * HW will do the cache maintenance while powering down 96 * ---------------------------------------------------- 97 */ 98func cortex_a725_core_pwr_dwn 99 /* --------------------------------------------------- 100 * Enable CPU power down bit in power control register 101 * --------------------------------------------------- 102 */ 103 sysreg_bit_set CORTEX_A725_CPUPWRCTLR_EL1, CORTEX_A725_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 104 isb 105 ret 106endfunc cortex_a725_core_pwr_dwn 107 108 /* --------------------------------------------- 109 * This function provides Cortex-A725 specific 110 * register information for crash reporting. 111 * It needs to return with x6 pointing to 112 * a list of register names in ascii and 113 * x8 - x15 having values of registers to be 114 * reported. 115 * --------------------------------------------- 116 */ 117.section .rodata.cortex_a725_regs, "aS" 118cortex_a725_regs: /* The ascii list of register names to be reported */ 119 .asciz "cpuectlr_el1", "" 120 121func cortex_a725_cpu_reg_dump 122 adr x6, cortex_a725_regs 123 mrs x8, CORTEX_A725_CPUECTLR_EL1 124 ret 125endfunc cortex_a725_cpu_reg_dump 126 127declare_cpu_ops cortex_a725, CORTEX_A725_MIDR, \ 128 cortex_a725_reset_func, \ 129 cortex_a725_core_pwr_dwn 130