1/* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a72.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14#if WORKAROUND_CVE_2022_23960 15 wa_cve_2022_23960_bhb_vector_table CORTEX_A72_BHB_LOOP_COUNT, cortex_a72 16#endif /* WORKAROUND_CVE_2022_23960 */ 17 18cpu_reset_prologue cortex_a72 19 20 /* --------------------------------------------- 21 * Disable all types of L2 prefetches. 22 * --------------------------------------------- 23 */ 24func cortex_a72_disable_l2_prefetch 25 mrs x0, CORTEX_A72_ECTLR_EL1 26 orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 27 mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK 28 orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK 29 bic x0, x0, x1 30 msr CORTEX_A72_ECTLR_EL1, x0 31 isb 32 ret 33endfunc cortex_a72_disable_l2_prefetch 34 35 /* --------------------------------------------- 36 * Disable the load-store hardware prefetcher. 37 * --------------------------------------------- 38 */ 39func cortex_a72_disable_hw_prefetcher 40 sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH 41 isb 42 dsb ish 43 ret 44endfunc cortex_a72_disable_hw_prefetcher 45 46 /* --------------------------------------------- 47 * Disable intra-cluster coherency 48 * --------------------------------------------- 49 */ 50func cortex_a72_disable_smp 51 sysreg_bit_clear CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT 52 ret 53endfunc cortex_a72_disable_smp 54 55 /* --------------------------------------------- 56 * Disable debug interfaces 57 * --------------------------------------------- 58 */ 59func cortex_a72_disable_ext_debug 60 mov x0, #1 61 msr osdlr_el1, x0 62 isb 63 dsb sy 64 ret 65endfunc cortex_a72_disable_ext_debug 66 67check_erratum_ls cortex_a72, ERRATUM(ARCH_WORKAROUND_3), CPU_REV(1, 0) 68 69/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */ 70add_erratum_entry cortex_a72, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960 71 72workaround_reset_start cortex_a72, ERRATUM(859971), ERRATA_A72_859971 73 sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH 74workaround_reset_end cortex_a72, ERRATUM(859971) 75 76check_erratum_ls cortex_a72, ERRATUM(859971), CPU_REV(0, 3) 77 78/* Due to the nature of the errata it is applied unconditionally when chosen */ 79check_erratum_chosen cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367 80/* erratum workaround is interleaved with generic code */ 81add_erratum_entry cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367 82 83workaround_reset_start cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 84#if IMAGE_BL31 85 override_vector_table wa_cve_2017_5715_mmu_vbar 86#endif 87workaround_reset_end cortex_a72, CVE(2017, 5715) 88 89/* r1p0 implements FEAT_CSV2 */ 90check_erratum_ls cortex_a72, CVE(2017, 5715), CPU_REV(1, 0) 91 92workaround_reset_start cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 93 sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE 94 isb 95 dsb sy 96workaround_reset_end cortex_a72, CVE(2018, 3639) 97check_erratum_chosen cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 98 99workaround_reset_start cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 100#if IMAGE_BL31 101 /* Skip installing vector table again if already done for CVE(2017, 5715) */ 102 /* 103 * The Cortex-A72 generic vectors are overridden to apply the 104 * mitigation on exception entry from lower ELs for revisions >= r1p0 105 * which has CSV2 implemented. 106 */ 107 adr x0, wa_cve_vbar_cortex_a72 108 mrs x1, vbar_el3 109 cmp x0, x1 110 b.eq 1f 111 msr vbar_el3, x0 1121: 113#endif /* IMAGE_BL31 */ 114workaround_reset_end cortex_a72, CVE(2022, 23960) 115 116check_erratum_custom_start cortex_a72, CVE(2022, 23960) 117#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 118 cpu_check_csv2 x0, 1f 119 mov x0, #ERRATA_APPLIES 120 ret 1211: 122#if WORKAROUND_CVE_2022_23960 123 mov x0, #ERRATA_APPLIES 124#else 125 mov x0, #ERRATA_MISSING 126#endif /* WORKAROUND_CVE_2022_23960 */ 127 ret 128#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 129 mov x0, #ERRATA_MISSING 130 ret 131check_erratum_custom_end cortex_a72, CVE(2022, 23960) 132 133cpu_reset_func_start cortex_a72 134 135 /* --------------------------------------------- 136 * Enable the SMP bit. 137 * --------------------------------------------- 138 */ 139 sysreg_bit_set CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT 140 141cpu_reset_func_end cortex_a72 142 143 /* ---------------------------------------------------- 144 * The CPU Ops core power down function for Cortex-A72. 145 * ---------------------------------------------------- 146 */ 147func cortex_a72_core_pwr_dwn 148 mov x18, x30 149 150 /* --------------------------------------------- 151 * Disable the L2 prefetches. 152 * --------------------------------------------- 153 */ 154 bl cortex_a72_disable_l2_prefetch 155 156 /* --------------------------------------------- 157 * Disable the load-store hardware prefetcher. 158 * --------------------------------------------- 159 */ 160 bl cortex_a72_disable_hw_prefetcher 161 162 /* --------------------------------------------- 163 * Flush L1 caches. 164 * --------------------------------------------- 165 */ 166 mov x0, #DCCISW 167 bl dcsw_op_level1 168 169 /* --------------------------------------------- 170 * Come out of intra cluster coherency 171 * --------------------------------------------- 172 */ 173 bl cortex_a72_disable_smp 174 175 /* --------------------------------------------- 176 * Force the debug interfaces to be quiescent 177 * --------------------------------------------- 178 */ 179 mov x30, x18 180 b cortex_a72_disable_ext_debug 181endfunc cortex_a72_core_pwr_dwn 182 183 /* ------------------------------------------------------- 184 * The CPU Ops cluster power down function for Cortex-A72. 185 * ------------------------------------------------------- 186 */ 187func cortex_a72_cluster_pwr_dwn 188 mov x18, x30 189 190 /* --------------------------------------------- 191 * Disable the L2 prefetches. 192 * --------------------------------------------- 193 */ 194 bl cortex_a72_disable_l2_prefetch 195 196 /* --------------------------------------------- 197 * Disable the load-store hardware prefetcher. 198 * --------------------------------------------- 199 */ 200 bl cortex_a72_disable_hw_prefetcher 201 202#if !SKIP_A72_L1_FLUSH_PWR_DWN 203 /* --------------------------------------------- 204 * Flush L1 caches. 205 * --------------------------------------------- 206 */ 207 mov x0, #DCCISW 208 bl dcsw_op_level1 209#endif 210 211 /* --------------------------------------------- 212 * Disable the optional ACP. 213 * --------------------------------------------- 214 */ 215 bl plat_disable_acp 216 217 /* ------------------------------------------------- 218 * Flush the L2 caches. 219 * ------------------------------------------------- 220 */ 221 mov x0, #DCCISW 222 bl dcsw_op_level2 223 224 /* --------------------------------------------- 225 * Come out of intra cluster coherency 226 * --------------------------------------------- 227 */ 228 bl cortex_a72_disable_smp 229 230 /* --------------------------------------------- 231 * Force the debug interfaces to be quiescent 232 * --------------------------------------------- 233 */ 234 mov x30, x18 235 b cortex_a72_disable_ext_debug 236endfunc cortex_a72_cluster_pwr_dwn 237 238 /* --------------------------------------------- 239 * This function provides cortex_a72 specific 240 * register information for crash reporting. 241 * It needs to return with x6 pointing to 242 * a list of register names in ascii and 243 * x8 - x15 having values of registers to be 244 * reported. 245 * --------------------------------------------- 246 */ 247.section .rodata.cortex_a72_regs, "aS" 248cortex_a72_regs: /* The ascii list of register names to be reported */ 249 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 250 251func cortex_a72_cpu_reg_dump 252 adr x6, cortex_a72_regs 253 mrs x8, CORTEX_A72_ECTLR_EL1 254 mrs x9, CORTEX_A72_MERRSR_EL1 255 mrs x10, CORTEX_A72_L2MERRSR_EL1 256 ret 257endfunc cortex_a72_cpu_reg_dump 258 259declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ 260 cortex_a72_reset_func, \ 261 cortex_a72_core_pwr_dwn, \ 262 cortex_a72_cluster_pwr_dwn 263