1/* 2 * Copyright (c) 2024-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_premium.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Premium must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Premium supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Premium needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_premium 30 31cpu_reset_func_start c1_premium 32 /* Disable speculative loads */ 33 msr SSBS, xzr 34 enable_mpmm 35cpu_reset_func_end c1_premium 36 37func c1_premium_core_pwr_dwn 38 /* --------------------------------------------------- 39 * Flip CPU power down bit in power control register. 40 * It will be set on powerdown and cleared on wakeup. 41 * --------------------------------------------------- 42 */ 43 sysreg_bit_toggle C1_PREMIUM_IMP_CPUPWRCTLR_EL1, \ 44 C1_PREMIUM_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 45 isb 46 signal_pabandon_handled 47 ret 48endfunc c1_premium_core_pwr_dwn 49 50.section .rodata.c1_premium_regs, "aS" 51c1_premium_regs: /* The ASCII list of register names to be reported */ 52 .asciz "cpuectlr_el1", "" 53 54func c1_premium_cpu_reg_dump 55 adr x6, c1_premium_regs 56 mrs x8, C1_PREMIUM_IMP_CPUECTLR_EL1 57 ret 58endfunc c1_premium_cpu_reg_dump 59 60declare_cpu_ops c1_premium, C1_PREMIUM_MIDR, \ 61 c1_premium_reset_func, \ 62 c1_premium_core_pwr_dwn 63