1/* 2 * Copyright (c) 2024-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_premium.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12#include <wa_cve_2025_0647_cpprctx.h> 13 14#include <plat_macros.S> 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Arm C1-Premium must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Arm C1-Premium supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26cpu_reset_prologue c1_premium 27 28workaround_runtime_start c1_premium, ERRATUM(3324333), ERRATA_C1PREMIUM_3324333 29 speculation_barrier 30workaround_runtime_end c1_premium, ERRATUM(3324333) 31 32check_erratum_ls c1_premium, ERRATUM(3324333), CPU_REV(0, 0) 33 34workaround_reset_start c1_premium, ERRATUM(3502731), ERRATA_C1PREMIUM_3502731 35 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR4_EL1, BIT(23) 36workaround_reset_end c1_premium, ERRATUM(3502731) 37 38check_erratum_ls c1_premium, ERRATUM(3502731), CPU_REV(0, 0) 39 40workaround_reset_start c1_premium, ERRATUM(3684152), ERRATA_C1PREMIUM_3684152 41 sysreg_bitfield_insert C1_PREMIUM_IMP_CPUACTLR_EL1, C1_PREMIUM_IMP_CPUACTLR_EL1_LOAD_BIT, \ 42 C1_PREMIUM_IMP_CPUACTLR_EL1_LOAD_SHIFT, C1_PREMIUM_IMP_CPUACTLR_EL1_LOAD_WIDTH 43workaround_reset_end c1_premium, ERRATUM(3684152) 44 45check_erratum_ls c1_premium, ERRATUM(3684152), CPU_REV(0, 0) 46 47workaround_reset_start c1_premium, ERRATUM(3705939), ERRATA_C1PREMIUM_3705939 48 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR_EL1, BIT(48) 49workaround_reset_end c1_premium, ERRATUM(3705939) 50 51check_erratum_ls c1_premium, ERRATUM(3705939), CPU_REV(1, 0) 52 53workaround_reset_start c1_premium, ERRATUM(3815514), ERRATA_C1PREMIUM_3815514 54 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR5_EL1, BIT(13) 55workaround_reset_end c1_premium, ERRATUM(3815514) 56 57check_erratum_ls c1_premium, ERRATUM(3815514), CPU_REV(1, 0) 58 59workaround_reset_start c1_premium, ERRATUM(3865171), ERRATA_C1PREMIUM_3865171 60 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR2_EL1, BIT(22) 61workaround_reset_end c1_premium, ERRATUM(3865171) 62 63check_erratum_ls c1_premium, ERRATUM(3865171), CPU_REV(1, 0) 64 65workaround_reset_start c1_premium, ERRATUM(3926381), ERRATA_C1PREMIUM_3926381 66 /* Convert WFx to NOP */ 67 ldr x0,=0x0 68 msr C1_PREMIUM_IMP_CPUPSELR_EL3, x0 69 ldr x0,=0xD503205f 70 msr C1_PREMIUM_IMP_CPUPOR_EL3, x0 71 ldr x0,=0xFFFFFFDF 72 msr C1_PREMIUM_IMP_CPUPMR_EL3, x0 73 ldr x0,=0x1000002043ff 74 msr C1_PREMIUM_IMP_CPUPCR_EL3, x0 75 76 /* Convert WFxT to NOP */ 77 ldr x0,=0x1 78 msr C1_PREMIUM_IMP_CPUPSELR_EL3, x0 79 ldr x0,=0xD5031000 80 msr C1_PREMIUM_IMP_CPUPOR_EL3, x0 81 ldr x0,=0xFFFFFFC0 82 msr C1_PREMIUM_IMP_CPUPMR_EL3, x0 83 ldr x0,=0x1000002043ff 84 msr C1_PREMIUM_IMP_CPUPCR_EL3, x0 85 isb 86workaround_reset_end c1_premium, ERRATUM(3926381) 87 88check_erratum_range c1_premium, ERRATUM(3926381), CPU_REV(1, 0), CPU_REV(1, 0) 89 90workaround_reset_start c1_premium, ERRATUM(4102704), ERRATA_C1PREMIUM_4102704 91 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR4_EL1, BIT(23) 92workaround_reset_end c1_premium, ERRATUM(4102704) 93 94check_erratum_ls c1_premium, ERRATUM(4102704), CPU_REV(1, 0) 95 96 /* --------------------------------------------------------------- 97 * CVE-2024-7881 is mitigated for C1-Premium using erratum 3651221 98 * workaround by disabling the affected prefetcher setting 99 * CPUACTLR6_EL1[41]. 100 * --------------------------------------------------------------- 101 */ 102workaround_reset_start c1_premium, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 103 sysreg_bit_set C1_PREMIUM_CPUACTLR6_EL1, BIT(41) 104workaround_reset_end c1_premium, CVE(2024, 7881) 105 106check_erratum_ls c1_premium, CVE(2024, 7881), CPU_REV(0, 0) 107 108 /* 109 * Instruction patch sequence to trap 'cpp rctx' instructions to EL3. 110 * Enables mitigation for CVE-2025-0647. 111 */ 112workaround_reset_start c1_premium, CVE(2025, 647), WORKAROUND_CVE_2025_0647 113#if IMAGE_BL31 114 mov x0, #WA_PATCH_SLOT(3) 115 bl wa_cve_2025_0647_instruction_patch 116#endif /* IMAGE_BL31 */ 117workaround_reset_end c1_premium, CVE(2025, 647) 118 119check_erratum_chosen c1_premium, CVE(2025, 647), WORKAROUND_CVE_2025_0647 120 121#if WORKAROUND_CVE_2025_0647 122func c1_premium_impl_defined_el3_handler 123 mov x0, #WA_LS_RCG_EN 124 125 /* See if this call came from trap handler. */ 126 cmp x1, #EC_IMP_DEF_EL3 127 bne wa_cve_2025_0647_do_cpp_wa 128 orr x0, x0, #WA_IS_TRAP_HANDLER 129 b wa_cve_2025_0647_do_cpp_wa 130endfunc c1_premium_impl_defined_el3_handler 131#endif 132 133cpu_reset_func_start c1_premium 134 /* Disable speculative loads */ 135 msr SSBS, xzr 136 apply_erratum c1_premium, ERRATUM(3324333), ERRATA_C1PREMIUM_3324333 137 enable_mpmm 138cpu_reset_func_end c1_premium 139 140func c1_premium_core_pwr_dwn 141 /* 142 * When software running at lower ELs requests power down without first 143 * disabling SME, the CME connected to it will reject its power down 144 * request. Skip setting the PWRDN_EN bit, downgrading the powerdown 145 * request to a simple WFI wait, to get a minimal amount of power saving 146 * rather than an instant pabandon. 147 */ 148 mrs x0, SVCR 149 cbnz x0, c1_premium_skip_pwr_dwn 150 151 /* --------------------------------------------------- 152 * Flip CPU power down bit in power control register. 153 * It will be set on powerdown and cleared on wakeup. 154 * --------------------------------------------------- 155 */ 156 sysreg_bit_toggle C1_PREMIUM_IMP_CPUPWRCTLR_EL1, \ 157 C1_PREMIUM_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 158 isb 159c1_premium_skip_pwr_dwn: 160 signal_pabandon_handled 161 ret 162endfunc c1_premium_core_pwr_dwn 163 164.section .rodata.c1_premium_regs, "aS" 165c1_premium_regs: /* The ASCII list of register names to be reported */ 166 .asciz "cpuectlr_el1", "" 167 168func c1_premium_cpu_reg_dump 169 adr x6, c1_premium_regs 170 mrs x8, C1_PREMIUM_IMP_CPUECTLR_EL1 171 ret 172endfunc c1_premium_cpu_reg_dump 173 174#if WORKAROUND_CVE_2025_0647 && IMAGE_BL31 175declare_cpu_ops_eh c1_premium, C1_PREMIUM_MIDR, \ 176 c1_premium_reset_func, \ 177 c1_premium_impl_defined_el3_handler, \ 178 c1_premium_core_pwr_dwn 179#else 180declare_cpu_ops c1_premium, C1_PREMIUM_MIDR, \ 181 c1_premium_reset_func, \ 182 c1_premium_core_pwr_dwn 183#endif 184