1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/mux/ti-serdes.h> 10 11/ { 12 cmn_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17 18 cmn_refclk1: clock-cmnrefclk1 { 19 #clock-cells = <0>; 20 compatible = "fixed-clock"; 21 clock-frequency = <0>; 22 }; 23}; 24 25&cbass_main { 26 msmc_ram: sram@70000000 { 27 compatible = "mmio-sram"; 28 reg = <0x0 0x70000000 0x0 0x800000>; 29 #address-cells = <1>; 30 #size-cells = <1>; 31 ranges = <0x0 0x0 0x70000000 0x800000>; 32 33 atf-sram@0 { 34 reg = <0x0 0x20000>; 35 }; 36 }; 37 38 scm_conf: scm-conf@100000 { 39 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 40 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 41 #address-cells = <1>; 42 #size-cells = <1>; 43 ranges = <0x0 0x0 0x00100000 0x1c000>; 44 45 pcie0_ctrl: syscon@4070 { 46 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 47 reg = <0x00004070 0x4>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 ranges = <0x4070 0x4070 0x4>; 51 }; 52 53 pcie1_ctrl: syscon@4074 { 54 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 55 reg = <0x00004074 0x4>; 56 #address-cells = <1>; 57 #size-cells = <1>; 58 ranges = <0x4074 0x4074 0x4>; 59 }; 60 61 pcie2_ctrl: syscon@4078 { 62 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 63 reg = <0x00004078 0x4>; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 ranges = <0x4078 0x4078 0x4>; 67 }; 68 69 pcie3_ctrl: syscon@407c { 70 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 71 reg = <0x0000407c 0x4>; 72 #address-cells = <1>; 73 #size-cells = <1>; 74 ranges = <0x407c 0x407c 0x4>; 75 }; 76 77 serdes_ln_ctrl: mux@4080 { 78 compatible = "mmio-mux"; 79 reg = <0x00004080 0x50>; 80 #mux-control-cells = <1>; 81 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 82 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 83 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 84 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 85 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 86 /* SERDES4 lane0/1/2/3 select */ 87 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 88 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 89 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 90 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 91 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 92 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 93 }; 94 95 usb_serdes_mux: mux-controller@4000 { 96 compatible = "mmio-mux"; 97 #mux-control-cells = <1>; 98 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 99 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 100 }; 101 }; 102 103 gic500: interrupt-controller@1800000 { 104 compatible = "arm,gic-v3"; 105 #address-cells = <2>; 106 #size-cells = <2>; 107 ranges; 108 #interrupt-cells = <3>; 109 interrupt-controller; 110 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 111 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 112 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 113 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 114 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 115 116 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 117 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 118 119 gic_its: msi-controller@1820000 { 120 compatible = "arm,gic-v3-its"; 121 reg = <0x00 0x01820000 0x00 0x10000>; 122 socionext,synquacer-pre-its = <0x1000000 0x400000>; 123 msi-controller; 124 #msi-cells = <1>; 125 }; 126 }; 127 128 main_gpio_intr: interrupt-controller0 { 129 compatible = "ti,sci-intr"; 130 ti,intr-trigger-type = <1>; 131 interrupt-controller; 132 interrupt-parent = <&gic500>; 133 #interrupt-cells = <1>; 134 ti,sci = <&dmsc>; 135 ti,sci-dev-id = <131>; 136 ti,interrupt-ranges = <8 392 56>; 137 }; 138 139 main-navss { 140 compatible = "simple-mfd"; 141 #address-cells = <2>; 142 #size-cells = <2>; 143 ranges; 144 dma-coherent; 145 dma-ranges; 146 147 ti,sci-dev-id = <199>; 148 149 main_navss_intr: interrupt-controller1 { 150 compatible = "ti,sci-intr"; 151 ti,intr-trigger-type = <4>; 152 interrupt-controller; 153 interrupt-parent = <&gic500>; 154 #interrupt-cells = <1>; 155 ti,sci = <&dmsc>; 156 ti,sci-dev-id = <213>; 157 ti,interrupt-ranges = <0 64 64>, 158 <64 448 64>, 159 <128 672 64>; 160 }; 161 162 main_udmass_inta: interrupt-controller@33d00000 { 163 compatible = "ti,sci-inta"; 164 reg = <0x0 0x33d00000 0x0 0x100000>; 165 interrupt-controller; 166 interrupt-parent = <&main_navss_intr>; 167 msi-controller; 168 ti,sci = <&dmsc>; 169 ti,sci-dev-id = <209>; 170 ti,interrupt-ranges = <0 0 256>; 171 }; 172 173 secure_proxy_main: mailbox@32c00000 { 174 compatible = "ti,am654-secure-proxy"; 175 #mbox-cells = <1>; 176 reg-names = "target_data", "rt", "scfg"; 177 reg = <0x00 0x32c00000 0x00 0x100000>, 178 <0x00 0x32400000 0x00 0x100000>, 179 <0x00 0x32800000 0x00 0x100000>; 180 interrupt-names = "rx_011"; 181 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 182 }; 183 184 smmu0: iommu@36600000 { 185 compatible = "arm,smmu-v3"; 186 reg = <0x0 0x36600000 0x0 0x100000>; 187 interrupt-parent = <&gic500>; 188 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 189 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 190 interrupt-names = "eventq", "gerror"; 191 #iommu-cells = <1>; 192 }; 193 194 hwspinlock: spinlock@30e00000 { 195 compatible = "ti,am654-hwspinlock"; 196 reg = <0x00 0x30e00000 0x00 0x1000>; 197 #hwlock-cells = <1>; 198 }; 199 200 mailbox0_cluster0: mailbox@31f80000 { 201 compatible = "ti,am654-mailbox"; 202 reg = <0x00 0x31f80000 0x00 0x200>; 203 #mbox-cells = <1>; 204 ti,mbox-num-users = <4>; 205 ti,mbox-num-fifos = <16>; 206 interrupt-parent = <&main_navss_intr>; 207 }; 208 209 mailbox0_cluster1: mailbox@31f81000 { 210 compatible = "ti,am654-mailbox"; 211 reg = <0x00 0x31f81000 0x00 0x200>; 212 #mbox-cells = <1>; 213 ti,mbox-num-users = <4>; 214 ti,mbox-num-fifos = <16>; 215 interrupt-parent = <&main_navss_intr>; 216 }; 217 218 mailbox0_cluster2: mailbox@31f82000 { 219 compatible = "ti,am654-mailbox"; 220 reg = <0x00 0x31f82000 0x00 0x200>; 221 #mbox-cells = <1>; 222 ti,mbox-num-users = <4>; 223 ti,mbox-num-fifos = <16>; 224 interrupt-parent = <&main_navss_intr>; 225 }; 226 227 mailbox0_cluster3: mailbox@31f83000 { 228 compatible = "ti,am654-mailbox"; 229 reg = <0x00 0x31f83000 0x00 0x200>; 230 #mbox-cells = <1>; 231 ti,mbox-num-users = <4>; 232 ti,mbox-num-fifos = <16>; 233 interrupt-parent = <&main_navss_intr>; 234 }; 235 236 mailbox0_cluster4: mailbox@31f84000 { 237 compatible = "ti,am654-mailbox"; 238 reg = <0x00 0x31f84000 0x00 0x200>; 239 #mbox-cells = <1>; 240 ti,mbox-num-users = <4>; 241 ti,mbox-num-fifos = <16>; 242 interrupt-parent = <&main_navss_intr>; 243 }; 244 245 mailbox0_cluster5: mailbox@31f85000 { 246 compatible = "ti,am654-mailbox"; 247 reg = <0x00 0x31f85000 0x00 0x200>; 248 #mbox-cells = <1>; 249 ti,mbox-num-users = <4>; 250 ti,mbox-num-fifos = <16>; 251 interrupt-parent = <&main_navss_intr>; 252 }; 253 254 mailbox0_cluster6: mailbox@31f86000 { 255 compatible = "ti,am654-mailbox"; 256 reg = <0x00 0x31f86000 0x00 0x200>; 257 #mbox-cells = <1>; 258 ti,mbox-num-users = <4>; 259 ti,mbox-num-fifos = <16>; 260 interrupt-parent = <&main_navss_intr>; 261 }; 262 263 mailbox0_cluster7: mailbox@31f87000 { 264 compatible = "ti,am654-mailbox"; 265 reg = <0x00 0x31f87000 0x00 0x200>; 266 #mbox-cells = <1>; 267 ti,mbox-num-users = <4>; 268 ti,mbox-num-fifos = <16>; 269 interrupt-parent = <&main_navss_intr>; 270 }; 271 272 mailbox0_cluster8: mailbox@31f88000 { 273 compatible = "ti,am654-mailbox"; 274 reg = <0x00 0x31f88000 0x00 0x200>; 275 #mbox-cells = <1>; 276 ti,mbox-num-users = <4>; 277 ti,mbox-num-fifos = <16>; 278 interrupt-parent = <&main_navss_intr>; 279 }; 280 281 mailbox0_cluster9: mailbox@31f89000 { 282 compatible = "ti,am654-mailbox"; 283 reg = <0x00 0x31f89000 0x00 0x200>; 284 #mbox-cells = <1>; 285 ti,mbox-num-users = <4>; 286 ti,mbox-num-fifos = <16>; 287 interrupt-parent = <&main_navss_intr>; 288 }; 289 290 mailbox0_cluster10: mailbox@31f8a000 { 291 compatible = "ti,am654-mailbox"; 292 reg = <0x00 0x31f8a000 0x00 0x200>; 293 #mbox-cells = <1>; 294 ti,mbox-num-users = <4>; 295 ti,mbox-num-fifos = <16>; 296 interrupt-parent = <&main_navss_intr>; 297 }; 298 299 mailbox0_cluster11: mailbox@31f8b000 { 300 compatible = "ti,am654-mailbox"; 301 reg = <0x00 0x31f8b000 0x00 0x200>; 302 #mbox-cells = <1>; 303 ti,mbox-num-users = <4>; 304 ti,mbox-num-fifos = <16>; 305 interrupt-parent = <&main_navss_intr>; 306 }; 307 308 main_ringacc: ringacc@3c000000 { 309 compatible = "ti,am654-navss-ringacc"; 310 reg = <0x0 0x3c000000 0x0 0x400000>, 311 <0x0 0x38000000 0x0 0x400000>, 312 <0x0 0x31120000 0x0 0x100>, 313 <0x0 0x33000000 0x0 0x40000>; 314 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 315 ti,num-rings = <1024>; 316 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 317 ti,sci = <&dmsc>; 318 ti,sci-dev-id = <211>; 319 msi-parent = <&main_udmass_inta>; 320 }; 321 322 main_udmap: dma-controller@31150000 { 323 compatible = "ti,j721e-navss-main-udmap"; 324 reg = <0x0 0x31150000 0x0 0x100>, 325 <0x0 0x34000000 0x0 0x100000>, 326 <0x0 0x35000000 0x0 0x100000>; 327 reg-names = "gcfg", "rchanrt", "tchanrt"; 328 msi-parent = <&main_udmass_inta>; 329 #dma-cells = <1>; 330 331 ti,sci = <&dmsc>; 332 ti,sci-dev-id = <212>; 333 ti,ringacc = <&main_ringacc>; 334 335 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 336 <0x0f>, /* TX_HCHAN */ 337 <0x10>; /* TX_UHCHAN */ 338 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 339 <0x0b>, /* RX_HCHAN */ 340 <0x0c>; /* RX_UHCHAN */ 341 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 342 }; 343 344 cpts@310d0000 { 345 compatible = "ti,j721e-cpts"; 346 reg = <0x0 0x310d0000 0x0 0x400>; 347 reg-names = "cpts"; 348 clocks = <&k3_clks 201 1>; 349 clock-names = "cpts"; 350 interrupts-extended = <&main_navss_intr 391>; 351 interrupt-names = "cpts"; 352 ti,cpts-periodic-outputs = <6>; 353 ti,cpts-ext-ts-inputs = <8>; 354 }; 355 }; 356 357 main_crypto: crypto@4e00000 { 358 compatible = "ti,j721e-sa2ul"; 359 reg = <0x0 0x4e00000 0x0 0x1200>; 360 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 361 #address-cells = <2>; 362 #size-cells = <2>; 363 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 364 365 status = "okay"; 366 367 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 368 <&main_udmap 0x4001>; 369 dma-names = "tx", "rx1", "rx2"; 370 dma-coherent; 371 372 rng: rng@4e10000 { 373 compatible = "inside-secure,safexcel-eip76"; 374 reg = <0x0 0x4e10000 0x0 0x7d>; 375 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&k3_clks 264 1>; 377 }; 378 }; 379 380 main_pmx0: pinctrl@11c000 { 381 compatible = "pinctrl-single"; 382 /* Proxy 0 addressing */ 383 reg = <0x0 0x11c000 0x0 0x2b4>; 384 #pinctrl-cells = <1>; 385 pinctrl-single,register-width = <32>; 386 pinctrl-single,function-mask = <0xffffffff>; 387 }; 388 389 serdes_wiz0: wiz@5000000 { 390 compatible = "ti,j721e-wiz-16g"; 391 #address-cells = <1>; 392 #size-cells = <1>; 393 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 394 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; 395 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 396 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 397 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 398 num-lanes = <2>; 399 #reset-cells = <1>; 400 ranges = <0x5000000 0x0 0x5000000 0x10000>; 401 402 wiz0_pll0_refclk: pll0-refclk { 403 clocks = <&k3_clks 292 11>, <&cmn_refclk>; 404 #clock-cells = <0>; 405 assigned-clocks = <&wiz0_pll0_refclk>; 406 assigned-clock-parents = <&k3_clks 292 11>; 407 }; 408 409 wiz0_pll1_refclk: pll1-refclk { 410 clocks = <&k3_clks 292 0>, <&cmn_refclk1>; 411 #clock-cells = <0>; 412 assigned-clocks = <&wiz0_pll1_refclk>; 413 assigned-clock-parents = <&k3_clks 292 0>; 414 }; 415 416 wiz0_refclk_dig: refclk-dig { 417 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; 418 #clock-cells = <0>; 419 assigned-clocks = <&wiz0_refclk_dig>; 420 assigned-clock-parents = <&k3_clks 292 11>; 421 }; 422 423 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 424 clocks = <&wiz0_refclk_dig>; 425 #clock-cells = <0>; 426 }; 427 428 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 429 clocks = <&wiz0_pll1_refclk>; 430 #clock-cells = <0>; 431 }; 432 433 serdes0: serdes@5000000 { 434 compatible = "ti,sierra-phy-t0"; 435 reg-names = "serdes"; 436 reg = <0x5000000 0x10000>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 resets = <&serdes_wiz0 0>; 440 reset-names = "sierra_reset"; 441 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; 442 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 443 }; 444 }; 445 446 serdes_wiz1: wiz@5010000 { 447 compatible = "ti,j721e-wiz-16g"; 448 #address-cells = <1>; 449 #size-cells = <1>; 450 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 451 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; 452 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 453 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 454 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 455 num-lanes = <2>; 456 #reset-cells = <1>; 457 ranges = <0x5010000 0x0 0x5010000 0x10000>; 458 459 wiz1_pll0_refclk: pll0-refclk { 460 clocks = <&k3_clks 293 13>, <&cmn_refclk>; 461 #clock-cells = <0>; 462 assigned-clocks = <&wiz1_pll0_refclk>; 463 assigned-clock-parents = <&k3_clks 293 13>; 464 }; 465 466 wiz1_pll1_refclk: pll1-refclk { 467 clocks = <&k3_clks 293 0>, <&cmn_refclk1>; 468 #clock-cells = <0>; 469 assigned-clocks = <&wiz1_pll1_refclk>; 470 assigned-clock-parents = <&k3_clks 293 0>; 471 }; 472 473 wiz1_refclk_dig: refclk-dig { 474 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; 475 #clock-cells = <0>; 476 assigned-clocks = <&wiz1_refclk_dig>; 477 assigned-clock-parents = <&k3_clks 293 13>; 478 }; 479 480 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 481 clocks = <&wiz1_refclk_dig>; 482 #clock-cells = <0>; 483 }; 484 485 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 486 clocks = <&wiz1_pll1_refclk>; 487 #clock-cells = <0>; 488 }; 489 490 serdes1: serdes@5010000 { 491 compatible = "ti,sierra-phy-t0"; 492 reg-names = "serdes"; 493 reg = <0x5010000 0x10000>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 resets = <&serdes_wiz1 0>; 497 reset-names = "sierra_reset"; 498 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; 499 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 500 }; 501 }; 502 503 serdes_wiz2: wiz@5020000 { 504 compatible = "ti,j721e-wiz-16g"; 505 #address-cells = <1>; 506 #size-cells = <1>; 507 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 508 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; 509 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 510 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 511 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 512 num-lanes = <2>; 513 #reset-cells = <1>; 514 ranges = <0x5020000 0x0 0x5020000 0x10000>; 515 516 wiz2_pll0_refclk: pll0-refclk { 517 clocks = <&k3_clks 294 11>, <&cmn_refclk>; 518 #clock-cells = <0>; 519 assigned-clocks = <&wiz2_pll0_refclk>; 520 assigned-clock-parents = <&k3_clks 294 11>; 521 }; 522 523 wiz2_pll1_refclk: pll1-refclk { 524 clocks = <&k3_clks 294 0>, <&cmn_refclk1>; 525 #clock-cells = <0>; 526 assigned-clocks = <&wiz2_pll1_refclk>; 527 assigned-clock-parents = <&k3_clks 294 0>; 528 }; 529 530 wiz2_refclk_dig: refclk-dig { 531 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; 532 #clock-cells = <0>; 533 assigned-clocks = <&wiz2_refclk_dig>; 534 assigned-clock-parents = <&k3_clks 294 11>; 535 }; 536 537 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 538 clocks = <&wiz2_refclk_dig>; 539 #clock-cells = <0>; 540 }; 541 542 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 543 clocks = <&wiz2_pll1_refclk>; 544 #clock-cells = <0>; 545 }; 546 547 serdes2: serdes@5020000 { 548 compatible = "ti,sierra-phy-t0"; 549 reg-names = "serdes"; 550 reg = <0x5020000 0x10000>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 resets = <&serdes_wiz2 0>; 554 reset-names = "sierra_reset"; 555 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; 556 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 557 }; 558 }; 559 560 serdes_wiz3: wiz@5030000 { 561 compatible = "ti,j721e-wiz-16g"; 562 #address-cells = <1>; 563 #size-cells = <1>; 564 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 565 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; 566 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 567 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 568 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 569 num-lanes = <2>; 570 #reset-cells = <1>; 571 ranges = <0x5030000 0x0 0x5030000 0x10000>; 572 573 wiz3_pll0_refclk: pll0-refclk { 574 clocks = <&k3_clks 295 9>, <&cmn_refclk>; 575 #clock-cells = <0>; 576 assigned-clocks = <&wiz3_pll0_refclk>; 577 assigned-clock-parents = <&k3_clks 295 9>; 578 }; 579 580 wiz3_pll1_refclk: pll1-refclk { 581 clocks = <&k3_clks 295 0>, <&cmn_refclk1>; 582 #clock-cells = <0>; 583 assigned-clocks = <&wiz3_pll1_refclk>; 584 assigned-clock-parents = <&k3_clks 295 0>; 585 }; 586 587 wiz3_refclk_dig: refclk-dig { 588 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; 589 #clock-cells = <0>; 590 assigned-clocks = <&wiz3_refclk_dig>; 591 assigned-clock-parents = <&k3_clks 295 9>; 592 }; 593 594 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 595 clocks = <&wiz3_refclk_dig>; 596 #clock-cells = <0>; 597 }; 598 599 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 600 clocks = <&wiz3_pll1_refclk>; 601 #clock-cells = <0>; 602 }; 603 604 serdes3: serdes@5030000 { 605 compatible = "ti,sierra-phy-t0"; 606 reg-names = "serdes"; 607 reg = <0x5030000 0x10000>; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 resets = <&serdes_wiz3 0>; 611 reset-names = "sierra_reset"; 612 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; 613 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 614 }; 615 }; 616 617 pcie0_rc: pcie@2900000 { 618 compatible = "ti,j721e-pcie-host"; 619 reg = <0x00 0x02900000 0x00 0x1000>, 620 <0x00 0x02907000 0x00 0x400>, 621 <0x00 0x0d000000 0x00 0x00800000>, 622 <0x00 0x10000000 0x00 0x00001000>; 623 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 624 interrupt-names = "link_state"; 625 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 626 device_type = "pci"; 627 ti,syscon-pcie-ctrl = <&pcie0_ctrl>; 628 max-link-speed = <3>; 629 num-lanes = <2>; 630 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 631 clocks = <&k3_clks 239 1>; 632 clock-names = "fck"; 633 #address-cells = <3>; 634 #size-cells = <2>; 635 bus-range = <0x0 0xff>; 636 vendor-id = <0x104c>; 637 device-id = <0xb00d>; 638 msi-map = <0x0 &gic_its 0x0 0x10000>; 639 dma-coherent; 640 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 641 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 642 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 643 }; 644 645 pcie0_ep: pcie-ep@2900000 { 646 compatible = "ti,j721e-pcie-ep"; 647 reg = <0x00 0x02900000 0x00 0x1000>, 648 <0x00 0x02907000 0x00 0x400>, 649 <0x00 0x0d000000 0x00 0x00800000>, 650 <0x00 0x10000000 0x00 0x08000000>; 651 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 652 interrupt-names = "link_state"; 653 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 654 ti,syscon-pcie-ctrl = <&pcie0_ctrl>; 655 max-link-speed = <3>; 656 num-lanes = <2>; 657 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 658 clocks = <&k3_clks 239 1>; 659 clock-names = "fck"; 660 cdns,max-outbound-regions = <16>; 661 max-functions = /bits/ 8 <6>; 662 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 663 dma-coherent; 664 }; 665 666 pcie1_rc: pcie@2910000 { 667 compatible = "ti,j721e-pcie-host"; 668 reg = <0x00 0x02910000 0x00 0x1000>, 669 <0x00 0x02917000 0x00 0x400>, 670 <0x00 0x0d800000 0x00 0x00800000>, 671 <0x00 0x18000000 0x00 0x00001000>; 672 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 673 interrupt-names = "link_state"; 674 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 675 device_type = "pci"; 676 ti,syscon-pcie-ctrl = <&pcie1_ctrl>; 677 max-link-speed = <3>; 678 num-lanes = <2>; 679 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 680 clocks = <&k3_clks 240 1>; 681 clock-names = "fck"; 682 #address-cells = <3>; 683 #size-cells = <2>; 684 bus-range = <0x0 0xff>; 685 vendor-id = <0x104c>; 686 device-id = <0xb00d>; 687 msi-map = <0x0 &gic_its 0x10000 0x10000>; 688 dma-coherent; 689 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, 690 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; 691 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 692 }; 693 694 pcie1_ep: pcie-ep@2910000 { 695 compatible = "ti,j721e-pcie-ep"; 696 reg = <0x00 0x02910000 0x00 0x1000>, 697 <0x00 0x02917000 0x00 0x400>, 698 <0x00 0x0d800000 0x00 0x00800000>, 699 <0x00 0x18000000 0x00 0x08000000>; 700 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 701 interrupt-names = "link_state"; 702 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 703 ti,syscon-pcie-ctrl = <&pcie1_ctrl>; 704 max-link-speed = <3>; 705 num-lanes = <2>; 706 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 707 clocks = <&k3_clks 240 1>; 708 clock-names = "fck"; 709 cdns,max-outbound-regions = <16>; 710 max-functions = /bits/ 8 <6>; 711 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 712 dma-coherent; 713 }; 714 715 pcie2_rc: pcie@2920000 { 716 compatible = "ti,j721e-pcie-host"; 717 reg = <0x00 0x02920000 0x00 0x1000>, 718 <0x00 0x02927000 0x00 0x400>, 719 <0x00 0x0e000000 0x00 0x00800000>, 720 <0x44 0x00000000 0x00 0x00001000>; 721 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 722 interrupt-names = "link_state"; 723 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 724 device_type = "pci"; 725 ti,syscon-pcie-ctrl = <&pcie2_ctrl>; 726 max-link-speed = <3>; 727 num-lanes = <2>; 728 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 729 clocks = <&k3_clks 241 1>; 730 clock-names = "fck"; 731 #address-cells = <3>; 732 #size-cells = <2>; 733 bus-range = <0x0 0xff>; 734 vendor-id = <0x104c>; 735 device-id = <0xb00d>; 736 msi-map = <0x0 &gic_its 0x20000 0x10000>; 737 dma-coherent; 738 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 739 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 740 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 741 }; 742 743 pcie2_ep: pcie-ep@2920000 { 744 compatible = "ti,j721e-pcie-ep"; 745 reg = <0x00 0x02920000 0x00 0x1000>, 746 <0x00 0x02927000 0x00 0x400>, 747 <0x00 0x0e000000 0x00 0x00800000>, 748 <0x44 0x00000000 0x00 0x08000000>; 749 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 750 interrupt-names = "link_state"; 751 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 752 ti,syscon-pcie-ctrl = <&pcie2_ctrl>; 753 max-link-speed = <3>; 754 num-lanes = <2>; 755 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 756 clocks = <&k3_clks 241 1>; 757 clock-names = "fck"; 758 cdns,max-outbound-regions = <16>; 759 max-functions = /bits/ 8 <6>; 760 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 761 dma-coherent; 762 }; 763 764 pcie3_rc: pcie@2930000 { 765 compatible = "ti,j721e-pcie-host"; 766 reg = <0x00 0x02930000 0x00 0x1000>, 767 <0x00 0x02937000 0x00 0x400>, 768 <0x00 0x0e800000 0x00 0x00800000>, 769 <0x44 0x10000000 0x00 0x00001000>; 770 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 771 interrupt-names = "link_state"; 772 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 773 device_type = "pci"; 774 ti,syscon-pcie-ctrl = <&pcie3_ctrl>; 775 max-link-speed = <3>; 776 num-lanes = <2>; 777 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 778 clocks = <&k3_clks 242 1>; 779 clock-names = "fck"; 780 #address-cells = <3>; 781 #size-cells = <2>; 782 bus-range = <0x0 0xff>; 783 vendor-id = <0x104c>; 784 device-id = <0xb00d>; 785 msi-map = <0x0 &gic_its 0x30000 0x10000>; 786 dma-coherent; 787 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 788 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 789 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 790 }; 791 792 pcie3_ep: pcie-ep@2930000 { 793 compatible = "ti,j721e-pcie-ep"; 794 reg = <0x00 0x02930000 0x00 0x1000>, 795 <0x00 0x02937000 0x00 0x400>, 796 <0x00 0x0e800000 0x00 0x00800000>, 797 <0x44 0x10000000 0x00 0x08000000>; 798 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 799 interrupt-names = "link_state"; 800 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 801 ti,syscon-pcie-ctrl = <&pcie3_ctrl>; 802 max-link-speed = <3>; 803 num-lanes = <2>; 804 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 805 clocks = <&k3_clks 242 1>; 806 clock-names = "fck"; 807 cdns,max-outbound-regions = <16>; 808 max-functions = /bits/ 8 <6>; 809 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 810 dma-coherent; 811 #address-cells = <2>; 812 #size-cells = <2>; 813 }; 814 815 main_uart0: serial@2800000 { 816 compatible = "ti,j721e-uart", "ti,am654-uart"; 817 reg = <0x00 0x02800000 0x00 0x100>; 818 reg-shift = <2>; 819 reg-io-width = <4>; 820 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 821 clock-frequency = <48000000>; 822 current-speed = <115200>; 823 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 824 clocks = <&k3_clks 146 0>; 825 clock-names = "fclk"; 826 }; 827 828 main_uart1: serial@2810000 { 829 compatible = "ti,j721e-uart", "ti,am654-uart"; 830 reg = <0x00 0x02810000 0x00 0x100>; 831 reg-shift = <2>; 832 reg-io-width = <4>; 833 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 834 clock-frequency = <48000000>; 835 current-speed = <115200>; 836 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 837 clocks = <&k3_clks 278 0>; 838 clock-names = "fclk"; 839 }; 840 841 main_uart2: serial@2820000 { 842 compatible = "ti,j721e-uart", "ti,am654-uart"; 843 reg = <0x00 0x02820000 0x00 0x100>; 844 reg-shift = <2>; 845 reg-io-width = <4>; 846 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 847 clock-frequency = <48000000>; 848 current-speed = <115200>; 849 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 850 clocks = <&k3_clks 279 0>; 851 clock-names = "fclk"; 852 }; 853 854 main_uart3: serial@2830000 { 855 compatible = "ti,j721e-uart", "ti,am654-uart"; 856 reg = <0x00 0x02830000 0x00 0x100>; 857 reg-shift = <2>; 858 reg-io-width = <4>; 859 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 860 clock-frequency = <48000000>; 861 current-speed = <115200>; 862 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 863 clocks = <&k3_clks 280 0>; 864 clock-names = "fclk"; 865 }; 866 867 main_uart4: serial@2840000 { 868 compatible = "ti,j721e-uart", "ti,am654-uart"; 869 reg = <0x00 0x02840000 0x00 0x100>; 870 reg-shift = <2>; 871 reg-io-width = <4>; 872 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 873 clock-frequency = <48000000>; 874 current-speed = <115200>; 875 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 876 clocks = <&k3_clks 281 0>; 877 clock-names = "fclk"; 878 }; 879 880 main_uart5: serial@2850000 { 881 compatible = "ti,j721e-uart", "ti,am654-uart"; 882 reg = <0x00 0x02850000 0x00 0x100>; 883 reg-shift = <2>; 884 reg-io-width = <4>; 885 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 886 clock-frequency = <48000000>; 887 current-speed = <115200>; 888 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 889 clocks = <&k3_clks 282 0>; 890 clock-names = "fclk"; 891 }; 892 893 main_uart6: serial@2860000 { 894 compatible = "ti,j721e-uart", "ti,am654-uart"; 895 reg = <0x00 0x02860000 0x00 0x100>; 896 reg-shift = <2>; 897 reg-io-width = <4>; 898 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 899 clock-frequency = <48000000>; 900 current-speed = <115200>; 901 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 902 clocks = <&k3_clks 283 0>; 903 clock-names = "fclk"; 904 }; 905 906 main_uart7: serial@2870000 { 907 compatible = "ti,j721e-uart", "ti,am654-uart"; 908 reg = <0x00 0x02870000 0x00 0x100>; 909 reg-shift = <2>; 910 reg-io-width = <4>; 911 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 912 clock-frequency = <48000000>; 913 current-speed = <115200>; 914 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 915 clocks = <&k3_clks 284 0>; 916 clock-names = "fclk"; 917 }; 918 919 main_uart8: serial@2880000 { 920 compatible = "ti,j721e-uart", "ti,am654-uart"; 921 reg = <0x00 0x02880000 0x00 0x100>; 922 reg-shift = <2>; 923 reg-io-width = <4>; 924 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 925 clock-frequency = <48000000>; 926 current-speed = <115200>; 927 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 928 clocks = <&k3_clks 285 0>; 929 clock-names = "fclk"; 930 }; 931 932 main_uart9: serial@2890000 { 933 compatible = "ti,j721e-uart", "ti,am654-uart"; 934 reg = <0x00 0x02890000 0x00 0x100>; 935 reg-shift = <2>; 936 reg-io-width = <4>; 937 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 938 clock-frequency = <48000000>; 939 current-speed = <115200>; 940 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 941 clocks = <&k3_clks 286 0>; 942 clock-names = "fclk"; 943 }; 944 945 main_gpio0: gpio@600000 { 946 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 947 reg = <0x0 0x00600000 0x0 0x100>; 948 gpio-controller; 949 #gpio-cells = <2>; 950 interrupt-parent = <&main_gpio_intr>; 951 interrupts = <256>, <257>, <258>, <259>, 952 <260>, <261>, <262>, <263>; 953 interrupt-controller; 954 #interrupt-cells = <2>; 955 ti,ngpio = <128>; 956 ti,davinci-gpio-unbanked = <0>; 957 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 958 clocks = <&k3_clks 105 0>; 959 clock-names = "gpio"; 960 }; 961 962 main_gpio1: gpio@601000 { 963 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 964 reg = <0x0 0x00601000 0x0 0x100>; 965 gpio-controller; 966 #gpio-cells = <2>; 967 interrupt-parent = <&main_gpio_intr>; 968 interrupts = <288>, <289>, <290>; 969 interrupt-controller; 970 #interrupt-cells = <2>; 971 ti,ngpio = <36>; 972 ti,davinci-gpio-unbanked = <0>; 973 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 974 clocks = <&k3_clks 106 0>; 975 clock-names = "gpio"; 976 }; 977 978 main_gpio2: gpio@610000 { 979 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 980 reg = <0x0 0x00610000 0x0 0x100>; 981 gpio-controller; 982 #gpio-cells = <2>; 983 interrupt-parent = <&main_gpio_intr>; 984 interrupts = <264>, <265>, <266>, <267>, 985 <268>, <269>, <270>, <271>; 986 interrupt-controller; 987 #interrupt-cells = <2>; 988 ti,ngpio = <128>; 989 ti,davinci-gpio-unbanked = <0>; 990 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 991 clocks = <&k3_clks 107 0>; 992 clock-names = "gpio"; 993 }; 994 995 main_gpio3: gpio@611000 { 996 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 997 reg = <0x0 0x00611000 0x0 0x100>; 998 gpio-controller; 999 #gpio-cells = <2>; 1000 interrupt-parent = <&main_gpio_intr>; 1001 interrupts = <292>, <293>, <294>; 1002 interrupt-controller; 1003 #interrupt-cells = <2>; 1004 ti,ngpio = <36>; 1005 ti,davinci-gpio-unbanked = <0>; 1006 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 1007 clocks = <&k3_clks 108 0>; 1008 clock-names = "gpio"; 1009 }; 1010 1011 main_gpio4: gpio@620000 { 1012 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1013 reg = <0x0 0x00620000 0x0 0x100>; 1014 gpio-controller; 1015 #gpio-cells = <2>; 1016 interrupt-parent = <&main_gpio_intr>; 1017 interrupts = <272>, <273>, <274>, <275>, 1018 <276>, <277>, <278>, <279>; 1019 interrupt-controller; 1020 #interrupt-cells = <2>; 1021 ti,ngpio = <128>; 1022 ti,davinci-gpio-unbanked = <0>; 1023 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 1024 clocks = <&k3_clks 109 0>; 1025 clock-names = "gpio"; 1026 }; 1027 1028 main_gpio5: gpio@621000 { 1029 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1030 reg = <0x0 0x00621000 0x0 0x100>; 1031 gpio-controller; 1032 #gpio-cells = <2>; 1033 interrupt-parent = <&main_gpio_intr>; 1034 interrupts = <296>, <297>, <298>; 1035 interrupt-controller; 1036 #interrupt-cells = <2>; 1037 ti,ngpio = <36>; 1038 ti,davinci-gpio-unbanked = <0>; 1039 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 1040 clocks = <&k3_clks 110 0>; 1041 clock-names = "gpio"; 1042 }; 1043 1044 main_gpio6: gpio@630000 { 1045 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1046 reg = <0x0 0x00630000 0x0 0x100>; 1047 gpio-controller; 1048 #gpio-cells = <2>; 1049 interrupt-parent = <&main_gpio_intr>; 1050 interrupts = <280>, <281>, <282>, <283>, 1051 <284>, <285>, <286>, <287>; 1052 interrupt-controller; 1053 #interrupt-cells = <2>; 1054 ti,ngpio = <128>; 1055 ti,davinci-gpio-unbanked = <0>; 1056 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1057 clocks = <&k3_clks 111 0>; 1058 clock-names = "gpio"; 1059 }; 1060 1061 main_gpio7: gpio@631000 { 1062 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1063 reg = <0x0 0x00631000 0x0 0x100>; 1064 gpio-controller; 1065 #gpio-cells = <2>; 1066 interrupt-parent = <&main_gpio_intr>; 1067 interrupts = <300>, <301>, <302>; 1068 interrupt-controller; 1069 #interrupt-cells = <2>; 1070 ti,ngpio = <36>; 1071 ti,davinci-gpio-unbanked = <0>; 1072 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1073 clocks = <&k3_clks 112 0>; 1074 clock-names = "gpio"; 1075 }; 1076 1077 main_sdhci0: sdhci@4f80000 { 1078 compatible = "ti,j721e-sdhci-8bit"; 1079 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1080 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1081 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1082 clock-names = "clk_xin", "clk_ahb"; 1083 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; 1084 assigned-clocks = <&k3_clks 91 1>; 1085 assigned-clock-parents = <&k3_clks 91 2>; 1086 bus-width = <8>; 1087 mmc-hs400-1_8v; 1088 mmc-ddr-1_8v; 1089 ti,otap-del-sel = <0x2>; 1090 ti,trm-icp = <0x8>; 1091 ti,strobe-sel = <0x77>; 1092 dma-coherent; 1093 }; 1094 1095 main_sdhci1: sdhci@4fb0000 { 1096 compatible = "ti,j721e-sdhci-4bit"; 1097 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1098 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1099 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1100 clock-names = "clk_xin", "clk_ahb"; 1101 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; 1102 assigned-clocks = <&k3_clks 92 0>; 1103 assigned-clock-parents = <&k3_clks 92 1>; 1104 ti,otap-del-sel = <0x2>; 1105 ti,trm-icp = <0x8>; 1106 ti,clkbuf-sel = <0x7>; 1107 dma-coherent; 1108 no-1-8-v; 1109 }; 1110 1111 main_sdhci2: sdhci@4f98000 { 1112 compatible = "ti,j721e-sdhci-4bit"; 1113 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1114 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1115 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1116 clock-names = "clk_xin", "clk_ahb"; 1117 clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; 1118 assigned-clocks = <&k3_clks 93 0>; 1119 assigned-clock-parents = <&k3_clks 93 1>; 1120 ti,otap-del-sel = <0x2>; 1121 ti,trm-icp = <0x8>; 1122 ti,clkbuf-sel = <0x7>; 1123 dma-coherent; 1124 no-1-8-v; 1125 }; 1126 1127 usbss0: cdns-usb@4104000 { 1128 compatible = "ti,j721e-usb"; 1129 reg = <0x00 0x4104000 0x00 0x100>; 1130 dma-coherent; 1131 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1132 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1133 clock-names = "ref", "lpm"; 1134 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1135 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1136 #address-cells = <2>; 1137 #size-cells = <2>; 1138 ranges; 1139 1140 usb0: usb@6000000 { 1141 compatible = "cdns,usb3"; 1142 reg = <0x00 0x6000000 0x00 0x10000>, 1143 <0x00 0x6010000 0x00 0x10000>, 1144 <0x00 0x6020000 0x00 0x10000>; 1145 reg-names = "otg", "xhci", "dev"; 1146 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1147 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1148 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1149 interrupt-names = "host", 1150 "peripheral", 1151 "otg"; 1152 maximum-speed = "super-speed"; 1153 dr_mode = "otg"; 1154 }; 1155 }; 1156 1157 usbss1: cdns-usb@4114000 { 1158 compatible = "ti,j721e-usb"; 1159 reg = <0x00 0x4114000 0x00 0x100>; 1160 dma-coherent; 1161 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1162 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1163 clock-names = "ref", "lpm"; 1164 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1165 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1166 #address-cells = <2>; 1167 #size-cells = <2>; 1168 ranges; 1169 1170 usb1: usb@6400000 { 1171 compatible = "cdns,usb3"; 1172 reg = <0x00 0x6400000 0x00 0x10000>, 1173 <0x00 0x6410000 0x00 0x10000>, 1174 <0x00 0x6420000 0x00 0x10000>; 1175 reg-names = "otg", "xhci", "dev"; 1176 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1177 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1178 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1179 interrupt-names = "host", 1180 "peripheral", 1181 "otg"; 1182 maximum-speed = "super-speed"; 1183 dr_mode = "otg"; 1184 }; 1185 }; 1186 1187 main_i2c0: i2c@2000000 { 1188 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1189 reg = <0x0 0x2000000 0x0 0x100>; 1190 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 clock-names = "fck"; 1194 clocks = <&k3_clks 187 0>; 1195 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1196 }; 1197 1198 main_i2c1: i2c@2010000 { 1199 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1200 reg = <0x0 0x2010000 0x0 0x100>; 1201 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 clock-names = "fck"; 1205 clocks = <&k3_clks 188 0>; 1206 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1207 }; 1208 1209 main_i2c2: i2c@2020000 { 1210 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1211 reg = <0x0 0x2020000 0x0 0x100>; 1212 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 clock-names = "fck"; 1216 clocks = <&k3_clks 189 0>; 1217 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1218 }; 1219 1220 main_i2c3: i2c@2030000 { 1221 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1222 reg = <0x0 0x2030000 0x0 0x100>; 1223 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 clock-names = "fck"; 1227 clocks = <&k3_clks 190 0>; 1228 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1229 }; 1230 1231 main_i2c4: i2c@2040000 { 1232 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1233 reg = <0x0 0x2040000 0x0 0x100>; 1234 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 clock-names = "fck"; 1238 clocks = <&k3_clks 191 0>; 1239 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1240 }; 1241 1242 main_i2c5: i2c@2050000 { 1243 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1244 reg = <0x0 0x2050000 0x0 0x100>; 1245 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 clock-names = "fck"; 1249 clocks = <&k3_clks 192 0>; 1250 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1251 }; 1252 1253 main_i2c6: i2c@2060000 { 1254 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1255 reg = <0x0 0x2060000 0x0 0x100>; 1256 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 clock-names = "fck"; 1260 clocks = <&k3_clks 193 0>; 1261 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1262 }; 1263 1264 ufs_wrapper: ufs-wrapper@4e80000 { 1265 compatible = "ti,j721e-ufs"; 1266 reg = <0x0 0x4e80000 0x0 0x100>; 1267 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1268 clocks = <&k3_clks 277 1>; 1269 assigned-clocks = <&k3_clks 277 1>; 1270 assigned-clock-parents = <&k3_clks 277 4>; 1271 ranges; 1272 #address-cells = <2>; 1273 #size-cells = <2>; 1274 1275 ufs@4e84000 { 1276 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1277 reg = <0x0 0x4e84000 0x0 0x10000>; 1278 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1279 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1280 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1281 clock-names = "core_clk", "phy_clk", "ref_clk"; 1282 dma-coherent; 1283 }; 1284 }; 1285 1286 dss: dss@4a00000 { 1287 compatible = "ti,j721e-dss"; 1288 reg = 1289 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1290 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1291 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1292 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1293 1294 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1295 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1296 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1297 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1298 1299 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1300 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1301 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1302 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1303 1304 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1305 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1306 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1307 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1308 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1309 1310 reg-names = "common_m", "common_s0", 1311 "common_s1", "common_s2", 1312 "vidl1", "vidl2","vid1","vid2", 1313 "ovr1", "ovr2", "ovr3", "ovr4", 1314 "vp1", "vp2", "vp3", "vp4", 1315 "wb"; 1316 1317 clocks = <&k3_clks 152 0>, 1318 <&k3_clks 152 1>, 1319 <&k3_clks 152 4>, 1320 <&k3_clks 152 9>, 1321 <&k3_clks 152 13>; 1322 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1323 1324 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1325 1326 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1327 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1329 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1330 interrupt-names = "common_m", 1331 "common_s0", 1332 "common_s1", 1333 "common_s2"; 1334 1335 status = "disabled"; 1336 1337 dss_ports: ports { 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 }; 1341 }; 1342 1343 mcasp0: mcasp@2b00000 { 1344 compatible = "ti,am33xx-mcasp-audio"; 1345 reg = <0x0 0x02b00000 0x0 0x2000>, 1346 <0x0 0x02b08000 0x0 0x1000>; 1347 reg-names = "mpu","dat"; 1348 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1350 interrupt-names = "tx", "rx"; 1351 1352 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1353 dma-names = "tx", "rx"; 1354 1355 clocks = <&k3_clks 174 1>; 1356 clock-names = "fck"; 1357 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1358 1359 status = "disabled"; 1360 }; 1361 1362 mcasp1: mcasp@2b10000 { 1363 compatible = "ti,am33xx-mcasp-audio"; 1364 reg = <0x0 0x02b10000 0x0 0x2000>, 1365 <0x0 0x02b18000 0x0 0x1000>; 1366 reg-names = "mpu","dat"; 1367 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1369 interrupt-names = "tx", "rx"; 1370 1371 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1372 dma-names = "tx", "rx"; 1373 1374 clocks = <&k3_clks 175 1>; 1375 clock-names = "fck"; 1376 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1377 1378 status = "disabled"; 1379 }; 1380 1381 mcasp2: mcasp@2b20000 { 1382 compatible = "ti,am33xx-mcasp-audio"; 1383 reg = <0x0 0x02b20000 0x0 0x2000>, 1384 <0x0 0x02b28000 0x0 0x1000>; 1385 reg-names = "mpu","dat"; 1386 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1388 interrupt-names = "tx", "rx"; 1389 1390 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1391 dma-names = "tx", "rx"; 1392 1393 clocks = <&k3_clks 176 1>; 1394 clock-names = "fck"; 1395 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1396 1397 status = "disabled"; 1398 }; 1399 1400 mcasp3: mcasp@2b30000 { 1401 compatible = "ti,am33xx-mcasp-audio"; 1402 reg = <0x0 0x02b30000 0x0 0x2000>, 1403 <0x0 0x02b38000 0x0 0x1000>; 1404 reg-names = "mpu","dat"; 1405 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1407 interrupt-names = "tx", "rx"; 1408 1409 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1410 dma-names = "tx", "rx"; 1411 1412 clocks = <&k3_clks 177 1>; 1413 clock-names = "fck"; 1414 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1415 1416 status = "disabled"; 1417 }; 1418 1419 mcasp4: mcasp@2b40000 { 1420 compatible = "ti,am33xx-mcasp-audio"; 1421 reg = <0x0 0x02b40000 0x0 0x2000>, 1422 <0x0 0x02b48000 0x0 0x1000>; 1423 reg-names = "mpu","dat"; 1424 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1426 interrupt-names = "tx", "rx"; 1427 1428 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1429 dma-names = "tx", "rx"; 1430 1431 clocks = <&k3_clks 178 1>; 1432 clock-names = "fck"; 1433 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1434 1435 status = "disabled"; 1436 }; 1437 1438 mcasp5: mcasp@2b50000 { 1439 compatible = "ti,am33xx-mcasp-audio"; 1440 reg = <0x0 0x02b50000 0x0 0x2000>, 1441 <0x0 0x02b58000 0x0 0x1000>; 1442 reg-names = "mpu","dat"; 1443 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1445 interrupt-names = "tx", "rx"; 1446 1447 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1448 dma-names = "tx", "rx"; 1449 1450 clocks = <&k3_clks 179 1>; 1451 clock-names = "fck"; 1452 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1453 1454 status = "disabled"; 1455 }; 1456 1457 mcasp6: mcasp@2b60000 { 1458 compatible = "ti,am33xx-mcasp-audio"; 1459 reg = <0x0 0x02b60000 0x0 0x2000>, 1460 <0x0 0x02b68000 0x0 0x1000>; 1461 reg-names = "mpu","dat"; 1462 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1464 interrupt-names = "tx", "rx"; 1465 1466 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1467 dma-names = "tx", "rx"; 1468 1469 clocks = <&k3_clks 180 1>; 1470 clock-names = "fck"; 1471 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1472 1473 status = "disabled"; 1474 }; 1475 1476 mcasp7: mcasp@2b70000 { 1477 compatible = "ti,am33xx-mcasp-audio"; 1478 reg = <0x0 0x02b70000 0x0 0x2000>, 1479 <0x0 0x02b78000 0x0 0x1000>; 1480 reg-names = "mpu","dat"; 1481 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1483 interrupt-names = "tx", "rx"; 1484 1485 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1486 dma-names = "tx", "rx"; 1487 1488 clocks = <&k3_clks 181 1>; 1489 clock-names = "fck"; 1490 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1491 1492 status = "disabled"; 1493 }; 1494 1495 mcasp8: mcasp@2b80000 { 1496 compatible = "ti,am33xx-mcasp-audio"; 1497 reg = <0x0 0x02b80000 0x0 0x2000>, 1498 <0x0 0x02b88000 0x0 0x1000>; 1499 reg-names = "mpu","dat"; 1500 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1502 interrupt-names = "tx", "rx"; 1503 1504 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1505 dma-names = "tx", "rx"; 1506 1507 clocks = <&k3_clks 182 1>; 1508 clock-names = "fck"; 1509 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1510 1511 status = "disabled"; 1512 }; 1513 1514 mcasp9: mcasp@2b90000 { 1515 compatible = "ti,am33xx-mcasp-audio"; 1516 reg = <0x0 0x02b90000 0x0 0x2000>, 1517 <0x0 0x02b98000 0x0 0x1000>; 1518 reg-names = "mpu","dat"; 1519 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1521 interrupt-names = "tx", "rx"; 1522 1523 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1524 dma-names = "tx", "rx"; 1525 1526 clocks = <&k3_clks 183 1>; 1527 clock-names = "fck"; 1528 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1529 1530 status = "disabled"; 1531 }; 1532 1533 mcasp10: mcasp@2ba0000 { 1534 compatible = "ti,am33xx-mcasp-audio"; 1535 reg = <0x0 0x02ba0000 0x0 0x2000>, 1536 <0x0 0x02ba8000 0x0 0x1000>; 1537 reg-names = "mpu","dat"; 1538 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1540 interrupt-names = "tx", "rx"; 1541 1542 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1543 dma-names = "tx", "rx"; 1544 1545 clocks = <&k3_clks 184 1>; 1546 clock-names = "fck"; 1547 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1548 1549 status = "disabled"; 1550 }; 1551 1552 mcasp11: mcasp@2bb0000 { 1553 compatible = "ti,am33xx-mcasp-audio"; 1554 reg = <0x0 0x02bb0000 0x0 0x2000>, 1555 <0x0 0x02bb8000 0x0 0x1000>; 1556 reg-names = "mpu","dat"; 1557 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1559 interrupt-names = "tx", "rx"; 1560 1561 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1562 dma-names = "tx", "rx"; 1563 1564 clocks = <&k3_clks 185 1>; 1565 clock-names = "fck"; 1566 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1567 1568 status = "disabled"; 1569 }; 1570 1571 watchdog0: watchdog@2200000 { 1572 compatible = "ti,j7-rti-wdt"; 1573 reg = <0x0 0x2200000 0x0 0x100>; 1574 clocks = <&k3_clks 252 1>; 1575 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1576 assigned-clocks = <&k3_clks 252 1>; 1577 assigned-clock-parents = <&k3_clks 252 5>; 1578 }; 1579 1580 watchdog1: watchdog@2210000 { 1581 compatible = "ti,j7-rti-wdt"; 1582 reg = <0x0 0x2210000 0x0 0x100>; 1583 clocks = <&k3_clks 253 1>; 1584 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1585 assigned-clocks = <&k3_clks 253 1>; 1586 assigned-clock-parents = <&k3_clks 253 5>; 1587 }; 1588 1589 c66_0: dsp@4d80800000 { 1590 compatible = "ti,j721e-c66-dsp"; 1591 reg = <0x4d 0x80800000 0x00 0x00048000>, 1592 <0x4d 0x80e00000 0x00 0x00008000>, 1593 <0x4d 0x80f00000 0x00 0x00008000>; 1594 reg-names = "l2sram", "l1pram", "l1dram"; 1595 ti,sci = <&dmsc>; 1596 ti,sci-dev-id = <142>; 1597 ti,sci-proc-ids = <0x03 0xff>; 1598 resets = <&k3_reset 142 1>; 1599 firmware-name = "j7-c66_0-fw"; 1600 }; 1601 1602 c66_1: dsp@4d81800000 { 1603 compatible = "ti,j721e-c66-dsp"; 1604 reg = <0x4d 0x81800000 0x00 0x00048000>, 1605 <0x4d 0x81e00000 0x00 0x00008000>, 1606 <0x4d 0x81f00000 0x00 0x00008000>; 1607 reg-names = "l2sram", "l1pram", "l1dram"; 1608 ti,sci = <&dmsc>; 1609 ti,sci-dev-id = <143>; 1610 ti,sci-proc-ids = <0x04 0xff>; 1611 resets = <&k3_reset 143 1>; 1612 firmware-name = "j7-c66_1-fw"; 1613 }; 1614 1615 c71_0: dsp@64800000 { 1616 compatible = "ti,j721e-c71-dsp"; 1617 reg = <0x00 0x64800000 0x00 0x00080000>, 1618 <0x00 0x64e00000 0x00 0x0000c000>; 1619 reg-names = "l2sram", "l1dram"; 1620 ti,sci = <&dmsc>; 1621 ti,sci-dev-id = <15>; 1622 ti,sci-proc-ids = <0x30 0xff>; 1623 resets = <&k3_reset 15 1>; 1624 firmware-name = "j7-c71_0-fw"; 1625 }; 1626}; 1627