1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ARM64_KVM_HYP_SWITCH_H__
8 #define __ARM64_KVM_HYP_SWITCH_H__
9
10 #include <hyp/adjust_pc.h>
11
12 #include <linux/arm-smccc.h>
13 #include <linux/kvm_host.h>
14 #include <linux/types.h>
15 #include <linux/jump_label.h>
16 #include <uapi/linux/psci.h>
17
18 #include <kvm/arm_psci.h>
19
20 #include <asm/barrier.h>
21 #include <asm/cpufeature.h>
22 #include <asm/extable.h>
23 #include <asm/kprobes.h>
24 #include <asm/kvm_asm.h>
25 #include <asm/kvm_emulate.h>
26 #include <asm/kvm_hyp.h>
27 #include <asm/kvm_mmu.h>
28 #include <asm/fpsimd.h>
29 #include <asm/debug-monitors.h>
30 #include <asm/processor.h>
31 #include <asm/thread_info.h>
32
33 extern const char __hyp_panic_string[];
34
35 extern struct exception_table_entry __start___kvm_ex_table;
36 extern struct exception_table_entry __stop___kvm_ex_table;
37
38 /* Check whether the FP regs were dirtied while in the host-side run loop: */
update_fp_enabled(struct kvm_vcpu * vcpu)39 static inline bool update_fp_enabled(struct kvm_vcpu *vcpu)
40 {
41 /*
42 * When the system doesn't support FP/SIMD, we cannot rely on
43 * the _TIF_FOREIGN_FPSTATE flag. However, we always inject an
44 * abort on the very first access to FP and thus we should never
45 * see KVM_ARM64_FP_ENABLED. For added safety, make sure we always
46 * trap the accesses.
47 */
48 if (!system_supports_fpsimd() ||
49 vcpu->arch.host_thread_info->flags & _TIF_FOREIGN_FPSTATE)
50 vcpu->arch.flags &= ~(KVM_ARM64_FP_ENABLED |
51 KVM_ARM64_FP_HOST);
52
53 return !!(vcpu->arch.flags & KVM_ARM64_FP_ENABLED);
54 }
55
56 /* Save the 32-bit only FPSIMD system register state */
__fpsimd_save_fpexc32(struct kvm_vcpu * vcpu)57 static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
58 {
59 if (!vcpu_el1_is_32bit(vcpu))
60 return;
61
62 __vcpu_sys_reg(vcpu, FPEXC32_EL2) = read_sysreg(fpexc32_el2);
63 }
64
__activate_traps_fpsimd32(struct kvm_vcpu * vcpu)65 static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
66 {
67 /*
68 * We are about to set CPTR_EL2.TFP to trap all floating point
69 * register accesses to EL2, however, the ARM ARM clearly states that
70 * traps are only taken to EL2 if the operation would not otherwise
71 * trap to EL1. Therefore, always make sure that for 32-bit guests,
72 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
73 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
74 * it will cause an exception.
75 */
76 if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
77 write_sysreg(1 << 30, fpexc32_el2);
78 isb();
79 }
80 }
81
__activate_traps_common(struct kvm_vcpu * vcpu)82 static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
83 {
84 /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
85 write_sysreg(1 << 15, hstr_el2);
86
87 /*
88 * Make sure we trap PMU access from EL0 to EL2. Also sanitize
89 * PMSELR_EL0 to make sure it never contains the cycle
90 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
91 * EL1 instead of being trapped to EL2.
92 */
93 if (kvm_arm_support_pmu_v3()) {
94 write_sysreg(0, pmselr_el0);
95 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
96 }
97 write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
98 }
99
__deactivate_traps_common(void)100 static inline void __deactivate_traps_common(void)
101 {
102 write_sysreg(0, hstr_el2);
103 if (kvm_arm_support_pmu_v3())
104 write_sysreg(0, pmuserenr_el0);
105 }
106
___activate_traps(struct kvm_vcpu * vcpu)107 static inline void ___activate_traps(struct kvm_vcpu *vcpu)
108 {
109 u64 hcr = vcpu->arch.hcr_el2;
110
111 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
112 hcr |= HCR_TVM;
113
114 write_sysreg(hcr, hcr_el2);
115
116 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
117 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
118 }
119
___deactivate_traps(struct kvm_vcpu * vcpu)120 static inline void ___deactivate_traps(struct kvm_vcpu *vcpu)
121 {
122 /*
123 * If we pended a virtual abort, preserve it until it gets
124 * cleared. See D1.14.3 (Virtual Interrupts) for details, but
125 * the crucial bit is "On taking a vSError interrupt,
126 * HCR_EL2.VSE is cleared to 0."
127 */
128 if (vcpu->arch.hcr_el2 & HCR_VSE) {
129 vcpu->arch.hcr_el2 &= ~HCR_VSE;
130 vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE;
131 }
132 }
133
__translate_far_to_hpfar(u64 far,u64 * hpfar)134 static inline bool __translate_far_to_hpfar(u64 far, u64 *hpfar)
135 {
136 u64 par, tmp;
137
138 /*
139 * Resolve the IPA the hard way using the guest VA.
140 *
141 * Stage-1 translation already validated the memory access
142 * rights. As such, we can use the EL1 translation regime, and
143 * don't have to distinguish between EL0 and EL1 access.
144 *
145 * We do need to save/restore PAR_EL1 though, as we haven't
146 * saved the guest context yet, and we may return early...
147 */
148 par = read_sysreg_par();
149 if (!__kvm_at("s1e1r", far))
150 tmp = read_sysreg_par();
151 else
152 tmp = SYS_PAR_EL1_F; /* back to the guest */
153 write_sysreg(par, par_el1);
154
155 if (unlikely(tmp & SYS_PAR_EL1_F))
156 return false; /* Translation failed, back to guest */
157
158 /* Convert PAR to HPFAR format */
159 *hpfar = PAR_TO_HPFAR(tmp);
160 return true;
161 }
162
__get_fault_info(u64 esr,struct kvm_vcpu_fault_info * fault)163 static inline bool __get_fault_info(u64 esr, struct kvm_vcpu_fault_info *fault)
164 {
165 u64 hpfar, far;
166
167 far = read_sysreg_el2(SYS_FAR);
168
169 /*
170 * The HPFAR can be invalid if the stage 2 fault did not
171 * happen during a stage 1 page table walk (the ESR_EL2.S1PTW
172 * bit is clear) and one of the two following cases are true:
173 * 1. The fault was due to a permission fault
174 * 2. The processor carries errata 834220
175 *
176 * Therefore, for all non S1PTW faults where we either have a
177 * permission fault or the errata workaround is enabled, we
178 * resolve the IPA using the AT instruction.
179 */
180 if (!(esr & ESR_ELx_S1PTW) &&
181 (cpus_have_final_cap(ARM64_WORKAROUND_834220) ||
182 (esr & ESR_ELx_FSC_TYPE) == FSC_PERM)) {
183 if (!__translate_far_to_hpfar(far, &hpfar))
184 return false;
185 } else {
186 hpfar = read_sysreg(hpfar_el2);
187 }
188
189 fault->far_el2 = far;
190 fault->hpfar_el2 = hpfar;
191 return true;
192 }
193
__populate_fault_info(struct kvm_vcpu * vcpu)194 static inline bool __populate_fault_info(struct kvm_vcpu *vcpu)
195 {
196 u8 ec;
197 u64 esr;
198
199 esr = vcpu->arch.fault.esr_el2;
200 ec = ESR_ELx_EC(esr);
201
202 if (ec != ESR_ELx_EC_DABT_LOW && ec != ESR_ELx_EC_IABT_LOW)
203 return true;
204
205 return __get_fault_info(esr, &vcpu->arch.fault);
206 }
207
__hyp_sve_save_host(struct kvm_vcpu * vcpu)208 static inline void __hyp_sve_save_host(struct kvm_vcpu *vcpu)
209 {
210 struct thread_struct *thread;
211
212 thread = container_of(vcpu->arch.host_fpsimd_state, struct thread_struct,
213 uw.fpsimd_state);
214
215 __sve_save_state(sve_pffr(thread), &vcpu->arch.host_fpsimd_state->fpsr);
216 }
217
__hyp_sve_restore_guest(struct kvm_vcpu * vcpu)218 static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu)
219 {
220 sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2);
221 __sve_restore_state(vcpu_sve_pffr(vcpu),
222 &vcpu->arch.ctxt.fp_regs.fpsr);
223 write_sysreg_el1(__vcpu_sys_reg(vcpu, ZCR_EL1), SYS_ZCR);
224 }
225
226 /* Check for an FPSIMD/SVE trap and handle as appropriate */
__hyp_handle_fpsimd(struct kvm_vcpu * vcpu)227 static inline bool __hyp_handle_fpsimd(struct kvm_vcpu *vcpu)
228 {
229 bool sve_guest, sve_host;
230 u8 esr_ec;
231 u64 reg;
232
233 if (!system_supports_fpsimd())
234 return false;
235
236 if (system_supports_sve()) {
237 sve_guest = vcpu_has_sve(vcpu);
238 sve_host = vcpu->arch.flags & KVM_ARM64_HOST_SVE_IN_USE;
239 } else {
240 sve_guest = false;
241 sve_host = false;
242 }
243
244 esr_ec = kvm_vcpu_trap_get_class(vcpu);
245 if (esr_ec != ESR_ELx_EC_FP_ASIMD &&
246 esr_ec != ESR_ELx_EC_SVE)
247 return false;
248
249 /* Don't handle SVE traps for non-SVE vcpus here: */
250 if (!sve_guest && esr_ec != ESR_ELx_EC_FP_ASIMD)
251 return false;
252
253 /* Valid trap. Switch the context: */
254 if (has_vhe()) {
255 reg = CPACR_EL1_FPEN;
256 if (sve_guest)
257 reg |= CPACR_EL1_ZEN;
258
259 sysreg_clear_set(cpacr_el1, 0, reg);
260 } else {
261 reg = CPTR_EL2_TFP;
262 if (sve_guest)
263 reg |= CPTR_EL2_TZ;
264
265 sysreg_clear_set(cptr_el2, reg, 0);
266 }
267 isb();
268
269 if (vcpu->arch.flags & KVM_ARM64_FP_HOST) {
270 if (sve_host)
271 __hyp_sve_save_host(vcpu);
272 else
273 __fpsimd_save_state(vcpu->arch.host_fpsimd_state);
274
275 vcpu->arch.flags &= ~KVM_ARM64_FP_HOST;
276 }
277
278 if (sve_guest)
279 __hyp_sve_restore_guest(vcpu);
280 else
281 __fpsimd_restore_state(&vcpu->arch.ctxt.fp_regs);
282
283 /* Skip restoring fpexc32 for AArch64 guests */
284 if (!(read_sysreg(hcr_el2) & HCR_RW))
285 write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2);
286
287 vcpu->arch.flags |= KVM_ARM64_FP_ENABLED;
288
289 return true;
290 }
291
handle_tx2_tvm(struct kvm_vcpu * vcpu)292 static inline bool handle_tx2_tvm(struct kvm_vcpu *vcpu)
293 {
294 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
295 int rt = kvm_vcpu_sys_get_rt(vcpu);
296 u64 val = vcpu_get_reg(vcpu, rt);
297
298 /*
299 * The normal sysreg handling code expects to see the traps,
300 * let's not do anything here.
301 */
302 if (vcpu->arch.hcr_el2 & HCR_TVM)
303 return false;
304
305 switch (sysreg) {
306 case SYS_SCTLR_EL1:
307 write_sysreg_el1(val, SYS_SCTLR);
308 break;
309 case SYS_TTBR0_EL1:
310 write_sysreg_el1(val, SYS_TTBR0);
311 break;
312 case SYS_TTBR1_EL1:
313 write_sysreg_el1(val, SYS_TTBR1);
314 break;
315 case SYS_TCR_EL1:
316 write_sysreg_el1(val, SYS_TCR);
317 break;
318 case SYS_ESR_EL1:
319 write_sysreg_el1(val, SYS_ESR);
320 break;
321 case SYS_FAR_EL1:
322 write_sysreg_el1(val, SYS_FAR);
323 break;
324 case SYS_AFSR0_EL1:
325 write_sysreg_el1(val, SYS_AFSR0);
326 break;
327 case SYS_AFSR1_EL1:
328 write_sysreg_el1(val, SYS_AFSR1);
329 break;
330 case SYS_MAIR_EL1:
331 write_sysreg_el1(val, SYS_MAIR);
332 break;
333 case SYS_AMAIR_EL1:
334 write_sysreg_el1(val, SYS_AMAIR);
335 break;
336 case SYS_CONTEXTIDR_EL1:
337 write_sysreg_el1(val, SYS_CONTEXTIDR);
338 break;
339 default:
340 return false;
341 }
342
343 __kvm_skip_instr(vcpu);
344 return true;
345 }
346
esr_is_ptrauth_trap(u32 esr)347 static inline bool esr_is_ptrauth_trap(u32 esr)
348 {
349 u32 ec = ESR_ELx_EC(esr);
350
351 if (ec == ESR_ELx_EC_PAC)
352 return true;
353
354 if (ec != ESR_ELx_EC_SYS64)
355 return false;
356
357 switch (esr_sys64_to_sysreg(esr)) {
358 case SYS_APIAKEYLO_EL1:
359 case SYS_APIAKEYHI_EL1:
360 case SYS_APIBKEYLO_EL1:
361 case SYS_APIBKEYHI_EL1:
362 case SYS_APDAKEYLO_EL1:
363 case SYS_APDAKEYHI_EL1:
364 case SYS_APDBKEYLO_EL1:
365 case SYS_APDBKEYHI_EL1:
366 case SYS_APGAKEYLO_EL1:
367 case SYS_APGAKEYHI_EL1:
368 return true;
369 }
370
371 return false;
372 }
373
374 #define __ptrauth_save_key(ctxt, key) \
375 do { \
376 u64 __val; \
377 __val = read_sysreg_s(SYS_ ## key ## KEYLO_EL1); \
378 ctxt_sys_reg(ctxt, key ## KEYLO_EL1) = __val; \
379 __val = read_sysreg_s(SYS_ ## key ## KEYHI_EL1); \
380 ctxt_sys_reg(ctxt, key ## KEYHI_EL1) = __val; \
381 } while(0)
382
383 DECLARE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
384
__hyp_handle_ptrauth(struct kvm_vcpu * vcpu)385 static inline bool __hyp_handle_ptrauth(struct kvm_vcpu *vcpu)
386 {
387 struct kvm_cpu_context *ctxt;
388 u64 val;
389
390 if (!vcpu_has_ptrauth(vcpu) ||
391 !esr_is_ptrauth_trap(kvm_vcpu_get_esr(vcpu)))
392 return false;
393
394 ctxt = this_cpu_ptr(&kvm_hyp_ctxt);
395 __ptrauth_save_key(ctxt, APIA);
396 __ptrauth_save_key(ctxt, APIB);
397 __ptrauth_save_key(ctxt, APDA);
398 __ptrauth_save_key(ctxt, APDB);
399 __ptrauth_save_key(ctxt, APGA);
400
401 vcpu_ptrauth_enable(vcpu);
402
403 val = read_sysreg(hcr_el2);
404 val |= (HCR_API | HCR_APK);
405 write_sysreg(val, hcr_el2);
406
407 return true;
408 }
409
410 /*
411 * Return true when we were able to fixup the guest exit and should return to
412 * the guest, false when we should restore the host state and return to the
413 * main run loop.
414 */
fixup_guest_exit(struct kvm_vcpu * vcpu,u64 * exit_code)415 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
416 {
417 /*
418 * Save PSTATE early so that we can evaluate the vcpu mode
419 * early on.
420 */
421 vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR);
422
423 if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
424 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
425
426 if (ARM_SERROR_PENDING(*exit_code) &&
427 ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) {
428 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
429
430 /*
431 * HVC already have an adjusted PC, which we need to
432 * correct in order to return to after having injected
433 * the SError.
434 *
435 * SMC, on the other hand, is *trapped*, meaning its
436 * preferred return address is the SMC itself.
437 */
438 if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64)
439 write_sysreg_el2(read_sysreg_el2(SYS_ELR) - 4, SYS_ELR);
440 }
441
442 /*
443 * We're using the raw exception code in order to only process
444 * the trap if no SError is pending. We will come back to the
445 * same PC once the SError has been injected, and replay the
446 * trapping instruction.
447 */
448 if (*exit_code != ARM_EXCEPTION_TRAP)
449 goto exit;
450
451 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
452 kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 &&
453 handle_tx2_tvm(vcpu))
454 goto guest;
455
456 /*
457 * We trap the first access to the FP/SIMD to save the host context
458 * and restore the guest context lazily.
459 * If FP/SIMD is not implemented, handle the trap and inject an
460 * undefined instruction exception to the guest.
461 * Similarly for trapped SVE accesses.
462 */
463 if (__hyp_handle_fpsimd(vcpu))
464 goto guest;
465
466 if (__hyp_handle_ptrauth(vcpu))
467 goto guest;
468
469 if (!__populate_fault_info(vcpu))
470 goto guest;
471
472 if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
473 bool valid;
474
475 valid = kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_DABT_LOW &&
476 kvm_vcpu_trap_get_fault_type(vcpu) == FSC_FAULT &&
477 kvm_vcpu_dabt_isvalid(vcpu) &&
478 !kvm_vcpu_abt_issea(vcpu) &&
479 !kvm_vcpu_abt_iss1tw(vcpu);
480
481 if (valid) {
482 int ret = __vgic_v2_perform_cpuif_access(vcpu);
483
484 if (ret == 1)
485 goto guest;
486
487 /* Promote an illegal access to an SError.*/
488 if (ret == -1)
489 *exit_code = ARM_EXCEPTION_EL1_SERROR;
490
491 goto exit;
492 }
493 }
494
495 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
496 (kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 ||
497 kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_CP15_32)) {
498 int ret = __vgic_v3_perform_cpuif_access(vcpu);
499
500 if (ret == 1)
501 goto guest;
502 }
503
504 exit:
505 /* Return to the host kernel and handle the exit */
506 return false;
507
508 guest:
509 /* Re-enter the guest */
510 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));
511 return true;
512 }
513
__kvm_unexpected_el2_exception(void)514 static inline void __kvm_unexpected_el2_exception(void)
515 {
516 extern char __guest_exit_panic[];
517 unsigned long addr, fixup;
518 struct exception_table_entry *entry, *end;
519 unsigned long elr_el2 = read_sysreg(elr_el2);
520
521 entry = &__start___kvm_ex_table;
522 end = &__stop___kvm_ex_table;
523
524 while (entry < end) {
525 addr = (unsigned long)&entry->insn + entry->insn;
526 fixup = (unsigned long)&entry->fixup + entry->fixup;
527
528 if (addr != elr_el2) {
529 entry++;
530 continue;
531 }
532
533 write_sysreg(fixup, elr_el2);
534 return;
535 }
536
537 /* Trigger a panic after restoring the hyp context. */
538 write_sysreg(__guest_exit_panic, elr_el2);
539 }
540
541 #endif /* __ARM64_KVM_HYP_SWITCH_H__ */
542