1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HWREG_FRC_H_ 96 #define _HWREG_FRC_H_ 97 98 #include "MsCommon.h" 99 100 101 #define BK_REG_L( x, y ) ((x) | (((y) << 1))) 102 #define BK_REG_H( x, y ) (((x) | (((y) << 1))) + 1) 103 104 //============================================================= 105 #define REG_FRC_CHIP_BASE (REG_FRC_BANK_BASE+0x1E00) //REG_FRC_CHIP_BASE 106 107 #define REG_FRC_SC16_BASE (REG_FRC_BANK_BASE+0x1600) //REG_FRC_SC0_IP_BASE 108 109 #define REG_FRC_SC18_BASE (REG_FRC_BANK_BASE+0x1800) // 110 111 #define REG_FRC_SC20_BASE (REG_FRC_BANK_BASE+0x2000) //REG_FRC_SC0_IP_BASE 112 #define REG_FRC_SC21_BASE (REG_FRC_BANK_BASE+0x2100) //REG_FRC_SC1_VBI_BASE 113 #define REG_FRC_SC22_BASE (REG_FRC_BANK_BASE+0x2200) //REG_FRC_SC2_LVDSRX_BASE 114 #define REG_FRC_SC23_BASE (REG_FRC_BANK_BASE+0x2300) //REG_FRC_SC3_TCON_BASE 115 #define REG_FRC_SC24_BASE (REG_FRC_BANK_BASE+0x2400) //REG_FRC_SC4_SCTOP_BASE 116 #define REG_FRC_SC25_BASE (REG_FRC_BANK_BASE+0x2500) //REG_FRC_SC5_PWM_BASE 117 #define REG_FRC_SC26_BASE (REG_FRC_BANK_BASE+0x2600) //REG_FRC_SC6_MCPLUS_BASE 118 #define REG_FRC_SC27_BASE (REG_FRC_BANK_BASE+0x2700) //REG_FRC_SC7_MC_3FRAME_BASE 119 #define REG_FRC_SC28_BASE (REG_FRC_BANK_BASE+0x2800) //REG_FRC_SC8_OD_BASE 120 #define REG_FRC_SC29_BASE (REG_FRC_BANK_BASE+0x2900) //REG_FRC_SC9_MC2D_BASE 121 #define REG_FRC_SC2A_BASE (REG_FRC_BANK_BASE+0x2A00) //REG_FRC_SC10_DISP_LPLL_BASE 122 #define REG_FRC_SC2C_BASE (REG_FRC_BANK_BASE+0x2C00) //REG_FRC_SC16_MC2D_BASE 123 #define REG_FRC_SC2D_BASE (REG_FRC_BANK_BASE+0x2D00) //REG_FRC_SC17_IP_BASE 124 #define REG_FRC_SC2E_BASE (REG_FRC_BANK_BASE+0x2E00) //REG_FRC_SC11_SNR_BASE 125 #define REG_FRC_SC2F_BASE (REG_FRC_BANK_BASE+0x2F00) //REG_FRC_SC12_DISP_TGEN_BASE 126 #define REG_FRC_SC30_BASE (REG_FRC_BANK_BASE+0x3000) //REG_FRC_SC13_VOP2_BASE 127 #define REG_FRC_SC31_BASE (REG_FRC_BANK_BASE+0x3100) //REG_FRC_SC14_MFT_BASE 128 #define REG_FRC_SC32_BASE (REG_FRC_BANK_BASE+0x3200) //REG_FRC_SC15_MISC_BASE 129 #define REG_FRC_SC33_BASE (REG_FRC_BANK_BASE+0x3300) //REG_FRC_SC18_LD_BASE 130 #define REG_FRC_SC38_BASE (REG_FRC_BANK_BASE+0x3800) //REG_FRC_SC19_OD_LG_BASE 131 #define REG_FRC_SC3A_BASE (REG_FRC_BANK_BASE+0x3A00) //REG_FRC_SC20_MC2D_BASE 132 #define REG_FRC_SC3B_BASE (REG_FRC_BANK_BASE+0x3B00) //REG_FRC_SC21_NEW_FILM_BASE 133 #define REG_FRC_SC3D_BASE (REG_FRC_BANK_BASE+0x3D00) //REG_FRC_SC22_ADL_BASE 134 #define REG_FRC_SC3E_BASE (REG_FRC_BANK_BASE+0x3E00) //REG_FRC_SC25_HVSP_BASE 135 #define REG_FRC_SC130_BASE (REG_FRC_BANK_BASE+0x13000) //REG_FRC_SC26_3DD_BASE 136 #define REG_FRC_SC134_BASE (REG_FRC_BANK_BASE+0x13400) //REG_FRC_SC134_IPM_BASE 137 #define REG_FRC_SC135_BASE (REG_FRC_BANK_BASE+0x13500) //REG_FRC_SC135_OPM_BASE 138 139 //============================================================= 140 #define L_FRC_CHIP(x) BK_REG_L(REG_FRC_CHIP_BASE, x) 141 #define H_FRC_CHIP(x) BK_REG_H(REG_FRC_CHIP_BASE, x) 142 143 #define L_FRC_SC16(x) BK_REG_L(REG_FRC_SC16_BASE, x) 144 #define H_FRC_SC16(x) BK_REG_H(REG_FRC_SC16_BASE, x) 145 146 #define L_FRC_SC18(x) BK_REG_L(REG_FRC_SC18_BASE, x) 147 #define H_FRC_SC18(x) BK_REG_H(REG_FRC_SC18_BASE, x) 148 149 #define L_FRC_SC20(x) BK_REG_L(REG_FRC_SC20_BASE, x) 150 #define H_FRC_SC20(x) BK_REG_H(REG_FRC_SC20_BASE, x) 151 #define L_FRC_SC21(x) BK_REG_L(REG_FRC_SC21_BASE, x) 152 #define H_FRC_SC21(x) BK_REG_H(REG_FRC_SC21_BASE, x) 153 #define L_FRC_SC22(x) BK_REG_L(REG_FRC_SC22_BASE, x) 154 #define H_FRC_SC22(x) BK_REG_H(REG_FRC_SC22_BASE, x) 155 #define L_FRC_SC23(x) BK_REG_L(REG_FRC_SC23_BASE, x) 156 #define H_FRC_SC23(x) BK_REG_H(REG_FRC_SC23_BASE, x) 157 #define L_FRC_SC24(x) BK_REG_L(REG_FRC_SC24_BASE, x) 158 #define H_FRC_SC24(x) BK_REG_H(REG_FRC_SC24_BASE, x) 159 #define L_FRC_SC25(x) BK_REG_L(REG_FRC_SC25_BASE, x) 160 #define H_FRC_SC25(x) BK_REG_H(REG_FRC_SC25_BASE, x) 161 #define L_FRC_SC26(x) BK_REG_L(REG_FRC_SC26_BASE, x) 162 #define H_FRC_SC26(x) BK_REG_H(REG_FRC_SC26_BASE, x) 163 #define L_FRC_SC27(x) BK_REG_L(REG_FRC_SC27_BASE, x) 164 #define H_FRC_SC27(x) BK_REG_H(REG_FRC_SC27_BASE, x) 165 #define L_FRC_SC28(x) BK_REG_L(REG_FRC_SC28_BASE, x) 166 #define H_FRC_SC28(x) BK_REG_H(REG_FRC_SC28_BASE, x) 167 #define L_FRC_SC29(x) BK_REG_L(REG_FRC_SC29_BASE, x) 168 #define H_FRC_SC29(x) BK_REG_H(REG_FRC_SC29_BASE, x) 169 #define L_FRC_SC2A(x) BK_REG_L(REG_FRC_SC2A_BASE, x) 170 #define H_FRC_SC2A(x) BK_REG_H(REG_FRC_SC2A_BASE, x) 171 #define L_FRC_SC2C(x) BK_REG_L(REG_FRC_SC2C_BASE, x) 172 #define H_FRC_SC2C(x) BK_REG_H(REG_FRC_SC2C_BASE, x) 173 #define L_FRC_SC2D(x) BK_REG_L(REG_FRC_SC2D_BASE, x) 174 #define H_FRC_SC2D(x) BK_REG_H(REG_FRC_SC2D_BASE, x) 175 #define L_FRC_SC2E(x) BK_REG_L(REG_FRC_SC2E_BASE, x) 176 #define H_FRC_SC2E(x) BK_REG_H(REG_FRC_SC2E_BASE, x) 177 #define L_FRC_SC2F(x) BK_REG_L(REG_FRC_SC2F_BASE, x) 178 #define H_FRC_SC2F(x) BK_REG_H(REG_FRC_SC2F_BASE, x) 179 #define L_FRC_SC30(x) BK_REG_L(REG_FRC_SC30_BASE, x) 180 #define H_FRC_SC30(x) BK_REG_H(REG_FRC_SC30_BASE, x) 181 #define L_FRC_SC31(x) BK_REG_L(REG_FRC_SC31_BASE, x) 182 #define H_FRC_SC31(x) BK_REG_H(REG_FRC_SC31_BASE, x) 183 #define L_FRC_SC32(x) BK_REG_L(REG_FRC_SC32_BASE, x) 184 #define H_FRC_SC32(x) BK_REG_H(REG_FRC_SC32_BASE, x) 185 #define L_FRC_SC33(x) BK_REG_L(REG_FRC_SC33_BASE, x) 186 #define H_FRC_SC33(x) BK_REG_H(REG_FRC_SC33_BASE, x) 187 #define L_FRC_SC38(x) BK_REG_L(REG_FRC_SC38_BASE, x) 188 #define H_FRC_SC38(x) BK_REG_H(REG_FRC_SC38_BASE, x) 189 #define L_FRC_SC3A(x) BK_REG_L(REG_FRC_SC3A_BASE, x) 190 #define H_FRC_SC3A(x) BK_REG_H(REG_FRC_SC3A_BASE, x) 191 #define L_FRC_SC3B(x) BK_REG_L(REG_FRC_SC3B_BASE, x) 192 #define H_FRC_SC3B(x) BK_REG_H(REG_FRC_SC3B_BASE, x) 193 #define L_FRC_SC3D(x) BK_REG_L(REG_FRC_SC3D_BASE, x) 194 #define H_FRC_SC3D(x) BK_REG_H(REG_FRC_SC3D_BASE, x) 195 #define L_FRC_SC3E(x) BK_REG_L(REG_FRC_SC3E_BASE, x) 196 #define H_FRC_SC3E(x) BK_REG_H(REG_FRC_SC3E_BASE, x) 197 #define L_FRC_SC3F(x) BK_REG_L(REG_FRC_SC3E_BASE, x) 198 #define H_FRC_SC3F(x) BK_REG_H(REG_FRC_SC3E_BASE, x) 199 #define L_FRC_SC130(x) BK_REG_L(REG_FRC_SC130_BASE, x) 200 #define H_FRC_SC130(x) BK_REG_H(REG_FRC_SC130_BASE, x) 201 #define L_FRC_SC134(x) BK_REG_L(REG_FRC_SC134_BASE, x) 202 #define H_FRC_SC134(x) BK_REG_H(REG_FRC_SC134_BASE, x) 203 #define L_FRC_SC135(x) BK_REG_L(REG_FRC_SC135_BASE, x) 204 #define H_FRC_SC135(x) BK_REG_H(REG_FRC_SC135_BASE, x) 205 206 207 #endif 208 209 210