1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef HW_IEP_CONFIG_ADDR_H_ 3 #define HW_IEP_CONFIG_ADDR_H_ 4 5 #include <asm/io.h> 6 7 /*ignore the IEP_BASE when program running in linux kernel */ 8 #define IEP_BASE 0x0 9 10 #define IEP_CONFIG0 0x0000 11 #define IEP_CONFIG1 0x0004 12 13 #define IEP_STATUS 0x0008 14 #define IEP_INT 0x000C 15 #define IEP_FRM_START 0x0010 16 #define IEP_SOFT_RST 0x0014 17 #define IEP_CONF_DONE 0x0018 18 19 #define IEP_VIR_IMG_WIDTH 0x0020 20 21 #define IEP_IMG_SCL_FCT 0x0024 22 23 #define IEP_SRC_IMG_SIZE 0x0028 24 #define IEP_DST_IMG_SIZE 0x002C 25 26 #define IEP_DST_IMG_WIDTH_TILE0 0x0030 27 #define IEP_DST_IMG_WIDTH_TILE1 0x0034 28 #define IEP_DST_IMG_WIDTH_TILE2 0x0038 29 #define IEP_DST_IMG_WIDTH_TILE3 0x003C 30 31 #define IEP_ENH_YUV_CNFG_0 0x0040 32 #define IEP_ENH_YUV_CNFG_1 0x0044 33 #define IEP_ENH_YUV_CNFG_2 0x0048 34 #define IEP_ENH_RGB_CNFG 0x004C 35 #define IEP_ENH_C_COE 0x0050 36 37 #define IEP_SRC_ADDR_YRGB 0x0080 38 #define IEP_SRC_ADDR_CBCR 0x0084 39 #define IEP_SRC_ADDR_CR 0x0088 40 #define IEP_SRC_ADDR_Y1 0x008C 41 #define IEP_SRC_ADDR_CBCR1 0x0090 42 #define IEP_SRC_ADDR_CR1 0x0094 43 #define IEP_SRC_ADDR_Y_ITEMP 0x0098 44 #define IEP_SRC_ADDR_CBCR_ITEMP 0x009C 45 #define IEP_SRC_ADDR_CR_ITEMP 0x00A0 46 #define IEP_SRC_ADDR_Y_FTEMP 0x00A4 47 #define IEP_SRC_ADDR_CBCR_FTEMP 0x00A8 48 #define IEP_SRC_ADDR_CR_FTEMP 0x00AC 49 50 #define IEP_DST_ADDR_YRGB 0x00B0 51 #define IEP_DST_ADDR_CBCR 0x00B4 52 #define IEP_DST_ADDR_CR 0x00B8 53 #define IEP_DST_ADDR_Y1 0x00BC 54 #define IEP_DST_ADDR_CBCR1 0x00C0 55 #define IEP_DST_ADDR_CR1 0x00C4 56 #define IEP_DST_ADDR_Y_ITEMP 0x00C8 57 #define IEP_DST_ADDR_CBCR_ITEMP 0x00CC 58 #define IEP_DST_ADDR_CR_ITEMP 0x00D0 59 #define IEP_DST_ADDR_Y_FTEMP 0x00D4 60 #define IEP_DST_ADDR_CBCR_FTEMP 0x00D8 61 #define IEP_DST_ADDR_CR_FTEMP 0x00DC 62 63 #define IEP_DIL_MTN_TAB0 0x00E0 64 #define IEP_DIL_MTN_TAB1 0x00E4 65 #define IEP_DIL_MTN_TAB2 0x00E8 66 #define IEP_DIL_MTN_TAB3 0x00EC 67 #define IEP_DIL_MTN_TAB4 0x00F0 68 #define IEP_DIL_MTN_TAB5 0x00F4 69 #define IEP_DIL_MTN_TAB6 0x00F8 70 #define IEP_DIL_MTN_TAB7 0x00FC 71 72 #define IEP_ENH_CG_TAB 0x0100 73 74 #define IEP_YUV_DNS_CRCT_TEMP 0x0400 75 #define IEP_YUV_DNS_CRCT_SPAT 0x0800 76 77 #define IEP_ENH_DDE_COE0 0x0C00 78 #define IEP_ENH_DDE_COE1 0x0E00 79 80 #define RAW_IEP_CONFIG0 0x0058 81 #define RAW_IEP_CONFIG1 0x005C 82 #define RAW_IEP_VIR_IMG_WIDTH 0x0060 83 84 #define RAW_IEP_IMG_SCL_FCT 0x0064 85 86 #define RAW_IEP_SRC_IMG_SIZE 0x0068 87 #define RAW_IEP_DST_IMG_SIZE 0x006C 88 89 #define RAW_IEP_ENH_YUV_CNFG_0 0x0070 90 #define RAW_IEP_ENH_YUV_CNFG_1 0x0074 91 #define RAW_IEP_ENH_YUV_CNFG_2 0x0078 92 #define RAW_IEP_ENH_RGB_CNFG 0x007C 93 94 #define ReadReg32(base, raddr) (__raw_readl(base + raddr)) 95 #define WriteReg32(base, waddr, value) (__raw_writel(value, base + waddr)) 96 #define ConfRegBits32(base, raddr, waddr, position, value) WriteReg32(base, waddr, (ReadReg32(base, waddr)&~(position))|(value)) 97 #define MaskRegBits32(base, waddr, position, value) WriteReg32(base, waddr, (ReadReg32(base, waddr)&~(position))|(value)) 98 99 #endif 100