1 /****************************************************************************** 2 * 3 * Copyright(c) 2019 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _HAL_TX_8852BE_H_ 16 #define _HAL_TX_8852BE_H_ 17 18 #define MAX_RX_TAG_VALUE 0x1FFF 19 20 #define ACH0_QUEUE_IDX_8852BE 0x0 21 #define ACH1_QUEUE_IDX_8852BE 0x1 22 #define ACH2_QUEUE_IDX_8852BE 0x2 23 #define ACH3_QUEUE_IDX_8852BE 0x3 24 #define ACH4_QUEUE_IDX_8852BE 0x4 25 #define ACH5_QUEUE_IDX_8852BE 0x5 26 #define ACH6_QUEUE_IDX_8852BE 0x6 27 #define ACH7_QUEUE_IDX_8852BE 0x7 28 #define MGQ_B0_QUEUE_IDX_8852BE 0x8 29 #define HIQ_B0_QUEUE_IDX_8852BE 0x9 30 #define MGQ_B1_QUEUE_IDX_8852BE 0xa 31 #define HIQ_B1_QUEUE_IDX_8852BE 0xb 32 #define FWCMD_QUEUE_IDX_8852BE 0xc 33 34 #define RX_QUEUE_IDX_8852BE 0x10 35 #define RP_QUEUE_IDX_8852BE 0x11 36 37 #define RTW_TXDESC_QSEL_BE_0 0x0 38 #define RTW_TXDESC_QSEL_BK_0 0x1 39 #define RTW_TXDESC_QSEL_VI_0 0x2 40 #define RTW_TXDESC_QSEL_VO_0 0x3 41 #define RTW_TXDESC_QSEL_BE_1 0x4 42 #define RTW_TXDESC_QSEL_BK_1 0x5 43 #define RTW_TXDESC_QSEL_VI_1 0x6 44 #define RTW_TXDESC_QSEL_VO_1 0x7 45 #define RTW_TXDESC_QSEL_BE_2 0x8 46 #define RTW_TXDESC_QSEL_BK_2 0x9 47 #define RTW_TXDESC_QSEL_VI_2 0xa 48 #define RTW_TXDESC_QSEL_VO_2 0xb 49 #define RTW_TXDESC_QSEL_BE_3 0xc 50 #define RTW_TXDESC_QSEL_BK_3 0xd 51 #define RTW_TXDESC_QSEL_VI_3 0xe 52 #define RTW_TXDESC_QSEL_VO_3 0xf 53 54 #define RTW_TXDESC_QSEL_BCN_0 0x10 55 #define RTW_TXDESC_QSEL_HIGH_0 0x11 56 #define RTW_TXDESC_QSEL_MGT_0 0x12 57 #define RTW_TXDESC_QSEL_MGT_NOPS_0 0x13 58 #define RTW_TXDESC_QSEL_CPU_MGT_0 0x14 59 #define RTW_TXDESC_QSEL_BCN_1 0x18 60 #define RTW_TXDESC_QSEL_HIGH_1 0x19 61 #define RTW_TXDESC_QSEL_MGT_1 0x1a 62 #define RTW_TXDESC_QSEL_MGT_NOPS_1 0x1b 63 #define RTW_TXDESC_QSEL_CPU_MGT_1 0x1c 64 65 66 /* AC channel * 8 + MGQ * 2 + HIQ * 2 + FW CMDQ * 1 */ 67 #define TX_DMA_CHANNEL_ENTRY_8852BE 13 68 /* RXQ * 1 + RPQ * 1 */ 69 #define RX_DMA_CHANNEL_ENTRY_8852BE 2 70 71 72 /* temp register definitions, will be replaced by halmac */ 73 #define R_AX_RXQ_RXBD_IDX 0x1050 74 #define R_AX_RPQ_RXBD_IDX 0x1054 75 #define R_AX_ACH0_TXBD_IDX 0x1058 76 #define R_AX_ACH1_TXBD_IDX 0x105C 77 #define R_AX_ACH2_TXBD_IDX 0x1060 78 #define R_AX_ACH3_TXBD_IDX 0x1064 79 #define R_AX_ACH4_TXBD_IDX 0x1068 80 #define R_AX_ACH5_TXBD_IDX 0x106C 81 #define R_AX_ACH6_TXBD_IDX 0x1070 82 #define R_AX_ACH7_TXBD_IDX 0x1074 83 #define R_AX_CH8_TXBD_IDX 0x1078 /* Mgnt Queue band 0 */ 84 #define R_AX_CH9_TXBD_IDX 0x107C /* HI Queue band 0 */ 85 #define R_AX_CH10_TXBD_IDX 0x137C /* Mgnt Queue band 1 */ 86 #define R_AX_CH11_TXBD_IDX 0x1380 /* HI Queue band 1 */ 87 #define R_AX_CH12_TXBD_IDX 0x1080 /* FW CMD */ 88 89 #define R_AX_ACH0_TXBD_DESA_L 0x1110 90 #define R_AX_ACH0_TXBD_DESA_H 0x1114 91 #define R_AX_ACH1_TXBD_DESA_L 0x1118 92 #define R_AX_ACH1_TXBD_DESA_H 0x111C 93 #define R_AX_ACH2_TXBD_DESA_L 0x1120 94 #define R_AX_ACH2_TXBD_DESA_H 0x1124 95 #define R_AX_ACH3_TXBD_DESA_L 0x1128 96 #define R_AX_ACH3_TXBD_DESA_H 0x112C 97 #define R_AX_ACH4_TXBD_DESA_L 0x1130 98 #define R_AX_ACH4_TXBD_DESA_H 0x1134 99 #define R_AX_ACH5_TXBD_DESA_L 0x1138 100 #define R_AX_ACH5_TXBD_DESA_H 0x113C 101 #define R_AX_ACH6_TXBD_DESA_L 0x1140 102 #define R_AX_ACH6_TXBD_DESA_H 0x1144 103 #define R_AX_ACH7_TXBD_DESA_L 0x1148 104 #define R_AX_ACH7_TXBD_DESA_H 0x114C 105 #define R_AX_CH8_TXBD_DESA_L 0x1150 106 #define R_AX_CH8_TXBD_DESA_H 0x1154 107 #define R_AX_CH9_TXBD_DESA_L 0x1158 108 #define R_AX_CH9_TXBD_DESA_H 0x115C 109 #define R_AX_CH10_TXBD_DESA_L 0x1358 110 #define R_AX_CH10_TXBD_DESA_H 0x135C 111 #define R_AX_CH11_TXBD_DESA_L 0x1360 112 #define R_AX_CH11_TXBD_DESA_H 0x1364 113 #define R_AX_CH12_TXBD_DESA_L 0x1160 114 #define R_AX_CH12_TXBD_DESA_H 0x1164 115 #define R_AX_RXQ_RXBD_DESA_L 0x1100 116 #define R_AX_RXQ_RXBD_DESA_H 0x1104 117 #define R_AX_RPQ_RXBD_DESA_L 0x1108 118 #define R_AX_RPQ_RXBD_DESA_H 0x110C 119 120 #define B_AX_DESC_NUM_MSK 0xfff 121 122 #define R_AX_RXQ_RXBD_NUM 0x1020 123 #define R_AX_RPQ_RXBD_NUM 0x1022 124 #define R_AX_ACH0_TXBD_NUM 0x1024 125 #define R_AX_ACH1_TXBD_NUM 0x1026 126 #define R_AX_ACH2_TXBD_NUM 0x1028 127 #define R_AX_ACH3_TXBD_NUM 0x102A 128 #define R_AX_ACH4_TXBD_NUM 0x102C 129 #define R_AX_ACH5_TXBD_NUM 0x102E 130 #define R_AX_ACH6_TXBD_NUM 0x1030 131 #define R_AX_ACH7_TXBD_NUM 0x1032 132 #define R_AX_CH8_TXBD_NUM 0x1034 133 #define R_AX_CH9_TXBD_NUM 0x1036 134 #define R_AX_CH10_TXBD_NUM 0x1338 135 #define R_AX_CH11_TXBD_NUM 0x133A 136 #define R_AX_CH12_TXBD_NUM 0x1038 137 138 139 #define R_AX_ACH0_BDRAM_CTRL 0x1200 140 #define R_AX_ACH1_BDRAM_CTRL 0x1204 141 #define R_AX_ACH2_BDRAM_CTRL 0x1208 142 #define R_AX_ACH3_BDRAM_CTRL 0x120C 143 #define R_AX_ACH4_BDRAM_CTRL 0x1210 144 #define R_AX_ACH5_BDRAM_CTRL 0x1214 145 #define R_AX_ACH6_BDRAM_CTRL 0x1218 146 #define R_AX_ACH7_BDRAM_CTRL 0x121C 147 #define R_AX_CH8_BDRAM_CTRL 0x1220 148 #define R_AX_CH9_BDRAM_CTRL 0x1224 149 #define R_AX_CH10_BDRAM_CTRL 0x1320 150 #define R_AX_CH11_BDRAM_CTRL 0x1324 151 #define R_AX_CH12_BDRAM_CTRL 0x1228 152 153 #define R_AX_PCIE_INIT_CFG1 0x1000 154 #define B_AX_PCIE_RXRST_KEEP_REG BIT(23) 155 #define B_AX_PCIE_TXRST_KEEP_REG BIT(22) 156 #define B_AX_PCIE_PERST_KEEP_REG BIT(21) 157 #define B_AX_PCIE_FLR_KEEP_REG BIT(20) 158 #define B_AX_PCIE_TRAIN_KEEP_REG BIT(19) 159 #define B_AX_RXBD_MODE BIT(18) 160 #define B_AX_PCIE_MAX_RXDMA_SH 14 161 #define B_AX_PCIE_MAX_RXDMA_MSK 0x7 162 #define B_AX_RXHCI_EN BIT(13) 163 #define B_AX_LATENCY_CONTROL BIT(12) 164 #define B_AX_TXHCI_EN BIT(11) 165 #define B_AX_PCIE_MAX_TXDMA_SH 8 166 #define B_AX_PCIE_MAX_TXDMA_MSK 0x7 167 #define B_AX_TX_TRUNC_MODE BIT(5) 168 #define B_AX_RX_TRUNC_MODE BIT(4) 169 #define B_AX_RST_BDRAM BIT(3) 170 #define B_AX_DIS_RXDMA_PRE BIT(2) 171 172 #define R_AX_TXDMA_ADDR_H 0x10F0 173 #define R_AX_RXDMA_ADDR_H 0x10F4 174 175 #define R_AX_PCIE_DMA_STOP1 0x1010 176 #define B_AX_STOP_WPDMA BIT(19) 177 #define B_AX_STOP_CH12 BIT(18) 178 #define B_AX_STOP_CH9 BIT(17) 179 #define B_AX_STOP_CH8 BIT(16) 180 #define B_AX_STOP_ACH7 BIT(15) 181 #define B_AX_STOP_ACH6 BIT(14) 182 #define B_AX_STOP_ACH5 BIT(13) 183 #define B_AX_STOP_ACH4 BIT(12) 184 #define B_AX_STOP_ACH3 BIT(11) 185 #define B_AX_STOP_ACH2 BIT(10) 186 #define B_AX_STOP_ACH1 BIT(9) 187 #define B_AX_STOP_ACH0 BIT(8) 188 #define B_AX_STOP_RPQ BIT(1) 189 #define B_AX_STOP_RXQ BIT(0) 190 191 192 #define R_AX_PCIE_DMA_STOP2 0x1310 193 #define B_AX_STOP_CH11 BIT(1) 194 #define B_AX_STOP_CH10 BIT(0) 195 196 #define R_AX_TXBD_RWPTR_CLR1 0x1014 197 #define B_AX_CLR_CH12_IDX BIT(10) 198 #define B_AX_CLR_CH9_IDX BIT(9) 199 #define B_AX_CLR_CH8_IDX BIT(8) 200 #define B_AX_CLR_ACH7_IDX BIT(7) 201 #define B_AX_CLR_ACH6_IDX BIT(6) 202 #define B_AX_CLR_ACH5_IDX BIT(5) 203 #define B_AX_CLR_ACH4_IDX BIT(4) 204 #define B_AX_CLR_ACH3_IDX BIT(3) 205 #define B_AX_CLR_ACH2_IDX BIT(2) 206 #define B_AX_CLR_ACH1_IDX BIT(1) 207 #define B_AX_CLR_ACH0_IDX BIT(0) 208 209 #define R_AX_RXBD_RWPTR_CLR 0x1018 210 #define B_AX_CLR_RPQ_IDX BIT(1) 211 #define B_AX_CLR_RXQ_IDX BIT(0) 212 213 214 #define R_AX_TXBD_RWPTR_CLR2 0x1314 215 #define B_AX_CLR_CH11_IDX BIT(1) 216 #define B_AX_CLR_CH10_IDX BIT(0) 217 218 #define R_AX_PCIE_DMA_BUSY2 0x131C 219 #define B_AX_CH11_BUSY BIT(1) 220 #define B_AX_CH10_BUSY BIT(0) 221 222 #define GET_RX_RP_PKT_POLLUTED(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 31, 1) 223 #define GET_RX_RP_PKT_PCIE_SEQ(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 16, 15) 224 #define GET_RX_RP_PKT_TX_STS(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 13, 3) 225 #define GET_RX_RP_PKT_QSEL(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 8, 5) 226 #define GET_RX_RP_PKT_MAC_ID(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 0, 8) 227 228 /* TX BD */ 229 #define SET_TXBUFFER_DESC_LEN(__pTxDesc, __Value) \ 230 SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 0, 16, __Value) 231 #define SET_TXBUFFER_DESC_ADD_HIGH(__pTxDesc, __Value) \ 232 SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 22, 8, __Value) 233 #define SET_TXBUFFER_DESC_LS(__pTxDesc, __Value) \ 234 SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 30, 1, __Value) 235 #define SET_TXBUFFER_DESC_ADD_LOW(__pTxDesc, __Value) \ 236 SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 0, 32, __Value) 237 238 #define GET_TXBUFFER_DESC_LEN(_pTxDesc) \ 239 LE_BITS_TO_4BYTE(_pTxDesc + 0x00, 0, 16) 240 #define GET_TXBUFFER_DESC_ADD_HIGH(_pTxDesc) \ 241 LE_BITS_TO_4BYTE(_pTxDesc + 0x00, 22, 8) 242 #define GET_TXBUFFER_DESC_LS(_pTxDesc) \ 243 LE_BITS_TO_4BYTE(_pTxDesc + 0x00, 30, 1) 244 #define GET_TXBUFFER_DESC_ADD_LOW(_pTxDesc) \ 245 LE_BITS_TO_4BYTE(_pTxDesc + 0x04, 0, 32) 246 247 248 249 /* PCIE_SEQ Info */ 250 #define SET_PCIE_SEQ_INFO_0(__seq_info, __value) \ 251 SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 0, 15, __value) 252 #define SET_PCIE_SEQ_INFO_0_VALID(__seq_info, __value) \ 253 SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 15, 1, __value) 254 #define SET_PCIE_SEQ_INFO_1(__seq_info, __value) \ 255 SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 16, 15, __value) 256 #define SET_PCIE_SEQ_INFO_1_VALID(__seq_info, __value) \ 257 SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 31, 1, __value) 258 #define SET_PCIE_SEQ_INFO_2(__seq_info, __value) \ 259 SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 0, 15, __value) 260 #define SET_PCIE_SEQ_INFO_2_VALID(__seq_info, __value) \ 261 SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 15, 1, __value) 262 #define SET_PCIE_SEQ_INFO_3(__seq_info, __value) \ 263 SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 16, 15, __value) 264 #define SET_PCIE_SEQ_INFO_3_VALID(__seq_info, __value) \ 265 SET_BITS_TO_LE_4BYTE(__seq_info + 0x00, 31, 1, __value) 266 267 /* PCIE_SEQ Info */ 268 #define GET_PCIE_SEQ_INFO_0(__seq_info) \ 269 LE_BITS_TO_4BYTE(__seq_info + 0x00, 0, 15) 270 #define GET_PCIE_SEQ_INFO_0_VALID(__seq_info) \ 271 LE_BITS_TO_4BYTE(__seq_info + 0x00, 15, 1) 272 #define GET_PCIE_SEQ_INFO_1(__seq_info) \ 273 LE_BITS_TO_4BYTE(__seq_info + 0x00, 16, 15) 274 #define GET_PCIE_SEQ_INFO_1_VALID(__seq_info) \ 275 LE_BITS_TO_4BYTE(__seq_info + 0x00, 31, 1) 276 #define GET_PCIE_SEQ_INFO_2(__seq_info) \ 277 LE_BITS_TO_4BYTE(__seq_info + 0x00, 0, 15) 278 #define GET_PCIE_SEQ_INFO_2_VALID(__seq_info) \ 279 LE_BITS_TO_4BYTE(__seq_info + 0x00, 15, 1) 280 #define GET_PCIE_SEQ_INFO_3(__seq_info) \ 281 LE_BITS_TO_4BYTE(__seq_info + 0x00, 16, 15) 282 #define GET_PCIE_SEQ_INFO_3_VALID(__seq_info) \ 283 LE_BITS_TO_4BYTE(__seq_info + 0x00, 31, 1) 284 285 286 /* Addr Info */ 287 #define SET_ADDR_INFO_LEN(__addr_info, __value) \ 288 SET_BITS_TO_LE_4BYTE(__addr_info + 0x00, 0, 16, __value) 289 #define SET_ADDR_INFO_NUM(__addr_info, __value) \ 290 SET_BITS_TO_LE_4BYTE(__addr_info + 0x00, 16, 6, __value) 291 #define SET_ADDR_INFO_ADDR_HIGH(__addr_info, __value) \ 292 SET_BITS_TO_LE_4BYTE(__addr_info + 0x00, 22, 8, __value) 293 #define SET_ADDR_INFO_LS(__addr_info, __value) \ 294 SET_BITS_TO_LE_4BYTE(__addr_info + 0x00, 30, 1, __value) 295 #define SET_ADDR_INFO_MSDU_LS(__addr_info, __value) \ 296 SET_BITS_TO_LE_4BYTE(__addr_info + 0x00, 31, 1, __value) 297 #define SET_ADDR_INFO_ADDR_LOW(__addr_info, __value) \ 298 SET_BITS_TO_LE_4BYTE(__addr_info + 0x04, 0, 32, __value) 299 300 /* Addr Info */ 301 #define GET_ADDR_INFO_LEN(__addr_info) \ 302 LE_BITS_TO_4BYTE(__addr_info + 0x00, 0, 16) 303 #define GET_ADDR_INFO_NUM(__addr_info) \ 304 LE_BITS_TO_4BYTE(__addr_info + 0x00, 16, 6) 305 #define GET_ADDR_INFO_ADDR_HIGH(__addr_info) \ 306 LE_BITS_TO_4BYTE(__addr_info + 0x00, 22, 8) 307 #define GET_ADDR_INFO_LS(__addr_info) \ 308 LE_BITS_TO_4BYTE(__addr_info + 0x00, 30, 1) 309 #define GET_ADDR_INFO_MSDU_LS(__addr_info) \ 310 LE_BITS_TO_4BYTE(__addr_info + 0x00, 31, 1) 311 #define GET_ADDR_INFO_ADDR_LOW(__addr_info) \ 312 LE_BITS_TO_4BYTE(__addr_info + 0x04, 0, 32) 313 314 315 #define RX_RP_PACKET_SIZE 4 316 317 /* RX BD */ 318 #define SET_RX_BD_RXBUFFSIZE(__pRxBd, __Value) \ 319 SET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 0, 14, __Value) 320 #define SET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd, __Value) \ 321 SET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 22, 8, __Value) 322 #define SET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd, __Value) \ 323 SET_BITS_TO_LE_4BYTE(__pRxBd + 0x04, 0, 32, __Value) 324 325 /* RX RD INFO */ 326 #define SET_RX_BD_INFO_TAG(rxdesc, value) \ 327 SET_BITS_TO_LE_4BYTE(rxdesc + 0x00, 16, 13, value) 328 #define SET_RX_BD_INFO_FS(rxdesc, value) \ 329 SET_BITS_TO_LE_4BYTE(rxdesc + 0x00, 15, 1, value) 330 #define SET_RX_BD_INFO_LS(rxdesc, value) \ 331 SET_BITS_TO_LE_4BYTE(rxdesc + 0x00, 14, 1, value) 332 #define SET_RX_BD_INFO_HW_W_SIZE(rxdesc, value) \ 333 SET_BITS_TO_LE_4BYTE(rxdesc + 0x00, 0, 14, value) 334 335 #define GET_RX_BD_INFO_TAG(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 16, 13) 336 #define GET_RX_BD_INFO_FS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 15, 1) 337 #define GET_RX_BD_INFO_LS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 14, 1) 338 #define GET_RX_BD_INFO_HW_W_SIZE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 0, 14) 339 340 /* RX RP PACKET */ 341 #define SET_RX_RP_PKT_POLLUTED(rppkt, value) \ 342 SET_BITS_TO_LE_4BYTE(rppkt + 0x00, 31, 1, value) 343 #define SET_RX_RP_PKT_PCIE_SEQ(rppkt, value) \ 344 SET_BITS_TO_LE_4BYTE(rppkt + 0x00, 16, 15, value) 345 #define SET_RX_RP_PKT_TX_STS(rppkt, value) \ 346 SET_BITS_TO_LE_4BYTE(rppkt + 0x00, 13, 3, value) 347 #define SET_RX_RP_PKT_QSEL(rppkt, value) \ 348 SET_BITS_TO_LE_4BYTE(rppkt + 0x00, 8, 5, value) 349 #define SET_RX_RP_PKT_MAC_ID(rppkt, value) \ 350 SET_BITS_TO_LE_4BYTE(rppkt + 0x00, 0, 8, value) 351 352 #define GET_RX_RP_PKT_POLLUTED(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 31, 1) 353 #define GET_RX_RP_PKT_PCIE_SEQ(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 16, 15) 354 #define GET_RX_RP_PKT_TX_STS(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 13, 3) 355 #define GET_RX_RP_PKT_QSEL(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 8, 5) 356 #define GET_RX_RP_PKT_MAC_ID(rppkt) LE_BITS_TO_4BYTE(rppkt + 0x00, 0, 8) 357 358 /* CONFIG_PHL_TXSC */ 359 #define TID_0_QSEL 0 360 #define TID_1_QSEL 1 361 #define TID_2_QSEL 1 362 #define TID_3_QSEL 0 363 #define TID_4_QSEL 2 364 #define TID_5_QSEL 2 365 #define TID_6_QSEL 3 366 #define TID_7_QSEL 3 367 #define TID_0_IND 0 368 #define TID_1_IND 0 369 #define TID_2_IND 1 370 #define TID_3_IND 1 371 #define TID_4_IND 0 372 #define TID_5_IND 1 373 #define TID_6_IND 0 374 #define TID_7_IND 1 375 376 enum rxbd_mode_8852BE { 377 RXBD_MODE_PACKET = 0, 378 RXBD_MODE_SEPARATION = 1, 379 RXBD_MODE_MAX = 0xFF 380 }; 381 382 struct bd_ram { 383 u8 sidx; 384 u8 max; 385 u8 min; 386 }; 387 388 #endif 389 390