1 /* 2 * Copyright 2017 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __HAL_M4V_VDPU1_REG_TBL_H__ 18 #define __HAL_M4V_VDPU1_REG_TBL_H__ 19 20 #include "rk_type.h" 21 22 /* Number registers for the decoder */ 23 #define DEC_VDPU1_REGISTERS (101) 24 25 typedef struct { 26 RK_U32 SwReg00; 27 28 struct { 29 RK_U32 sw_dec_en : 1; 30 RK_U32 reserve0 : 3; 31 RK_U32 sw_dec_irq_dis : 1; 32 RK_U32 reserve1 : 3; 33 RK_U32 sw_dec_irq : 1; 34 RK_U32 reserve2 : 3; 35 RK_U32 sw_dec_rdy_int : 1; 36 RK_U32 sw_dec_bus_int : 1; 37 RK_U32 sw_dec_buffer_int : 1; 38 RK_U32 sw_dec_aso_int : 1; 39 RK_U32 sw_dec_error_int : 1; 40 RK_U32 sw_dec_slice_int : 1; 41 RK_U32 sw_dec_timeout : 1; 42 RK_U32 reserve3 : 5; 43 RK_U32 sw_dec_pic_inf : 1; 44 RK_U32 reserve4 : 7; 45 } SwReg01; 46 47 struct { 48 RK_U32 sw_dec_max_burst : 5; 49 RK_U32 sw_dec_scmd_dis : 1; 50 RK_U32 sw_dec_adv_pre_dis : 1; 51 RK_U32 sw_tiled_mode_lsb : 1; 52 RK_U32 sw_dec_out_endian : 1; 53 RK_U32 sw_dec_in_endian : 1; 54 RK_U32 sw_dec_clk_gate_e : 1; 55 RK_U32 sw_dec_latency : 6; 56 RK_U32 sw_tiled_mode_msb : 1; 57 RK_U32 sw_dec_data_disc_e : 1; 58 RK_U32 sw_dec_outswap32_e : 1; 59 RK_U32 sw_dec_inswap32_e : 1; 60 RK_U32 sw_dec_strendian_e : 1; 61 RK_U32 sw_dec_strswap32_e : 1; 62 RK_U32 sw_dec_timeout_e : 1; 63 RK_U32 sw_dec_axi_rd_id : 8; 64 } SwReg02; 65 66 struct { 67 RK_U32 sw_dec_axi_wr_id : 8; 68 RK_U32 reserve0 : 1; 69 RK_U32 sw_picord_count_e : 1; 70 RK_U32 sw_seq_mbaff_e : 1; 71 RK_U32 sw_reftopfirst_e : 1; 72 RK_U32 sw_write_mvs_e : 1; 73 RK_U32 sw_pic_fixed_quant : 1; 74 RK_U32 sw_filtering_dis : 1; 75 RK_U32 sw_dec_out_dis : 1; 76 RK_U32 sw_ref_topfield_e : 1; 77 RK_U32 sw_sorenson_e : 1; 78 RK_U32 sw_fwd_interlace_e : 1; 79 RK_U32 sw_pic_topfield_e : 1; 80 RK_U32 sw_pic_inter_e : 1; 81 RK_U32 sw_pic_b_e : 1; 82 RK_U32 sw_pic_fieldmode_e : 1; 83 RK_U32 sw_pic_interlace_e : 1; 84 RK_U32 sw_pjpeg_e : 1; 85 RK_U32 sw_divx3_e : 1; 86 RK_U32 sw_skip_mode : 1; 87 RK_U32 sw_rlc_mode_e : 1; 88 RK_U32 sw_dec_mode : 4; 89 } SwReg03; 90 91 struct { 92 RK_U32 sw_reserve0 : 5; 93 RK_U32 sw_topfieldfirst_e : 1; 94 RK_U32 sw_alt_scan_e : 1; 95 RK_U32 sw_mb_height_off : 4; 96 RK_U32 sw_pic_mb_hight_p : 8; 97 RK_U32 sw_mb_width_off : 4; 98 RK_U32 sw_pic_mb_width : 9; 99 } SwReg04; 100 101 struct { 102 RK_U32 sw_vop_time_incr : 16; 103 RK_U32 sw_intradc_vlc_thr : 3; 104 RK_U32 sw_ch_qp_offset : 5; 105 RK_U32 sw_type1_quant_e : 1; 106 RK_U32 sw_sync_markers_e : 1; 107 RK_U32 sw_strm_start_bit : 6; 108 } SwReg05; 109 110 struct { 111 RK_U32 sw_stream_len : 24; 112 RK_U32 sw_ch_8pix_ileav_e : 1; 113 RK_U32 sw_init_qp : 6; 114 RK_U32 sw_start_code_e : 1; 115 } SwReg06; 116 117 struct { 118 RK_U32 sw_framenum : 16; 119 RK_U32 sw_framenum_len : 5; 120 RK_U32 reserve0 : 5; 121 RK_U32 sw_weight_bipr_idc : 2; 122 RK_U32 sw_weight_pred_e : 1; 123 RK_U32 sw_dir_8x8_infer_e : 1; 124 RK_U32 sw_blackwhite_e : 1; 125 RK_U32 sw_cabac_e : 1; 126 } SwReg07; 127 128 struct { 129 RK_U32 sw_idr_pic_id : 16; 130 RK_U32 sw_idr_pic_e : 1; 131 RK_U32 sw_refpic_mk_len : 11; 132 RK_U32 sw_8x8trans_flag_e : 1; 133 RK_U32 sw_rdpic_cnt_pres : 1; 134 RK_U32 sw_filt_ctrl_pres : 1; 135 RK_U32 sw_const_intra_e : 1; 136 } SwReg08; 137 138 struct { 139 RK_U32 sw_poc_length : 8; 140 RK_U32 reserve0 : 6; 141 RK_U32 sw_refidx0_active : 5; 142 RK_U32 sw_refidx1_active : 5; 143 RK_U32 sw_pps_id : 8; 144 } SwReg09; 145 146 struct { 147 RK_U32 sw_diff_mv_base : 32; 148 } SwReg10; 149 150 RK_U32 SwReg11; 151 152 struct { 153 RK_U32 sw_rlc_vlc_base : 32; 154 } SwReg12; 155 156 struct { 157 RK_U32 dec_out_st_adr : 32; 158 } SwReg13; 159 160 /* MPP passes fd of reference frame to kernel 161 * with the whole register rather than higher 30-bit. 162 * At the same time, the lower 2-bit will be assigned 163 * by kernel. 164 * */ 165 struct { 166 //RK_U32 sw_refer0_topc_e : 1; 167 //RK_U32 sw_refer0_field_e : 1; 168 RK_U32 sw_refer0_base : 32; 169 } SwReg14; 170 171 struct { 172 //RK_U32 sw_refer1_topc_e : 1; 173 //RK_U32 sw_refer1_field_e : 1; 174 RK_U32 sw_refer1_base : 32; 175 } SwReg15; 176 177 struct { 178 //RK_U32 sw_refer2_topc_e : 1; 179 //RK_U32 sw_refer2_field_e : 1; 180 RK_U32 sw_refer2_base : 32; 181 } SwReg16; 182 183 struct { 184 //RK_U32 sw_refer3_topc_e : 1; 185 //RK_U32 sw_refer3_field_e : 1; 186 RK_U32 sw_refer3_base : 32; 187 } SwReg17; 188 189 struct { 190 RK_U32 sw_prev_anc_type : 1; 191 RK_U32 sw_mpeg4_vc1_rc : 1; 192 RK_U32 sw_mv_accuracy_fwd : 1; 193 RK_U32 sw_fcode_bwd_ver : 4; 194 RK_U32 sw_fcode_bwd_hor : 4; 195 RK_U32 sw_fcode_fwd_ver : 4; 196 RK_U32 sw_fcode_fwd_hor : 4; 197 RK_U32 sw_alt_scan_flag_e : 1; 198 RK_U32 reserve0 : 12; 199 } SwReg18; 200 201 struct { 202 //RK_U32 sw_refer5_topc_e : 1; 203 //RK_U32 sw_refer5_field_e : 1; 204 RK_U32 sw_refer5_base : 32; 205 } SwReg19; 206 207 struct { 208 //RK_U32 sw_refer6_topc_e : 1; 209 //RK_U32 sw_refer6_field_e : 1; 210 RK_U32 sw_refer6_base : 32; 211 } SwReg20; 212 213 struct { 214 //RK_U32 sw_refer7_topc_e : 1; 215 //RK_U32 sw_refer7_field_e : 1; 216 RK_U32 sw_refer7_base : 32; 217 } SwReg21; 218 219 220 RK_U32 SwReg22_33[12]; 221 222 struct { 223 RK_U32 reserve : 2; 224 RK_U32 sw_pred_bc_tap_1_1 : 10; 225 RK_U32 sw_pred_bc_tap_1_0 : 10; 226 RK_U32 sw_pred_bc_tap_0_3 : 10; 227 } SwReg34; 228 229 RK_U32 SwReg35_39[5]; 230 231 struct { 232 RK_U32 sw_qtable_base : 32; 233 } SwReg40; 234 235 struct { 236 RK_U32 sw_dir_mv_base : 32; 237 } SwReg41; 238 239 RK_U32 SwReg42_47[6]; 240 241 struct { 242 RK_U32 reserve0 : 15; 243 RK_U32 sw_startmb_y : 8; 244 RK_U32 sw_startmb_x : 9; 245 } SwReg48; 246 247 struct { 248 RK_U32 reserve0 : 2; 249 RK_U32 sw_pred_bc_tap_0_2 : 10; 250 RK_U32 sw_pred_bc_tap_0_1 : 10; 251 RK_U32 sw_pred_bc_tap_0_0 : 10; 252 } SwReg49; 253 254 RK_U32 SwReg50; 255 256 struct { 257 RK_U32 sw_refbu_y_offset : 9; 258 RK_U32 reserve0 : 3; 259 RK_U32 sw_refbu_fparmod_e : 1; 260 RK_U32 sw_refbu_eval_e : 1; 261 RK_U32 sw_refbu_picid : 5; 262 RK_U32 sw_refbu_thr : 12; 263 RK_U32 sw_refbu_e : 1; 264 } SwReg51; 265 266 RK_U32 SwReg52_54[3]; 267 268 struct { 269 RK_U32 sw_apf_threshold : 14; 270 RK_U32 reserve0 : 18; 271 } SwReg55; 272 273 RK_U32 SwReg56_100[45]; 274 } M4vdVdpu1Regs_t; 275 276 #endif /*__HAL_M4V_VDPU1_REG_TBL_H__*/ 277