1 /* 2 * 3 * Copyright 2015 Rockchip Electronics Co. LTD 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 /* 19 * @file hal_h265d_reg.h 20 * @brief 21 * @author csy(csy@rock-chips.com) 22 23 * @version 1.0.0 24 * @history 25 * 2015.7.15 : Create 26 */ 27 28 #ifndef __HAL_H265D_REG_H__ 29 #define __HAL_H265D_REG_H__ 30 31 #include "rk_type.h" 32 33 #define HEVC_DECODER_REG_NUM (48) 34 #define RKVDEC_REG_PERF_CYCLE_INDEX (64) 35 36 #define RKVDEC_HEVC_REGISTERS (68) 37 #define RKVDEC_V1_REGISTERS (78) 38 #define V345_HEVC_REGISTERS (108) 39 40 typedef struct RKV_HEVC_REG_END { 41 RK_U32 performance_cycle; //65 42 RK_U32 axi_ddr_rdata; 43 RK_U32 axi_ddr_wdata; 44 RK_U32 fpgadebug_reset; 45 RK_U32 reserve[9]; 46 RK_U32 extern_error_en; 47 } rkv_reg_end; 48 49 typedef struct V345_HEVC_REG_END { 50 struct hevc_mvc0 { 51 RK_U32 refp_layer_same_with_cur : 16 ; 52 RK_U32 reserve : 16 ; 53 } reg064_mvc0; 54 RK_U32 reserve[55]; 55 } v345_reg_end; 56 57 typedef struct { 58 struct swreg_id { 59 RK_U32 minor_ver : 8 ; 60 RK_U32 major_ver : 8 ; 61 RK_U32 prod_num : 16 ; 62 } sw_id; 63 64 struct swreg_int { 65 RK_U32 sw_dec_e : 1 ; 66 RK_U32 sw_dec_clkgate_e : 1 ; 67 RK_U32 reserve0 : 2 ; 68 RK_U32 sw_dec_irq_dis : 1 ; 69 RK_U32 sw_dec_timeout_e : 1 ; 70 RK_U32 sw_buf_empty_en : 1 ; 71 RK_U32 reserve1 : 1 ; 72 RK_U32 sw_dec_irq : 1 ; 73 RK_U32 sw_dec_irq_raw : 1 ; 74 RK_U32 reserve2 : 2 ; 75 RK_U32 sw_dec_rdy_sta : 1 ; 76 RK_U32 sw_dec_bus_sta : 1 ; 77 RK_U32 sw_dec_error_sta : 1 ; 78 RK_U32 sw_dec_timeout_sta : 1 ; 79 RK_U32 sw_dec_empty_sta : 1 ; 80 RK_U32 reserve4 : 3 ; 81 RK_U32 sw_softrst_en_p : 1 ; 82 RK_U32 sw_force_softreset_valid: 1 ; 83 RK_U32 sw_softreset_rdy : 1 ; 84 RK_U32 sw_wr_ddr_align_en : 1; 85 RK_U32 sw_scl_down_en : 1; 86 RK_U32 sw_allow_not_wr_unref_bframe : 1; 87 } sw_interrupt; ///<- zrh: do nothing in C Model 88 89 struct swreg_sysctrl { 90 RK_U32 sw_in_endian : 1 ; 91 RK_U32 sw_in_swap32_e : 1 ; 92 RK_U32 sw_in_swap64_e : 1 ; 93 RK_U32 sw_str_endian : 1 ; 94 RK_U32 sw_str_swap32_e : 1 ; 95 RK_U32 sw_str_swap64_e : 1 ; 96 RK_U32 sw_out_endian : 1 ; 97 RK_U32 sw_out_swap32_e : 1 ; 98 RK_U32 sw_out_cbcr_swap : 1 ; 99 RK_U32 sw_error_info_en : 1 ; 100 RK_U32 sw_rlc_mode_direct_write : 1; 101 RK_U32 sw_rlc_mode : 1 ; 102 RK_U32 sw_strm_start_bit : 7 ; 103 RK_U32 sw_inter_error_prc_mode : 1; 104 RK_U32 sw_dec_mode : 2 ; 105 RK_U32 sw_info_collect_en : 1 ; 106 RK_U32 sw_wait_reset_en : 1 ; 107 RK_U32 sw_h26x_rps_mode : 1 ; 108 RK_U32 reserve2 : 5 ; 109 RK_U32 sw_colmv_mode : 1 ; 110 RK_U32 sw_head_prior_high_en : 1; 111 } sw_sysctrl; 112 113 struct swreg_pic { 114 RK_U32 sw_y_hor_virstride : 9 ; 115 RK_U32 reserve : 3 ; 116 RK_U32 sw_uv_hor_virstride : 9 ; 117 RK_U32 sw_slice_num : 8 ; 118 } sw_picparameter; 119 120 RK_U32 sw_strm_rlc_base ;///<- zrh: do nothing in C Model 121 RK_U32 sw_stream_len ;///<- zrh: do nothing in C Model 122 RK_U32 sw_cabactbl_base ;///<- zrh: do nothing in C Model 123 RK_U32 sw_decout_base ; 124 RK_U32 sw_y_virstride ; 125 RK_U32 sw_yuv_virstride ; 126 RK_U32 sw_refer_base[15] ; 127 RK_S32 sw_refer_poc[15] ; 128 RK_S32 sw_cur_poc ; 129 RK_U32 sw_rlcwrite_base ;///<- zrh: do nothing in C Model 130 RK_U32 sw_pps_base ;///<- zrh: do nothing in C Model 131 RK_U32 sw_rps_base ;///<- zrh: do nothing in C Model 132 RK_U32 cabac_error_en ;///<- zrh add 133 RK_U32 cabac_error_status ;///<- zrh add 134 135 struct cabac_error_ctu { 136 RK_U32 sw_cabac_error_ctu_xoffset : 8; 137 RK_U32 sw_cabac_error_ctu_yoffset : 8; 138 RK_U32 sw_streamfifo_space2full : 7; 139 RK_U32 reversed0 : 9; 140 } cabac_error_ctu; 141 142 struct sao_ctu_position { 143 RK_U32 sw_saowr_xoffset : 9; 144 RK_U32 reversed0 : 7; 145 RK_U32 sw_saowr_yoffset : 10; 146 RK_U32 reversed1 : 6; 147 } sao_ctu_position; 148 149 RK_U32 reg_not_use0[RKVDEC_REG_PERF_CYCLE_INDEX - HEVC_DECODER_REG_NUM]; 150 union { 151 rkv_reg_end rkv_reg_ends; 152 v345_reg_end v345_reg_ends; 153 }; 154 } H265d_REGS_t; 155 156 #endif 157