1 /*
2 * Copyright 2020 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_h264d_vdpu34x"
18
19 #include <stdio.h>
20 #include <stdlib.h>
21 #include <string.h>
22
23 #include "rk_type.h"
24 #include "mpp_err.h"
25 #include "mpp_mem.h"
26 #include "mpp_common.h"
27 #include "mpp_bitput.h"
28
29 #include "mpp_device.h"
30
31 #include "hal_h264d_global.h"
32 #include "hal_h264d_vdpu34x.h"
33 #include "vdpu34x_h264d.h"
34 #include "mpp_dec_cb_param.h"
35
36 /* Number registers for the decoder */
37 #define DEC_VDPU34X_REGISTERS 276
38
39 #define VDPU34X_CABAC_TAB_SIZE (928*4 + 128) /* bytes */
40 #define VDPU34X_SPSPPS_SIZE (256*48 + 128) /* bytes */
41 #define VDPU34X_RPS_SIZE (128 + 128 + 128) /* bytes */
42 #define VDPU34X_SCALING_LIST_SIZE (6*16+2*64 + 128) /* bytes */
43 #define VDPU34X_ERROR_INFO_SIZE (256*144*4) /* bytes */
44 #define H264_CTU_SIZE 16
45
46 #define VDPU34X_CABAC_TAB_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_CABAC_TAB_SIZE, SZ_4K))
47 #define VDPU34X_ERROR_INFO_ALIGNED_SIZE (0)
48 #define VDPU34X_SPSPPS_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_SPSPPS_SIZE, SZ_4K))
49 #define VDPU34X_RPS_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_RPS_SIZE, SZ_4K))
50 #define VDPU34X_SCALING_LIST_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_SCALING_LIST_SIZE, SZ_4K))
51 #define VDPU34X_STREAM_INFO_SET_SIZE (VDPU34X_SPSPPS_ALIGNED_SIZE + \
52 VDPU34X_RPS_ALIGNED_SIZE + \
53 VDPU34X_SCALING_LIST_ALIGNED_SIZE)
54
55 #define VDPU34X_CABAC_TAB_OFFSET (0)
56 #define VDPU34X_ERROR_INFO_OFFSET (VDPU34X_CABAC_TAB_OFFSET + VDPU34X_CABAC_TAB_ALIGNED_SIZE)
57 #define VDPU34X_STREAM_INFO_OFFSET_BASE (VDPU34X_ERROR_INFO_OFFSET + VDPU34X_ERROR_INFO_ALIGNED_SIZE)
58 #define VDPU34X_SPSPPS_OFFSET(pos) (VDPU34X_STREAM_INFO_OFFSET_BASE + (VDPU34X_STREAM_INFO_SET_SIZE * pos))
59 #define VDPU34X_RPS_OFFSET(pos) (VDPU34X_SPSPPS_OFFSET(pos) + VDPU34X_SPSPPS_ALIGNED_SIZE)
60 #define VDPU34X_SCALING_LIST_OFFSET(pos) (VDPU34X_RPS_OFFSET(pos) + VDPU34X_RPS_ALIGNED_SIZE)
61 #define VDPU34X_INFO_BUFFER_SIZE(cnt) (VDPU34X_STREAM_INFO_OFFSET_BASE + (VDPU34X_STREAM_INFO_SET_SIZE * cnt))
62
63 #define VDPU34X_SPS_PPS_LEN (43)
64
65 #define SET_REF_INFO(regs, index, field, value)\
66 do{ \
67 switch(index){\
68 case 0: regs.reg99.ref0_##field = value; break;\
69 case 1: regs.reg99.ref1_##field = value; break;\
70 case 2: regs.reg99.ref2_##field = value; break;\
71 case 3: regs.reg99.ref3_##field = value; break;\
72 case 4: regs.reg100.ref4_##field = value; break;\
73 case 5: regs.reg100.ref5_##field = value; break;\
74 case 6: regs.reg100.ref6_##field = value; break;\
75 case 7: regs.reg100.ref7_##field = value; break;\
76 case 8: regs.reg101.ref8_##field = value; break;\
77 case 9: regs.reg101.ref9_##field = value; break;\
78 case 10: regs.reg101.ref10_##field = value; break;\
79 case 11: regs.reg101.ref11_##field = value; break;\
80 case 12: regs.reg102.ref12_##field = value; break;\
81 case 13: regs.reg102.ref13_##field = value; break;\
82 case 14: regs.reg102.ref14_##field = value; break;\
83 case 15: regs.reg102.ref15_##field = value; break;\
84 default: break;}\
85 }while(0)
86
87 #define SET_POC_HIGNBIT_INFO(regs, index, field, value)\
88 do{ \
89 switch(index){\
90 case 0: regs.reg200.ref0_##field = value; break;\
91 case 1: regs.reg200.ref1_##field = value; break;\
92 case 2: regs.reg200.ref2_##field = value; break;\
93 case 3: regs.reg200.ref3_##field = value; break;\
94 case 4: regs.reg200.ref4_##field = value; break;\
95 case 5: regs.reg200.ref5_##field = value; break;\
96 case 6: regs.reg200.ref6_##field = value; break;\
97 case 7: regs.reg200.ref7_##field = value; break;\
98 case 8: regs.reg201.ref8_##field = value; break;\
99 case 9: regs.reg201.ref9_##field = value; break;\
100 case 10: regs.reg201.ref10_##field = value; break;\
101 case 11: regs.reg201.ref11_##field = value; break;\
102 case 12: regs.reg201.ref12_##field = value; break;\
103 case 13: regs.reg201.ref13_##field = value; break;\
104 case 14: regs.reg201.ref14_##field = value; break;\
105 case 15: regs.reg201.ref15_##field = value; break;\
106 case 16: regs.reg202.ref16_##field = value; break;\
107 case 17: regs.reg202.ref17_##field = value; break;\
108 case 18: regs.reg202.ref18_##field = value; break;\
109 case 19: regs.reg202.ref19_##field = value; break;\
110 case 20: regs.reg202.ref20_##field = value; break;\
111 case 21: regs.reg202.ref21_##field = value; break;\
112 case 22: regs.reg202.ref22_##field = value; break;\
113 case 23: regs.reg202.ref23_##field = value; break;\
114 case 24: regs.reg203.ref24_##field = value; break;\
115 case 25: regs.reg203.ref25_##field = value; break;\
116 case 26: regs.reg203.ref26_##field = value; break;\
117 case 27: regs.reg203.ref27_##field = value; break;\
118 case 28: regs.reg203.ref28_##field = value; break;\
119 case 29: regs.reg203.ref29_##field = value; break;\
120 case 30: regs.reg203.ref30_##field = value; break;\
121 case 31: regs.reg203.ref31_##field = value; break;\
122 default: break;}\
123 }while(0)
124
125 #define VDPU34X_FAST_REG_SET_CNT 3
126
127 typedef struct h264d_rkv_buf_t {
128 RK_U32 valid;
129 Vdpu34xH264dRegSet *regs;
130 } H264dRkvBuf_t;
131
132 typedef struct Vdpu34xH264dRegCtx_t {
133 RK_U8 spspps[48];
134 RK_U8 rps[VDPU34X_RPS_SIZE];
135 RK_U8 sclst[VDPU34X_SCALING_LIST_SIZE];
136
137 MppBuffer bufs;
138 RK_S32 bufs_fd;
139 void *bufs_ptr;
140 RK_U32 offset_cabac;
141 RK_U32 offset_errinfo;
142 RK_U32 offset_spspps[VDPU34X_FAST_REG_SET_CNT];
143 RK_U32 offset_rps[VDPU34X_FAST_REG_SET_CNT];
144 RK_U32 offset_sclst[VDPU34X_FAST_REG_SET_CNT];
145
146 H264dRkvBuf_t reg_buf[VDPU34X_FAST_REG_SET_CNT];
147
148 RK_U32 spspps_offset;
149 RK_U32 rps_offset;
150 RK_U32 sclst_offset;
151
152 RK_S32 width;
153 RK_S32 height;
154 /* rcb buffers info */
155 RK_U32 bit_depth;
156 RK_U32 mbaff;
157 RK_U32 chroma_format_idc;
158
159 RK_S32 rcb_buf_size;
160 Vdpu34xRcbInfo rcb_info[RCB_BUF_COUNT];
161 MppBuffer rcb_buf[VDPU34X_FAST_REG_SET_CNT];
162
163 Vdpu34xH264dRegSet *regs;
164 } Vdpu34xH264dRegCtx;
165
166 const RK_U32 rkv_cabac_table_v34x[928] = {
167 0x3602f114, 0xf1144a03, 0x4a033602, 0x68e97fe4, 0x36ff35fa, 0x21173307,
168 0x00150217, 0x31000901, 0x390576db, 0x41f54ef3, 0x310c3e01, 0x321149fc,
169 0x2b094012, 0x431a001d, 0x68095a10, 0x68ec7fd2, 0x4ef34301, 0x3e0141f5,
170 0x5fef56fa, 0x2d093dfa, 0x51fa45fd, 0x370660f5, 0x56fb4307, 0x3a005802,
171 0x5ef64cfd, 0x45043605, 0x580051fd, 0x4afb43f9, 0x50fb4afc, 0x3a0148f9,
172 0x3f002900, 0x3f003f00, 0x560453f7, 0x48f96100, 0x3e03290d, 0x4efc2d00,
173 0x7ee560fd, 0x65e762e4, 0x52e443e9, 0x53f05eec, 0x5beb6eea, 0x5df366ee,
174 0x5cf97fe3, 0x60f959fb, 0x2efd6cf3, 0x39ff41ff, 0x4afd5df7, 0x57f85cf7,
175 0x36057ee9, 0x3b063c06, 0x30ff4506, 0x45fc4400, 0x55fe58f8, 0x4bff4efa,
176 0x36024df9, 0x44fd3205, 0x2a063201, 0x3f0151fc, 0x430046fc, 0x4cfe3902,
177 0x4004230b, 0x230b3d01, 0x180c1912, 0x240d1d0d, 0x49f95df6, 0x2e0d49fe,
178 0x64f93109, 0x35023509, 0x3dfe3505, 0x38003800, 0x3cfb3ff3, 0x39043eff,
179 0x390445fa, 0x3304270e, 0x4003440d, 0x3f093d01, 0x27103207, 0x34042c05,
180 0x3cfb300b, 0x3b003bff, 0x2c052116, 0x4eff2b0e, 0x45093c00, 0x28021c0b,
181 0x31002c03, 0x2c022e00, 0x2f003302, 0x3e022704, 0x36002e06, 0x3a023603,
182 0x33063f04, 0x35073906, 0x37063406, 0x240e2d0b, 0x52ff3508, 0x4efd3707,
183 0x1f162e0f, 0x071954ff, 0x031cf91e, 0x0020041c, 0x061eff22, 0x0920061e,
184 0x1b1a131f, 0x14251e1a, 0x4611221c, 0x3b054301, 0x1e104309, 0x23122012,
185 0x1f181d16, 0x2b122617, 0x3f0b2914, 0x40093b09, 0x59fe5eff, 0x4cfa6cf7,
186 0x2d002cfe, 0x40fd3400, 0x46fc3bfe, 0x52f84bfc, 0x4df766ef, 0x2a001803,
187 0x37003000, 0x47f93bfa, 0x57f553f4, 0x3a0177e2, 0x24ff1dfd, 0x2b022601,
188 0x3a0037fa, 0x4afd4000, 0x46005af6, 0x1f051dfc, 0x3b012a07, 0x48fd3afe,
189 0x61f551fd, 0x05083a00, 0x120e0e0a, 0x28021b0d, 0x46fd3a00, 0x55f84ffa,
190 0x6af30000, 0x57f66af0, 0x6eee72eb, 0x6eea62f2, 0x67ee6aeb, 0x6ce96beb,
191 0x60f670e6, 0x5bfb5ff4, 0x5eea5df7, 0x430956fb, 0x55f650fc, 0x3c0746ff,
192 0x3d053a09, 0x320f320c, 0x36113112, 0x2e07290a, 0x310733ff, 0x29093408,
193 0x37022f06, 0x2c0a290d, 0x35053206, 0x3f04310d, 0x45fe4006, 0x46063bfe,
194 0x1f092c0a, 0x35032b0c, 0x260a220e, 0x280d34fd, 0x2c072011, 0x320d2607,
195 0x2b1a390a, 0x0e0b0b0e, 0x0b120b09, 0xfe170915, 0xf120f120, 0xe927eb22,
196 0xe129df2a, 0xf426e42e, 0xe82d1d15, 0xe630d335, 0xed2bd541, 0x091ef627,
197 0x1b141a12, 0x52f23900, 0x61ed4bfb, 0x001b7ddd, 0xfc1f001c, 0x0822061b,
198 0x16180a1e, 0x20161321, 0x29151f1a, 0x2f172c1a, 0x470e4110, 0x3f063c08,
199 0x18154111, 0x171a1417, 0x171c201b, 0x2817181c, 0x1d1c2018, 0x39132a17,
200 0x3d163516, 0x280c560b, 0x3b0e330b, 0x47f94ffc, 0x46f745fb, 0x44f642f8,
201 0x45f449ed, 0x43f146f0, 0x46ed3eec, 0x41ea42f0, 0xfe093fec, 0xf721f71a,
202 0xfe29f927, 0x0931032d, 0x3b241b2d, 0x23f942fa, 0x2df82af9, 0x38f430fb,
203 0x3efb3cfa, 0x4cf842f8, 0x51fa55fb, 0x51f94df6, 0x49ee50ef, 0x53f64afc,
204 0x43f747f7, 0x42f83dff, 0x3b0042f2, 0xf3153b02, 0xf927f221, 0x0233fe2e,
205 0x113d063c, 0x3e2a2237, 0x00000000, 0x00000000, 0x3602f114, 0xf1144a03,
206 0x4a033602, 0x68e97fe4, 0x36ff35fa, 0x19163307, 0x00100022, 0x290409fe,
207 0x410276e3, 0x4ff347fa, 0x32093405, 0x360a46fd, 0x1613221a, 0x02390028,
208 0x451a2429, 0x65f17fd3, 0x47fa4cfc, 0x34054ff3, 0x5af34506, 0x2b083400,
209 0x52fb45fe, 0x3b0260f6, 0x57fd4b02, 0x380164fd, 0x55fa4afd, 0x51fd3b00,
210 0x5ffb56f9, 0x4dff42ff, 0x56fe4601, 0x3d0048fb, 0x3f002900, 0x3f003f00,
211 0x560453f7, 0x48f96100, 0x3e03290d, 0x33070f0d, 0x7fd95002, 0x60ef5bee,
212 0x62dd51e6, 0x61e966e8, 0x63e877e5, 0x66ee6eeb, 0x50007fdc, 0x5ef959fb,
213 0x27005cfc, 0x54f14100, 0x49fe7fdd, 0x5bf768f4, 0x37037fe1, 0x37073807,
214 0x35fd3d08, 0x4af94400, 0x67f358f7, 0x59f75bf3, 0x4cf85cf2, 0x6ee957f4,
215 0x4ef669e8, 0x63ef70ec, 0x7fba7fb2, 0x7fd27fce, 0x4efb42fc, 0x48f847fc,
216 0x37ff3b02, 0x4bfa46f9, 0x77de59f8, 0x14204bfd, 0x7fd4161e, 0x3dfb3600,
217 0x3cff3a00, 0x43f83dfd, 0x4af254e7, 0x340541fb, 0x3d003902, 0x46f545f7,
218 0x47fc3712, 0x3d073a00, 0x19122909, 0x2b052009, 0x2c002f09, 0x2e023300,
219 0x42fc2613, 0x2a0c260f, 0x59002209, 0x1c0a2d04, 0xf5211f0a, 0x0f12d534,
220 0xea23001c, 0x0022e726, 0xf420ee27, 0x0000a266, 0xfc21f138, 0xfb250a1d,
221 0xf727e333, 0xc645de34, 0xfb2cc143, 0xe3370720, 0x00000120, 0xe721241b,
222 0xe424e222, 0xe526e426, 0xf023ee22, 0xf820f222, 0x0023fa25, 0x121c0a1e,
223 0x291d191a, 0x48024b00, 0x230e4d08, 0x23111f12, 0x2d111e15, 0x2d122a14,
224 0x36101a1b, 0x38104207, 0x430a490b, 0x70e974f6, 0x3df947f1, 0x42fb3500,
225 0x50f74df5, 0x57f654f7, 0x65eb7fde, 0x35fb27fd, 0x4bf53df9, 0x5bef4df1,
226 0x6fe76be7, 0x4cf57ae4, 0x34f62cf6, 0x3af739f6, 0x45f948f0, 0x4afb45fc,
227 0x420256f7, 0x200122f7, 0x34051f0b, 0x43fe37fe, 0x59f84900, 0x04073403,
228 0x0811080a, 0x25031310, 0x49fb3dff, 0x4efc46ff, 0x7eeb0000, 0x6eec7ce9,
229 0x7ce77ee6, 0x79e569ef, 0x66ef75e5, 0x74e575e6, 0x5ff67adf, 0x5ff864f2,
230 0x72e46fef, 0x50fe59fa, 0x55f752fc, 0x48ff51f8, 0x43014005, 0x45003809,
231 0x45074501, 0x43fa45f9, 0x40fe4df0, 0x43fa3d02, 0x390240fd, 0x42fd41fd,
232 0x33093e00, 0x47fe42ff, 0x46ff4bfe, 0x3c0e48f7, 0x2f002510, 0x250b2312,
233 0x290a290c, 0x290c3002, 0x3b00290d, 0x28133203, 0x32124203, 0xfa12fa13,
234 0xf41a000e, 0xe721f01f, 0xe425ea21, 0xe22ae227, 0xdc2dd62f, 0xef29de31,
235 0xb9450920, 0xc042c13f, 0xd936b64d, 0xf629dd34, 0xff280024, 0x1a1c0e1e,
236 0x370c2517, 0xdf25410b, 0xdb28dc27, 0xdf2ee226, 0xe828e22a, 0xf426e331,
237 0xfd26f628, 0x141ffb2e, 0x2c191e1d, 0x310b300c, 0x16162d1a, 0x151b1617,
238 0x1c1a1421, 0x221b181e, 0x27192a12, 0x460c3212, 0x470e3615, 0x2019530b,
239 0x36153115, 0x51fa55fb, 0x51f94df6, 0x49ee50ef, 0x53f64afc, 0x43f747f7,
240 0x42f83dff, 0x3b0042f2, 0xf6113b02, 0xf72af320, 0x0035fb31, 0x0a440340,
241 0x392f1b42, 0x180047fb, 0x2afe24ff, 0x39f734fe, 0x41fc3ffa, 0x52f943fc,
242 0x4cfd51fd, 0x4efa48f9, 0x44f248f4, 0x4cfa46fd, 0x3efb42fb, 0x3dfc3900,
243 0x36013cf7, 0xf6113a02, 0xf72af320, 0x0035fb31, 0x0a440340, 0x392f1b42,
244 0x00000000, 0x00000000, 0x3602f114, 0xf1144a03, 0x4a033602, 0x68e97fe4,
245 0x36ff35fa, 0x101d3307, 0x000e0019, 0x3efd33f6, 0x101a63e5, 0x66e855fc,
246 0x39063905, 0x390e49ef, 0x0a142814, 0x0036001d, 0x610c2a25, 0x75ea7fe0,
247 0x55fc4afe, 0x390566e8, 0x58f25dfa, 0x37042cfa, 0x67f159f5, 0x391374eb,
248 0x54043a14, 0x3f016006, 0x6af355fb, 0x4b063f05, 0x65ff5afd, 0x4ffc3703,
249 0x61f44bfe, 0x3c0132f9, 0x3f002900, 0x3f003f00, 0x560453f7, 0x48f96100,
250 0x3e03290d, 0x58f72207, 0x7fdc7fec, 0x5ff25bef, 0x56e754e7, 0x5bef59f4,
251 0x4cf27fe1, 0x5af367ee, 0x500b7fdb, 0x54024c05, 0x37fa4e05, 0x53f23d04,
252 0x4ffb7fdb, 0x5bf568f5, 0x41007fe2, 0x48004ffe, 0x38fa5cfc, 0x47f84403,
253 0x56fc62f3, 0x52fb58f4, 0x43fc48fd, 0x59f048f8, 0x3bff45f7, 0x39044205,
254 0x47fe47fc, 0x4aff3a02, 0x45ff2cfc, 0x33f93e00, 0x2afa2ffc, 0x35fa29fd,
255 0x4ef74c08, 0x340953f5, 0x5afb4300, 0x48f14301, 0x50f84bfb, 0x40eb53eb,
256 0x40e71ff3, 0x4b095ee3, 0x4af83f11, 0x1bfe23fb, 0x41035b0d, 0x4d0845f9,
257 0x3e0342f6, 0x51ec44fd, 0x07011e00, 0x4aeb17fd, 0x7ce94210, 0xee2c2511,
258 0x7feade32, 0x2a002704, 0x1d0b2207, 0x25061f08, 0x28032a07, 0x2b0d2108,
259 0x2f04240d, 0x3a023703, 0x2c083c06, 0x2a0e2c0b, 0x38043007, 0x250d3404,
260 0x3a133109, 0x2d0c300a, 0x21144500, 0xee233f08, 0xfd1ce721, 0x001b0a18,
261 0xd434f222, 0x1113e827, 0x1d24191f, 0x0f222118, 0x4916141e, 0x1f132214,
262 0x10132c1b, 0x240f240f, 0x15191c15, 0x0c1f141e, 0x2a18101b, 0x380e5d00,
263 0x261a390f, 0x73e87fe8, 0x3ef752ea, 0x3b003500, 0x59f355f2, 0x5cf55ef3,
264 0x64eb7fe3, 0x43f439f2, 0x4df647f5, 0x58f055eb, 0x62f168e9, 0x52f67fdb,
265 0x3df830f8, 0x46f942f8, 0x4ff64bf2, 0x5cf453f7, 0x4ffc6cee, 0x4bf045ea,
266 0x3a013afe, 0x53f74ef3, 0x63f351fc, 0x26fa51f3, 0x3afa3ef3, 0x49f03bfe,
267 0x56f34cf6, 0x57f653f7, 0x7fea0000, 0x78e77fe7, 0x72ed7fe5, 0x76e775e9,
268 0x71e875e6, 0x78e176e4, 0x5ef67cdb, 0x63f666f1, 0x7fce6af3, 0x39115cfb,
269 0x5ef356fb, 0x4dfe5bf4, 0x49ff4700, 0x51f94004, 0x390f4005, 0x44004301,
270 0x440143f6, 0x40024d00, 0x4efb4400, 0x3b053707, 0x360e4102, 0x3c052c0f,
271 0x4cfe4602, 0x460c56ee, 0x46f44005, 0x3805370b, 0x41024500, 0x36054afa,
272 0x4cfa3607, 0x4dfe52f5, 0x2a194dfe, 0xf710f311, 0xeb1bf411, 0xd829e225,
273 0xd130d72a, 0xd82ee027, 0xd72ecd34, 0xed2bd934, 0xc93d0b20, 0xce3ed238,
274 0xec2dbd51, 0x0f1cfe23, 0x01270122, 0x2614111e, 0x360f2d12, 0xf0244f00,
275 0xef25f225, 0x0f220120, 0x19180f1d, 0x101f1622, 0x1c1f1223, 0x1c242921,
276 0x3e152f1b, 0x1a131f12, 0x17181824, 0x1e18101b, 0x29161d1f, 0x3c102a16,
277 0x3c0e340f, 0x7bf04e03, 0x38163515, 0x21153d19, 0x3d113213, 0x4af84efd,
278 0x48f648f7, 0x47f44bee, 0x46fb3ff5, 0x48f24bef, 0x35f843f0, 0x34f73bf2,
279 0xfe0944f5, 0xfc1ff61e, 0x0721ff21, 0x17250c1f, 0x4014261f, 0x25f947f7,
280 0x31f52cf8, 0x3bf438f6, 0x43f73ff8, 0x4ff644fa, 0x4af84efd, 0x48f648f7,
281 0x47f44bee, 0x46fb3ff5, 0x48f24bef, 0x35f843f0, 0x34f73bf2, 0xfe0944f5,
282 0xfc1ff61e, 0x0721ff21, 0x17250c1f, 0x4014261f, 0x00000000, 0x00000000,
283 0x3602f114, 0xf1144a03, 0x4a033602, 0x68e97fe4, 0x36ff35fa, 0x00003307,
284 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
285 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
286 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
287 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
288 0x3f002900, 0x3f003f00, 0x560453f7, 0x48f96100, 0x3e03290d, 0x37010b00,
289 0x7fef4500, 0x520066f3, 0x6beb4af9, 0x7fe17fe5, 0x5fee7fe8, 0x72eb7fe5,
290 0x7bef7fe2, 0x7af073f4, 0x3ff473f5, 0x54f144fe, 0x46fd68f3, 0x5af65df8,
291 0x4aff7fe2, 0x5bf961fa, 0x38fc7fec, 0x4cf952fb, 0x5df97dea, 0x4dfd57f5,
292 0x3ffc47fb, 0x54f444fc, 0x41f93ef9, 0x38053d08, 0x400142fe, 0x4efe3d00,
293 0x34073201, 0x2c00230a, 0x2d01260b, 0x2c052e00, 0x3301111f, 0x131c3207,
294 0x3e0e2110, 0x64f16cf3, 0x5bf365f3, 0x58f65ef4, 0x56f654f0, 0x57f353f9,
295 0x46015eed, 0x4afb4800, 0x66f83b12, 0x5f0064f1, 0x48024bfc, 0x47fd4bf5,
296 0x45f32e0f, 0x41003e00, 0x48f12515, 0x36103909, 0x480c3e00, 0x090f0018,
297 0x120d1908, 0x130d090f, 0x120c250a, 0x21141d06, 0x2d041e0f, 0x3e003a01,
298 0x260c3d07, 0x270f2d0b, 0x2c0d2a0b, 0x290c2d10, 0x221e310a, 0x370a2a12,
299 0x2e113311, 0xed1a5900, 0xef1aef16, 0xec1ce71e, 0xe525e921, 0xe428e921,
300 0xf521ef26, 0xfa29f128, 0x11290126, 0x031bfa1e, 0xf025161a, 0xf826fc23,
301 0x0325fd26, 0x002a0526, 0x16271023, 0x251b300e, 0x440c3c15, 0x47fd6102,
302 0x32fb2afa, 0x3efe36fd, 0x3f013a00, 0x4aff48fe, 0x43fb5bf7, 0x27fd1bfb,
303 0x2e002cfe, 0x44f840f0, 0x4dfa4ef6, 0x5cf456f6, 0x3cf637f1, 0x41fc3efa,
304 0x4cf849f4, 0x58f750f9, 0x61f56eef, 0x4ff554ec, 0x4afc49fa, 0x60f356f3,
305 0x75ed61f5, 0x21fb4ef8, 0x35fe30fc, 0x47f33efd, 0x56f44ff6, 0x61f25af3,
306 0x5dfa0000, 0x4ff854fa, 0x47ff4200, 0x3cfe3e00, 0x4bfb3bfe, 0x3afc3efd,
307 0x4fff42f7, 0x44034700, 0x3ef92c0a, 0x280e240f, 0x1d0c1b10, 0x24142c01,
308 0x2a052012, 0x3e0a3001, 0x40092e11, 0x61f568f4, 0x58f960f0, 0x55f955f8,
309 0x58f355f7, 0x4dfd4204, 0x4cfa4cfd, 0x4cff3a0a, 0x63f953ff, 0x5f025ff2,
310 0x4afb4c00, 0x4bf54600, 0x41004401, 0x3e0349f2, 0x44ff3e04, 0x370b4bf3,
311 0x460c4005, 0x1306060f, 0x0e0c1007, 0x0b0d0d12, 0x100f0f0d, 0x170d170c,
312 0x1a0e140f, 0x28112c0e, 0x11182f11, 0x16191515, 0x1d161b1f, 0x320e2313,
313 0x3f07390a, 0x52fc4dfe, 0x45095efd, 0xdd246df4, 0xe620de24, 0xe02ce225,
314 0xf122ee22, 0xf921f128, 0x0021fb23, 0x0d210226, 0x3a0d2317, 0x001afd1d,
315 0xf91f1e16, 0xfd22f123, 0xff240322, 0x0b200522, 0x0c220523, 0x1d1e0b27,
316 0x271d1a22, 0x151f4213, 0x32191f1f, 0x70ec78ef, 0x55f572ee, 0x59f25cf1,
317 0x51f147e6, 0x440050f2, 0x38e846f2, 0x32e844e9, 0xf3174af5, 0xf128f31a,
318 0x032cf231, 0x222c062d, 0x52133621, 0x17ff4bfd, 0x2b012201, 0x37fe3600,
319 0x40013d00, 0x5cf74400, 0x61f36af2, 0x5af45af1, 0x49f658ee, 0x56f24ff7,
320 0x46f649f6, 0x42fb45f6, 0x3afb40f7, 0xf6153b02, 0xf81cf518, 0x031dff1c,
321 0x1423091d, 0x430e241d, 0x00000000, 0x00000000
322 };
323
324 MPP_RET vdpu34x_h264d_deinit(void *hal);
rkv_ver_align(RK_U32 val)325 static RK_U32 rkv_ver_align(RK_U32 val)
326 {
327 return MPP_ALIGN(val, 16);
328 }
329
rkv_hor_align(RK_U32 val)330 static RK_U32 rkv_hor_align(RK_U32 val)
331 {
332 return MPP_ALIGN(val, 16);
333 }
334
rkv_hor_align_256_odds(RK_U32 val)335 static RK_U32 rkv_hor_align_256_odds(RK_U32 val)
336 {
337 return (MPP_ALIGN(val, 256) | 256);
338 }
339
rkv_len_align(RK_U32 val)340 static RK_U32 rkv_len_align(RK_U32 val)
341 {
342 return (2 * MPP_ALIGN(val, 16));
343 }
344
rkv_len_align_422(RK_U32 val)345 static RK_U32 rkv_len_align_422(RK_U32 val)
346 {
347 return ((5 * MPP_ALIGN(val, 16)) / 2);
348 }
349
prepare_spspps(H264dHalCtx_t * p_hal,RK_U64 * data,RK_U32 len)350 static MPP_RET prepare_spspps(H264dHalCtx_t *p_hal, RK_U64 *data, RK_U32 len)
351 {
352 RK_S32 i = 0;
353 RK_S32 is_long_term = 0, voidx = 0;
354 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
355 RK_U32 tmp = 0;
356 BitputCtx_t bp;
357
358 mpp_set_bitput_ctx(&bp, data, len);
359
360 if (!p_hal->fast_mode && !pp->spspps_update) {
361 bp.index = VDPU34X_SPS_PPS_LEN >> 3;
362 bp.bitpos = (VDPU34X_SPS_PPS_LEN & 0x7) << 3;
363 } else {
364 //!< sps syntax
365 mpp_put_bits(&bp, -1, 13); //!< sps_id 4bit && profile_idc 8bit && constraint_set3_flag 1bit
366 mpp_put_bits(&bp, pp->chroma_format_idc, 2);
367 mpp_put_bits(&bp, pp->bit_depth_luma_minus8, 3);
368 mpp_put_bits(&bp, pp->bit_depth_chroma_minus8, 3);
369 mpp_put_bits(&bp, 0, 1); //!< qpprime_y_zero_transform_bypass_flag
370 mpp_put_bits(&bp, pp->log2_max_frame_num_minus4, 4);
371 mpp_put_bits(&bp, pp->num_ref_frames, 5);
372 mpp_put_bits(&bp, pp->pic_order_cnt_type, 2);
373 mpp_put_bits(&bp, pp->log2_max_pic_order_cnt_lsb_minus4, 4);
374 mpp_put_bits(&bp, pp->delta_pic_order_always_zero_flag, 1);
375 mpp_put_bits(&bp, (pp->wFrameWidthInMbsMinus1 + 1), 12);
376 mpp_put_bits(&bp, (pp->wFrameHeightInMbsMinus1 + 1), 12);
377 mpp_put_bits(&bp, pp->frame_mbs_only_flag, 1);
378 mpp_put_bits(&bp, pp->MbaffFrameFlag, 1);
379 mpp_put_bits(&bp, pp->direct_8x8_inference_flag, 1);
380
381 mpp_put_bits(&bp, 1, 1); //!< mvc_extension_enable
382 mpp_put_bits(&bp, (pp->num_views_minus1 + 1), 2);
383 mpp_put_bits(&bp, pp->view_id[0], 10);
384 mpp_put_bits(&bp, pp->view_id[1], 10);
385 mpp_put_bits(&bp, pp->num_anchor_refs_l0[0], 1);
386 if (pp->num_anchor_refs_l0[0]) {
387 mpp_put_bits(&bp, pp->anchor_ref_l0[0][0], 10);
388 } else {
389 mpp_put_bits(&bp, 0, 10);
390 }
391 mpp_put_bits(&bp, pp->num_anchor_refs_l1[0], 1);
392 if (pp->num_anchor_refs_l1[0]) {
393 mpp_put_bits(&bp, pp->anchor_ref_l1[0][0], 10);
394 } else {
395 mpp_put_bits(&bp, 0, 10); //!< anchor_ref_l1
396 }
397 mpp_put_bits(&bp, pp->num_non_anchor_refs_l0[0], 1);
398 if (pp->num_non_anchor_refs_l0[0]) {
399 mpp_put_bits(&bp, pp->non_anchor_ref_l0[0][0], 10);
400 } else {
401 mpp_put_bits(&bp, 0, 10); //!< non_anchor_ref_l0
402 }
403 mpp_put_bits(&bp, pp->num_non_anchor_refs_l1[0], 1);
404 if (pp->num_non_anchor_refs_l1[0]) {
405 mpp_put_bits(&bp, pp->non_anchor_ref_l1[0][0], 10);
406 } else {
407 mpp_put_bits(&bp, 0, 10);//!< non_anchor_ref_l1
408 }
409 mpp_put_align(&bp, 128, 0);
410 //!< pps syntax
411 mpp_put_bits(&bp, -1, 13); //!< pps_id 8bit && sps_id 5bit
412 mpp_put_bits(&bp, pp->entropy_coding_mode_flag, 1);
413 mpp_put_bits(&bp, pp->pic_order_present_flag, 1);
414 mpp_put_bits(&bp, pp->num_ref_idx_l0_active_minus1, 5);
415 mpp_put_bits(&bp, pp->num_ref_idx_l1_active_minus1, 5);
416 mpp_put_bits(&bp, pp->weighted_pred_flag, 1);
417 mpp_put_bits(&bp, pp->weighted_bipred_idc, 2);
418 mpp_put_bits(&bp, pp->pic_init_qp_minus26, 7);
419 mpp_put_bits(&bp, pp->pic_init_qs_minus26, 6);
420 mpp_put_bits(&bp, pp->chroma_qp_index_offset, 5);
421 mpp_put_bits(&bp, pp->deblocking_filter_control_present_flag, 1);
422 mpp_put_bits(&bp, pp->constrained_intra_pred_flag, 1);
423 mpp_put_bits(&bp, pp->redundant_pic_cnt_present_flag, 1);
424 mpp_put_bits(&bp, pp->transform_8x8_mode_flag, 1);
425 mpp_put_bits(&bp, pp->second_chroma_qp_index_offset, 5);
426 mpp_put_bits(&bp, pp->scaleing_list_enable_flag, 1);
427 mpp_put_bits(&bp, 0, 32);// scanlist buffer has another addr
428 }
429
430 //!< set dpb
431 for (i = 0; i < 16; i++) {
432 is_long_term = (pp->RefFrameList[i].bPicEntry != 0xff) ? pp->RefFrameList[i].AssociatedFlag : 0;
433 tmp |= (RK_U32)(is_long_term & 0x1) << i;
434 }
435 for (i = 0; i < 16; i++) {
436 voidx = (pp->RefFrameList[i].bPicEntry != 0xff) ? pp->RefPicLayerIdList[i] : 0;
437 tmp |= (RK_U32)(voidx & 0x1) << (i + 16);
438 }
439 mpp_put_bits(&bp, tmp, 32);
440 mpp_put_align(&bp, 64, 0);
441
442 return MPP_OK;
443 }
444
prepare_framerps(H264dHalCtx_t * p_hal,RK_U64 * data,RK_U32 len)445 static MPP_RET prepare_framerps(H264dHalCtx_t *p_hal, RK_U64 *data, RK_U32 len)
446 {
447 RK_S32 i = 0, j = 0;
448 RK_S32 dpb_idx = 0, voidx = 0;
449 RK_S32 dpb_valid = 0, bottom_flag = 0;
450 RK_U32 max_frame_num = 0;
451 RK_U16 frame_num_wrap = 0;
452 RK_U32 tmp = 0;
453
454 BitputCtx_t bp;
455 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
456
457 mpp_set_bitput_ctx(&bp, data, len);
458 mpp_put_align(&bp, 128, 0);
459 max_frame_num = 1 << (pp->log2_max_frame_num_minus4 + 4);
460 for (i = 0; i < 16; i++) {
461 if ((pp->NonExistingFrameFlags >> i) & 0x01) {
462 frame_num_wrap = 0;
463 } else {
464 if (pp->RefFrameList[i].AssociatedFlag) {
465 frame_num_wrap = pp->FrameNumList[i];
466 } else {
467 frame_num_wrap = (pp->FrameNumList[i] > pp->frame_num) ?
468 (pp->FrameNumList[i] - max_frame_num) : pp->FrameNumList[i];
469 }
470 }
471
472 mpp_put_bits(&bp, frame_num_wrap, 16);
473 }
474
475 mpp_put_bits(&bp, 0, 16);//!< NULL
476 tmp = 0;
477 for (i = 0; i < 16; i++) {
478 tmp |= (RK_U32)pp->RefPicLayerIdList[i] << i;
479 }
480 mpp_put_bits(&bp, tmp, 16);
481
482 for (i = 0; i < 32; i++) {
483 tmp = 0;
484 dpb_valid = (p_hal->slice_long[0].RefPicList[0][i].bPicEntry == 0xff) ? 0 : 1;
485 dpb_idx = dpb_valid ? p_hal->slice_long[0].RefPicList[0][i].Index7Bits : 0;
486 bottom_flag = dpb_valid ? p_hal->slice_long[0].RefPicList[0][i].AssociatedFlag : 0;
487 voidx = dpb_valid ? pp->RefPicLayerIdList[dpb_idx] : 0;
488 tmp |= (RK_U32)(dpb_idx | (dpb_valid << 4)) & 0x1f;
489 tmp |= (RK_U32)(bottom_flag & 0x1) << 5;
490 tmp |= (RK_U32)(voidx & 0x1) << 6;
491 mpp_put_bits(&bp, tmp, 7);
492 }
493 for (j = 1; j < 3; j++) {
494 for (i = 0; i < 32; i++) {
495 tmp = 0;
496 dpb_valid = (p_hal->slice_long[0].RefPicList[j][i].bPicEntry == 0xff) ? 0 : 1;
497 dpb_idx = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].Index7Bits : 0;
498 bottom_flag = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].AssociatedFlag : 0;
499 voidx = dpb_valid ? pp->RefPicLayerIdList[dpb_idx] : 0;
500 tmp |= (RK_U32)(dpb_idx | (dpb_valid << 4)) & 0x1f;
501 tmp |= (RK_U32)(bottom_flag & 0x1) << 5;
502 tmp |= (RK_U32)(voidx & 0x1) << 6;
503 mpp_put_bits(&bp, tmp, 7);
504 }
505 }
506 mpp_put_align(&bp, 128, 0);
507
508 return MPP_OK;
509 }
510
prepare_scanlist(H264dHalCtx_t * p_hal,RK_U8 * data,RK_U32 len)511 static MPP_RET prepare_scanlist(H264dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
512 {
513 RK_U32 i = 0, j = 0, n = 0;
514
515 if (p_hal->pp->scaleing_list_enable_flag) {
516 for (i = 0; i < 6; i++) { //!< 4x4, 6 lists
517 for (j = 0; j < 16; j++) {
518 data[n++] = p_hal->qm->bScalingLists4x4[i][j];
519 }
520 }
521 for (i = 0; i < 2; i++) { //!< 8x8, 2 lists
522 for (j = 0; j < 64; j++) {
523 data[n++] = p_hal->qm->bScalingLists8x8[i][j];
524 }
525 }
526 }
527 mpp_assert(n <= len);
528
529 return MPP_OK;
530 }
531
set_registers(H264dHalCtx_t * p_hal,Vdpu34xH264dRegSet * regs,HalTaskInfo * task)532 static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, HalTaskInfo *task)
533 {
534 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
535 Vdpu34xRegCommon *common = ®s->common;
536 HalBuf *mv_buf = NULL;
537
538 // memset(regs, 0, sizeof(Vdpu34xH264dRegSet));
539 memset(®s->h264d_highpoc, 0, sizeof(regs->h264d_highpoc));
540 common->reg016_str_len = p_hal->strm_len;
541 common->reg013.cur_pic_is_idr = p_hal->slice_long->idr_flag;
542 common->reg012.colmv_compress_en = (pp->frame_mbs_only_flag) ? 1 : 0;
543 common->reg028.sw_poc_arb_flag = 0;
544
545 /* caculate the yuv_frame_size */
546 {
547 MppFrame mframe = NULL;
548 RK_U32 hor_virstride = 0;
549 RK_U32 ver_virstride = 0;
550 RK_U32 y_virstride = 0;
551
552 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe);
553 hor_virstride = mpp_frame_get_hor_stride(mframe);
554 ver_virstride = mpp_frame_get_ver_stride(mframe);
555 y_virstride = hor_virstride * ver_virstride;
556
557 if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
558 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
559 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K);
560
561 common->reg012.fbc_e = 1;
562 common->reg018.y_hor_virstride = fbc_hdr_stride / 16;
563 common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;
564 common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
565 } else {
566 common->reg012.fbc_e = 0;
567 common->reg018.y_hor_virstride = hor_virstride / 16;
568 common->reg019.uv_hor_virstride = hor_virstride / 16;
569 common->reg020_y_virstride.y_virstride = y_virstride / 16;
570 }
571 }
572 /* set current frame info */
573 {
574 MppBuffer mbuffer = NULL;
575 RK_S32 fd = -1;
576
577 regs->h264d_param.reg65.cur_top_poc = pp->CurrFieldOrderCnt[0];
578 regs->h264d_param.reg66.cur_bot_poc = pp->CurrFieldOrderCnt[1];
579 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &mbuffer);
580 fd = mpp_buffer_get_fd(mbuffer);
581 regs->common_addr.reg130_decout_base = fd;
582
583 //colmv_cur_base
584 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, pp->CurrPic.Index7Bits);
585 regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
586 regs->common_addr.reg132_error_ref_base = fd;
587 /*
588 * poc_hight bit[0] :
589 * 0 -> top field or frame
590 * 1 -> bot field
591 */
592 if (pp->field_pic_flag)
593 regs->h264d_highpoc.reg204.cur_poc_highbit = pp->CurrPic.AssociatedFlag;
594 else
595 regs->h264d_highpoc.reg204.cur_poc_highbit = 0;
596 }
597 /* set reference info */
598 {
599 RK_S32 i = 0;
600 RK_S32 ref_index = -1;
601 RK_S32 near_index = -1;
602 MppBuffer mbuffer = NULL;
603 RK_U32 min_frame_num = 0;
604 MppFrame mframe = NULL;
605
606 for (i = 0; i <= 15; i++) {
607 RK_U32 field_flag = (pp->RefPicFiledFlags >> i) & 0x01;
608 RK_U32 top_used = (pp->UsedForReferenceFlags >> (2 * i + 0)) & 0x01;
609 RK_U32 bot_used = (pp->UsedForReferenceFlags >> (2 * i + 1)) & 0x01;
610
611 regs->h264d_param.reg67_98_ref_poc[2 * i] = pp->FieldOrderCntList[i][0];
612 regs->h264d_param.reg67_98_ref_poc[2 * i + 1] = pp->FieldOrderCntList[i][1];
613 SET_REF_INFO(regs->h264d_param, i, field, field_flag);
614 SET_REF_INFO(regs->h264d_param, i, topfield_used, top_used);
615 SET_REF_INFO(regs->h264d_param, i, botfield_used, bot_used);
616 SET_REF_INFO(regs->h264d_param, i, colmv_use_flag, (pp->RefPicColmvUsedFlags >> i) & 0x01);
617
618 if (pp->RefFrameList[i].bPicEntry != 0xff) {
619 ref_index = pp->RefFrameList[i].Index7Bits;
620 near_index = pp->RefFrameList[i].Index7Bits;
621 } else {
622 ref_index = (near_index < 0) ? pp->CurrPic.Index7Bits : near_index;
623 }
624
625 if (pp->field_pic_flag) {
626 SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i, poc_highbit, 0);
627 SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i + 1, poc_highbit, 1);
628 } else if (ref_index == pp->CurrPic.Index7Bits) {
629 SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i, poc_highbit, 3);
630 SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i + 1, poc_highbit, 3);
631 }
632
633 mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer);
634 mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_FRAME_PTR, &mframe);
635
636 if (pp->FrameNumList[i] < pp->frame_num &&
637 pp->FrameNumList[i] > min_frame_num &&
638 (!mpp_frame_get_errinfo(mframe))) {
639 min_frame_num = pp->FrameNumList[i];
640 regs->common_addr.reg132_error_ref_base = mpp_buffer_get_fd(mbuffer);
641 if (!pp->weighted_pred_flag)
642 common->reg021.error_intra_mode = 0;
643 }
644
645 regs->h264d_addr.ref_base[i] = mpp_buffer_get_fd(mbuffer);
646 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, ref_index);
647 regs->h264d_addr.colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
648 }
649 }
650 /* set input */
651 {
652 MppBuffer mbuffer = NULL;
653 Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;
654
655 mpp_buf_slot_get_prop(p_hal->packet_slots, task->dec.input, SLOT_BUFFER, &mbuffer);
656 regs->common_addr.reg128_rlc_base = mpp_buffer_get_fd(mbuffer);
657 regs->common_addr.reg129_rlcwrite_base = regs->common_addr.reg128_rlc_base;
658
659 regs->h264d_addr.cabactbl_base = reg_ctx->bufs_fd;
660 mpp_dev_set_reg_offset(p_hal->dev, 197, reg_ctx->offset_cabac);
661 }
662
663 return MPP_OK;
664 }
665
init_common_regs(Vdpu34xH264dRegSet * regs)666 static MPP_RET init_common_regs(Vdpu34xH264dRegSet *regs)
667 {
668 Vdpu34xRegCommon *common = ®s->common;
669
670 common->reg009.dec_mode = 1; //!< h264
671 common->reg015.rlc_mode = 0;
672
673 common->reg011.buf_empty_en = 1;
674 common->reg011.dec_timeout_e = 1;
675
676 common->reg010.dec_e = 1;
677 common->reg017.slice_num = 0x3fff;
678
679 common->reg012.wait_reset_en = 1;
680 common->reg013.h26x_error_mode = 1;
681 common->reg013.colmv_error_mode = 1;
682 common->reg013.h26x_streamd_error_mode = 1;
683 common->reg021.error_deb_en = 1;
684 common->reg021.inter_error_prc_mode = 0;
685 common->reg021.error_intra_mode = 1;
686
687 if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3588) {
688 common->reg024.cabac_err_en_lowbits = 0;
689 common->reg025.cabac_err_en_highbits = 0;
690 common->reg026.swreg_block_gating_e = 0xfffef;
691 } else {
692 common->reg024.cabac_err_en_lowbits = 0xffffffff;
693 common->reg025.cabac_err_en_highbits = 0x3ff3ffff;
694 common->reg026.swreg_block_gating_e = 0xfffff;
695 }
696 common->reg026.reg_cfg_gating_en = 1;
697 common->reg032_timeout_threshold = 0x3ffff;
698
699 common->reg011.dec_clkgate_e = 1;
700 common->reg011.dec_e_strmd_clkgate_dis = 0;
701 common->reg011.dec_timeout_e = 1;
702
703 common->reg013.timeout_mode = 1;
704
705 return MPP_OK;
706 }
707
vdpu34x_h264d_init(void * hal,MppHalCfg * cfg)708 MPP_RET vdpu34x_h264d_init(void *hal, MppHalCfg *cfg)
709 {
710 MPP_RET ret = MPP_ERR_UNKNOW;
711 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
712
713 INP_CHECK(ret, NULL == p_hal);
714
715 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu34xH264dRegCtx)));
716 Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;
717 RK_U32 max_cnt = p_hal->fast_mode ? VDPU34X_FAST_REG_SET_CNT : 1;
718 RK_U32 i = 0;
719
720 //!< malloc buffers
721 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, ®_ctx->bufs,
722 VDPU34X_INFO_BUFFER_SIZE(max_cnt)));
723 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs);
724 reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs);
725 reg_ctx->offset_cabac = VDPU34X_CABAC_TAB_OFFSET;
726 reg_ctx->offset_errinfo = VDPU34X_ERROR_INFO_OFFSET;
727 for (i = 0; i < max_cnt; i++) {
728 reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu34xH264dRegSet, 1);
729 init_common_regs(reg_ctx->reg_buf[i].regs);
730 reg_ctx->offset_spspps[i] = VDPU34X_SPSPPS_OFFSET(i);
731 reg_ctx->offset_rps[i] = VDPU34X_RPS_OFFSET(i);
732 reg_ctx->offset_sclst[i] = VDPU34X_SCALING_LIST_OFFSET(i);
733 }
734
735 if (!p_hal->fast_mode) {
736 reg_ctx->regs = reg_ctx->reg_buf[0].regs;
737 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0];
738 reg_ctx->rps_offset = reg_ctx->offset_rps[0];
739 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0];
740 }
741
742 //!< copy cabac table bytes
743 memcpy((char *)reg_ctx->bufs_ptr + reg_ctx->offset_cabac,
744 (void *)rkv_cabac_table_v34x, sizeof(rkv_cabac_table_v34x));
745
746 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, rkv_hor_align);
747 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align);
748 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align);
749
750 if (cfg->hal_fbc_adj_cfg) {
751 cfg->hal_fbc_adj_cfg->func = vdpu34x_afbc_align_calc;
752 cfg->hal_fbc_adj_cfg->expand = 16;
753 }
754
755 __RETURN:
756 return MPP_OK;
757 __FAILED:
758 vdpu34x_h264d_deinit(hal);
759
760 return ret;
761 }
762
vdpu34x_h264d_deinit(void * hal)763 MPP_RET vdpu34x_h264d_deinit(void *hal)
764 {
765 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
766 Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;
767
768 RK_U32 i = 0;
769 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
770
771 mpp_buffer_put(reg_ctx->bufs);
772
773 for (i = 0; i < loop; i++)
774 MPP_FREE(reg_ctx->reg_buf[i].regs);
775
776 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->rcb_buf) : 1;
777 for (i = 0; i < loop; i++) {
778 if (reg_ctx->rcb_buf[i]) {
779 mpp_buffer_put(reg_ctx->rcb_buf[i]);
780 reg_ctx->rcb_buf[i] = NULL;
781 }
782 }
783
784 if (p_hal->cmv_bufs) {
785 hal_bufs_deinit(p_hal->cmv_bufs);
786 p_hal->cmv_bufs = NULL;
787 }
788
789 MPP_FREE(p_hal->reg_ctx);
790
791 return MPP_OK;
792 }
793
h264d_refine_rcb_size(H264dHalCtx_t * p_hal,Vdpu34xRcbInfo * rcb_info,Vdpu34xH264dRegSet * regs,RK_S32 width,RK_S32 height)794 static void h264d_refine_rcb_size(H264dHalCtx_t *p_hal, Vdpu34xRcbInfo *rcb_info,
795 Vdpu34xH264dRegSet *regs,
796 RK_S32 width, RK_S32 height)
797 {
798 RK_U32 rcb_bits = 0;
799 RK_U32 mbaff = p_hal->pp->MbaffFrameFlag;
800 RK_U32 bit_depth = p_hal->pp->bit_depth_luma_minus8 + 8;
801 RK_U32 chroma_format_idc = p_hal->pp->chroma_format_idc;
802
803 width = MPP_ALIGN(width, H264_CTU_SIZE);
804 height = MPP_ALIGN(height, H264_CTU_SIZE);
805 /* RCB_STRMD_ROW */
806 if (width > 4096)
807 rcb_bits = ((width + 15) / 16) * 154 * (mbaff ? 2 : 1);
808 else
809 rcb_bits = 0;
810 rcb_info[RCB_STRMD_ROW].size = MPP_RCB_BYTES(rcb_bits);
811 /* RCB_TRANSD_ROW */
812 if (width > 8192)
813 rcb_bits = ((width - 8192 + 3) / 4) * 2;
814 else
815 rcb_bits = 0;
816 rcb_info[RCB_TRANSD_ROW].size = MPP_RCB_BYTES(rcb_bits);
817 /* RCB_TRANSD_COL */
818 if (height > 8192)
819 rcb_bits = ((height - 8192 + 3) / 4) * 2;
820 else
821 rcb_bits = 0;
822 rcb_info[RCB_TRANSD_COL].size = MPP_RCB_BYTES(rcb_bits);
823 /* RCB_INTER_ROW */
824 rcb_bits = width * 42;
825 rcb_info[RCB_INTER_ROW].size = MPP_RCB_BYTES(rcb_bits);
826 /* RCB_INTER_COL */
827 rcb_info[RCB_INTER_COL].size = 0;
828 /* RCB_INTRA_ROW */
829 rcb_bits = width * 44;
830 rcb_info[RCB_INTRA_ROW].size = MPP_RCB_BYTES(rcb_bits);
831 /* RCB_DBLK_ROW */
832 rcb_bits = width * (2 + (mbaff ? 12 : 6) * bit_depth);
833 rcb_info[RCB_DBLK_ROW].size = MPP_RCB_BYTES(rcb_bits);
834 /* RCB_SAO_ROW */
835 rcb_info[RCB_SAO_ROW].size = 0;
836 /* RCB_FBC_ROW */
837 if (regs->common.reg012.fbc_e) {
838 rcb_bits = (chroma_format_idc > 1) ? (2 * width * bit_depth) : 0;
839 } else
840 rcb_bits = 0;
841 rcb_info[RCB_FBC_ROW].size = MPP_RCB_BYTES(rcb_bits);
842 /* RCB_FILT_COL */
843 rcb_info[RCB_FILT_COL].size = 0;
844 }
845
hal_h264d_rcb_info_update(void * hal,Vdpu34xH264dRegSet * regs)846 static void hal_h264d_rcb_info_update(void *hal, Vdpu34xH264dRegSet *regs)
847 {
848 H264dHalCtx_t *p_hal = (H264dHalCtx_t*)hal;
849 RK_U32 mbaff = p_hal->pp->MbaffFrameFlag;
850 RK_U32 bit_depth = p_hal->pp->bit_depth_luma_minus8 + 8;
851 RK_U32 chroma_format_idc = p_hal->pp->chroma_format_idc;
852 Vdpu34xH264dRegCtx *ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;
853 RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);
854 RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);
855
856 if ( ctx->bit_depth != bit_depth ||
857 ctx->chroma_format_idc != chroma_format_idc ||
858 ctx->mbaff != mbaff ||
859 ctx->width != width ||
860 ctx->height != height) {
861 RK_U32 i;
862 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(ctx->reg_buf) : 1;
863
864 ctx->rcb_buf_size = vdpu34x_get_rcb_buf_size(ctx->rcb_info, width, height);
865 h264d_refine_rcb_size(hal, ctx->rcb_info, regs, width, height);
866 for (i = 0; i < loop; i++) {
867 MppBuffer rcb_buf = ctx->rcb_buf[i];
868
869 if (rcb_buf) {
870 mpp_buffer_put(rcb_buf);
871 ctx->rcb_buf[i] = NULL;
872 }
873 mpp_buffer_get(p_hal->buf_group, &rcb_buf, ctx->rcb_buf_size);
874 ctx->rcb_buf[i] = rcb_buf;
875 }
876
877 if (mbaff && 2 == chroma_format_idc)
878 mpp_err("Warning: rkv do not support H.264 4:2:2 MBAFF decoding.");
879
880 ctx->bit_depth = bit_depth;
881 ctx->width = width;
882 ctx->height = height;
883 ctx->mbaff = mbaff;
884 ctx->chroma_format_idc = chroma_format_idc;
885 }
886 }
887
vdpu34x_h264d_setup_colmv_buf(void * hal,RK_U32 width,RK_U32 height)888 static MPP_RET vdpu34x_h264d_setup_colmv_buf(void *hal, RK_U32 width, RK_U32 height)
889 {
890 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
891 RK_U32 ctu_size = 16, colmv_size = 4, colmv_byte = 16;
892 RK_U32 colmv_compress = p_hal->pp->frame_mbs_only_flag ? 1 : 0;
893 RK_S32 mv_size;
894
895 mv_size = vdpu34x_get_colmv_size(width, height, ctu_size, colmv_byte, colmv_size, colmv_compress);
896
897 /* if is field mode is enabled enlarge colmv buffer and disable colmv compression */
898 if (!p_hal->pp->frame_mbs_only_flag)
899 mv_size *= 2;
900
901 if (p_hal->cmv_bufs == NULL || p_hal->mv_size < mv_size) {
902 size_t size = mv_size;
903
904 if (p_hal->cmv_bufs) {
905 hal_bufs_deinit(p_hal->cmv_bufs);
906 p_hal->cmv_bufs = NULL;
907 }
908
909 hal_bufs_init(&p_hal->cmv_bufs);
910 if (p_hal->cmv_bufs == NULL) {
911 mpp_err_f("colmv bufs init fail");
912 return MPP_NOK;
913 }
914 p_hal->mv_size = mv_size;
915 p_hal->mv_count = mpp_buf_slot_get_count(p_hal->frame_slots);
916 hal_bufs_setup(p_hal->cmv_bufs, p_hal->mv_count, 1, &size);
917 }
918
919 return MPP_OK;
920 }
921
vdpu34x_h264d_gen_regs(void * hal,HalTaskInfo * task)922 MPP_RET vdpu34x_h264d_gen_regs(void *hal, HalTaskInfo *task)
923 {
924 MPP_RET ret = MPP_ERR_UNKNOW;
925 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
926 RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);
927 RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);
928 Vdpu34xH264dRegCtx *ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;
929 Vdpu34xH264dRegSet *regs = ctx->regs;
930 INP_CHECK(ret, NULL == p_hal);
931
932 if (task->dec.flags.parse_err ||
933 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
934 goto __RETURN;
935 }
936
937 if (p_hal->fast_mode) {
938 RK_U32 i = 0;
939 for (i = 0; i < MPP_ARRAY_ELEMS(ctx->reg_buf); i++) {
940 if (!ctx->reg_buf[i].valid) {
941 task->dec.reg_index = i;
942 regs = ctx->reg_buf[i].regs;
943
944 ctx->spspps_offset = ctx->offset_spspps[i];
945 ctx->rps_offset = ctx->offset_rps[i];
946 ctx->sclst_offset = ctx->offset_sclst[i];
947 ctx->reg_buf[i].valid = 1;
948 break;
949 }
950 }
951 }
952
953 if (vdpu34x_h264d_setup_colmv_buf(hal, width, height))
954 goto __RETURN;
955 prepare_spspps(p_hal, (RK_U64 *)&ctx->spspps, sizeof(ctx->spspps));
956 prepare_framerps(p_hal, (RK_U64 *)&ctx->rps, sizeof(ctx->rps));
957 prepare_scanlist(p_hal, ctx->sclst, sizeof(ctx->sclst));
958 set_registers(p_hal, regs, task);
959
960 //!< copy datas
961 RK_U32 i = 0;
962 if (!p_hal->fast_mode && !p_hal->pp->spspps_update) {
963 RK_U32 offset = 0;
964 RK_U32 len = VDPU34X_SPS_PPS_LEN; //!< sps+pps data length
965 for (i = 0; i < 256; i++) {
966 offset = ctx->spspps_offset + (sizeof(ctx->spspps) * i) + len;
967 memcpy((char *)ctx->bufs_ptr + offset, (char *)ctx->spspps + len, sizeof(ctx->spspps) - len);
968 }
969 } else {
970 RK_U32 offset = 0;
971 for (i = 0; i < 256; i++) {
972 offset = ctx->spspps_offset + (sizeof(ctx->spspps) * i);
973 memcpy((char *)ctx->bufs_ptr + offset, (void *)ctx->spspps, sizeof(ctx->spspps));
974 }
975 }
976
977 regs->h264d_addr.pps_base = ctx->bufs_fd;
978 mpp_dev_set_reg_offset(p_hal->dev, 161, ctx->spspps_offset);
979
980 memcpy((char *)ctx->bufs_ptr + ctx->rps_offset, (void *)ctx->rps, sizeof(ctx->rps));
981 regs->h264d_addr.rps_base = ctx->bufs_fd;
982 mpp_dev_set_reg_offset(p_hal->dev, 163, ctx->rps_offset);
983
984 regs->common.reg012.scanlist_addr_valid_en = 1;
985 if (p_hal->pp->scaleing_list_enable_flag) {
986 memcpy((char *)ctx->bufs_ptr + ctx->sclst_offset, (void *)ctx->sclst, sizeof(ctx->sclst));
987 regs->h264d_addr.scanlist_addr = ctx->bufs_fd;
988 mpp_dev_set_reg_offset(p_hal->dev, 180, ctx->sclst_offset);
989 } else {
990 regs->h264d_addr.scanlist_addr = 0;
991 }
992
993 hal_h264d_rcb_info_update(p_hal, regs);
994 vdpu34x_setup_rcb(®s->common_addr, p_hal->dev, p_hal->fast_mode ?
995 ctx->rcb_buf[task->dec.reg_index] : ctx->rcb_buf[0],
996 ctx->rcb_info);
997 vdpu34x_setup_statistic(®s->common, ®s->statistic);
998 mpp_buffer_sync_end(ctx->bufs);
999
1000 __RETURN:
1001 return ret = MPP_OK;
1002 }
1003
vdpu34x_h264d_start(void * hal,HalTaskInfo * task)1004 MPP_RET vdpu34x_h264d_start(void *hal, HalTaskInfo *task)
1005 {
1006 MPP_RET ret = MPP_ERR_UNKNOW;
1007 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1008 INP_CHECK(ret, NULL == p_hal);
1009
1010 if (task->dec.flags.parse_err ||
1011 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
1012 goto __RETURN;
1013 }
1014
1015 Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;
1016 Vdpu34xH264dRegSet *regs = p_hal->fast_mode ?
1017 reg_ctx->reg_buf[task->dec.reg_index].regs :
1018 reg_ctx->regs;
1019 MppDev dev = p_hal->dev;
1020
1021 do {
1022 MppDevRegWrCfg wr_cfg;
1023 MppDevRegRdCfg rd_cfg;
1024
1025 wr_cfg.reg = ®s->common;
1026 wr_cfg.size = sizeof(regs->common);
1027 wr_cfg.offset = OFFSET_COMMON_REGS;
1028
1029 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
1030 if (ret) {
1031 mpp_err_f("set register write failed %d\n", ret);
1032 break;
1033 }
1034
1035 wr_cfg.reg = ®s->h264d_param;
1036 wr_cfg.size = sizeof(regs->h264d_param);
1037 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS;
1038
1039 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
1040 if (ret) {
1041 mpp_err_f("set register write failed %d\n", ret);
1042 break;
1043 }
1044
1045 wr_cfg.reg = ®s->common_addr;
1046 wr_cfg.size = sizeof(regs->common_addr);
1047 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS;
1048
1049 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
1050 if (ret) {
1051 mpp_err_f("set register write failed %d\n", ret);
1052 break;
1053 }
1054
1055 wr_cfg.reg = ®s->h264d_addr;
1056 wr_cfg.size = sizeof(regs->h264d_addr);
1057 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS;
1058
1059 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
1060 if (ret) {
1061 mpp_err_f("set register write failed %d\n", ret);
1062 break;
1063 }
1064
1065 if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3588) {
1066 wr_cfg.reg = ®s->h264d_highpoc;
1067 wr_cfg.size = sizeof(regs->h264d_highpoc);
1068 wr_cfg.offset = OFFSET_POC_HIGHBIT_REGS;
1069 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
1070 if (ret) {
1071 mpp_err_f("set register write failed %d\n", ret);
1072 break;
1073 }
1074 }
1075
1076 wr_cfg.reg = ®s->statistic;
1077 wr_cfg.size = sizeof(regs->statistic);
1078 wr_cfg.offset = OFFSET_STATISTIC_REGS;
1079
1080 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
1081 if (ret) {
1082 mpp_err_f("set register write failed %d\n", ret);
1083 break;
1084 }
1085
1086 rd_cfg.reg = ®s->irq_status;
1087 rd_cfg.size = sizeof(regs->irq_status);
1088 rd_cfg.offset = OFFSET_INTERRUPT_REGS;
1089
1090 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
1091 if (ret) {
1092 mpp_err_f("set register read failed %d\n", ret);
1093 break;
1094 }
1095
1096 /* rcb info for sram */
1097 vdpu34x_set_rcbinfo(dev, reg_ctx->rcb_info);
1098
1099 /* send request to hardware */
1100 ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
1101 if (ret) {
1102 mpp_err_f("send cmd failed %d\n", ret);
1103 break;
1104 }
1105 } while (0);
1106
1107 __RETURN:
1108 return ret = MPP_OK;
1109 }
1110
vdpu34x_h264d_wait(void * hal,HalTaskInfo * task)1111 MPP_RET vdpu34x_h264d_wait(void *hal, HalTaskInfo *task)
1112 {
1113 MPP_RET ret = MPP_ERR_UNKNOW;
1114 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1115
1116 INP_CHECK(ret, NULL == p_hal);
1117 Vdpu34xH264dRegCtx *reg_ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;
1118 Vdpu34xH264dRegSet *p_regs = p_hal->fast_mode ?
1119 reg_ctx->reg_buf[task->dec.reg_index].regs :
1120 reg_ctx->regs;
1121
1122 if (task->dec.flags.parse_err ||
1123 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
1124 goto __SKIP_HARD;
1125 }
1126
1127 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
1128 if (ret)
1129 mpp_err_f("poll cmd failed %d\n", ret);
1130
1131 __SKIP_HARD:
1132 if (p_hal->dec_cb) {
1133 DecCbHalDone param;
1134
1135 param.task = (void *)&task->dec;
1136 param.regs = (RK_U32 *)p_regs;
1137
1138 if (p_regs->irq_status.reg224.dec_error_sta ||
1139 (!p_regs->irq_status.reg224.dec_rdy_sta) ||
1140 p_regs->irq_status.reg224.buf_empty_sta ||
1141 p_regs->irq_status.reg226.strmd_error_status ||
1142 p_regs->irq_status.reg227.colmv_error_ref_picidx ||
1143 p_regs->irq_status.reg225.strmd_detect_error_flag)
1144 param.hard_err = 1;
1145 else
1146 param.hard_err = 0;
1147
1148 mpp_callback(p_hal->dec_cb, ¶m);
1149 }
1150 memset(&p_regs->irq_status.reg224, 0, sizeof(RK_U32));
1151 if (p_hal->fast_mode) {
1152 reg_ctx->reg_buf[task->dec.reg_index].valid = 0;
1153 }
1154
1155 (void)task;
1156 __RETURN:
1157 return ret = MPP_OK;
1158 }
1159
vdpu34x_h264d_reset(void * hal)1160 MPP_RET vdpu34x_h264d_reset(void *hal)
1161 {
1162 MPP_RET ret = MPP_ERR_UNKNOW;
1163 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1164
1165 INP_CHECK(ret, NULL == p_hal);
1166
1167
1168 __RETURN:
1169 return ret = MPP_OK;
1170 }
1171
vdpu34x_h264d_flush(void * hal)1172 MPP_RET vdpu34x_h264d_flush(void *hal)
1173 {
1174 MPP_RET ret = MPP_ERR_UNKNOW;
1175 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1176
1177 INP_CHECK(ret, NULL == p_hal);
1178
1179 __RETURN:
1180 return ret = MPP_OK;
1181 }
1182
vdpu34x_h264d_control(void * hal,MpiCmd cmd_type,void * param)1183 MPP_RET vdpu34x_h264d_control(void *hal, MpiCmd cmd_type, void *param)
1184 {
1185 MPP_RET ret = MPP_ERR_UNKNOW;
1186 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1187
1188 INP_CHECK(ret, NULL == p_hal);
1189
1190 switch ((MpiCmd)cmd_type) {
1191 case MPP_DEC_SET_FRAME_INFO: {
1192 MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param);
1193 RK_U32 imgwidth = mpp_frame_get_width((MppFrame)param);
1194 RK_U32 imgheight = mpp_frame_get_height((MppFrame)param);
1195
1196 mpp_log("control info: fmt %d, w %d, h %d\n", fmt, imgwidth, imgheight);
1197 if (fmt == MPP_FMT_YUV422SP) {
1198 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
1199 }
1200 if (MPP_FRAME_FMT_IS_FBC(fmt)) {
1201 vdpu34x_afbc_align_calc(p_hal->frame_slots, (MppFrame)param, 16);
1202 } else if (imgwidth > 1920 || imgheight > 1088) {
1203 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, rkv_hor_align_256_odds);
1204 }
1205 break;
1206 }
1207 case MPP_DEC_SET_OUTPUT_FORMAT: {
1208
1209 } break;
1210 default:
1211 break;
1212 }
1213
1214 __RETURN:
1215 return ret = MPP_OK;
1216 }
1217
1218 const MppHalApi hal_h264d_vdpu34x = {
1219 .name = "h264d_vdpu34x",
1220 .type = MPP_CTX_DEC,
1221 .coding = MPP_VIDEO_CodingAVC,
1222 .ctx_size = sizeof(Vdpu34xH264dRegCtx),
1223 .flag = 0,
1224 .init = vdpu34x_h264d_init,
1225 .deinit = vdpu34x_h264d_deinit,
1226 .reg_gen = vdpu34x_h264d_gen_regs,
1227 .start = vdpu34x_h264d_start,
1228 .wait = vdpu34x_h264d_wait,
1229 .reset = vdpu34x_h264d_reset,
1230 .flush = vdpu34x_h264d_flush,
1231 .control = vdpu34x_h264d_control,
1232 };
1233