1 /* 2 * Copyright 2017 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __HAL_H263D_VDPU1_REG_TBL_H__ 18 #define __HAL_H263D_VDPU1_REG_TBL_H__ 19 20 #include "rk_type.h" 21 /* Number registers for the decoder */ 22 #define DEC_VDPU1_REGISTERS (101) 23 24 typedef struct { 25 RK_U32 SwReg00; 26 27 struct { 28 RK_U32 sw_dec_en : 1; 29 RK_U32 reserve0 : 3; 30 RK_U32 sw_dec_irq_dis : 1; 31 RK_U32 reserve1 : 3; 32 RK_U32 sw_dec_irq : 1; 33 RK_U32 reserve2 : 3; 34 RK_U32 sw_dec_rdy_int : 1; 35 RK_U32 sw_dec_bus_int : 1; 36 RK_U32 sw_dec_buffer_int : 1; 37 RK_U32 sw_dec_aso_int : 1; 38 RK_U32 sw_dec_error_int : 1; 39 RK_U32 sw_dec_slice_int : 1; 40 RK_U32 sw_dec_timeout : 1; 41 RK_U32 reserve3 : 5; 42 RK_U32 sw_dec_pic_inf : 1; 43 RK_U32 reserve4 : 7; 44 } SwReg01; 45 46 struct { 47 RK_U32 sw_dec_max_burst : 5; 48 RK_U32 sw_dec_scmd_dis : 1; 49 RK_U32 sw_dec_adv_pre_dis : 1; 50 RK_U32 sw_tiled_mode_lsb : 1; 51 RK_U32 sw_dec_out_endian : 1; 52 RK_U32 sw_dec_in_endian : 1; 53 RK_U32 sw_dec_clk_gate_e : 1; 54 RK_U32 sw_dec_latency : 6; 55 RK_U32 sw_tiled_mode_msb : 1; 56 RK_U32 sw_dec_data_disc_e : 1; 57 RK_U32 sw_dec_outswap32_e : 1; 58 RK_U32 sw_dec_inswap32_e : 1; 59 RK_U32 sw_dec_strendian_e : 1; 60 RK_U32 sw_dec_strswap32_e : 1; 61 RK_U32 sw_dec_timeout_e : 1; 62 RK_U32 sw_dec_axi_rd_id : 8; 63 } SwReg02; 64 65 struct { 66 RK_U32 sw_dec_axi_wr_id : 8; 67 RK_U32 reserve0 : 1; 68 RK_U32 sw_picord_count_e : 1; 69 RK_U32 sw_seq_mbaff_e : 1; 70 RK_U32 sw_reftopfirst_e : 1; 71 RK_U32 sw_write_mvs_e : 1; 72 RK_U32 sw_pic_fixed_quant : 1; 73 RK_U32 sw_filtering_dis : 1; 74 RK_U32 sw_dec_out_dis : 1; 75 RK_U32 sw_ref_topfield_e : 1; 76 RK_U32 sw_sorenson_e : 1; 77 RK_U32 sw_fwd_interlace_e : 1; 78 RK_U32 sw_pic_topfield_e : 1; 79 RK_U32 sw_pic_inter_e : 1; 80 RK_U32 sw_pic_b_e : 1; 81 RK_U32 sw_pic_fieldmode_e : 1; 82 RK_U32 sw_pic_interlace_e : 1; 83 RK_U32 sw_pjpeg_e : 1; 84 RK_U32 sw_divx3_e : 1; 85 RK_U32 sw_skip_mode : 1; 86 RK_U32 sw_rlc_mode_e : 1; 87 RK_U32 sw_dec_mode : 4; 88 } SwReg03; 89 90 struct { 91 RK_U32 sw_reserve0 : 5; 92 RK_U32 sw_topfieldfirst_e : 1; 93 RK_U32 sw_alt_scan_e : 1; 94 RK_U32 sw_mb_height_off : 4; 95 RK_U32 sw_pic_mb_hight_p : 8; 96 RK_U32 sw_mb_width_off : 4; 97 RK_U32 sw_pic_mb_width : 9; 98 } SwReg04; 99 100 struct { 101 RK_U32 sw_vop_time_incr : 16; 102 RK_U32 sw_intradc_vlc_thr : 3; 103 RK_U32 sw_ch_qp_offset : 5; 104 RK_U32 sw_type1_quant_e : 1; 105 RK_U32 sw_sync_markers_e : 1; 106 RK_U32 sw_strm_start_bit : 6; 107 } SwReg05; 108 109 struct { 110 RK_U32 sw_stream_len : 24; 111 RK_U32 sw_ch_8pix_ileav_e : 1; 112 RK_U32 sw_init_qp : 6; 113 RK_U32 sw_start_code_e : 1; 114 } SwReg06; 115 116 struct { 117 RK_U32 sw_framenum : 16; 118 RK_U32 sw_framenum_len : 5; 119 RK_U32 reserve0 : 5; 120 RK_U32 sw_weight_bipr_idc : 2; 121 RK_U32 sw_weight_pred_e : 1; 122 RK_U32 sw_dir_8x8_infer_e : 1; 123 RK_U32 sw_blackwhite_e : 1; 124 RK_U32 sw_cabac_e : 1; 125 } SwReg07; 126 127 struct { 128 RK_U32 sw_idr_pic_id : 16; 129 RK_U32 sw_idr_pic_e : 1; 130 RK_U32 sw_refpic_mk_len : 11; 131 RK_U32 sw_8x8trans_flag_e : 1; 132 RK_U32 sw_rdpic_cnt_pres : 1; 133 RK_U32 sw_filt_ctrl_pres : 1; 134 RK_U32 sw_const_intra_e : 1; 135 } SwReg08; 136 137 struct { 138 RK_U32 sw_poc_length : 8; 139 RK_U32 reserve0 : 6; 140 RK_U32 sw_refidx0_active : 5; 141 RK_U32 sw_refidx1_active : 5; 142 RK_U32 sw_pps_id : 8; 143 } SwReg09; 144 145 struct { 146 RK_U32 sw_diff_mv_base : 32; 147 } SwReg10; 148 149 RK_U32 SwReg11; 150 151 struct { 152 RK_U32 sw_rlc_vlc_base : 32; 153 } SwReg12; 154 155 struct { 156 RK_U32 dec_out_st_adr : 32; 157 } SwReg13; 158 159 /* MPP passes fd of reference frame to kernel 160 * with the whole register rather than higher 30-bit. 161 * At the same time, the lower 2-bit will be assigned 162 * by kernel. 163 * */ 164 struct { 165 //RK_U32 sw_refer0_topc_e : 1; 166 //RK_U32 sw_refer0_field_e : 1; 167 RK_U32 sw_refer0_base : 32; 168 } SwReg14; 169 170 struct { 171 //RK_U32 sw_refer1_topc_e : 1; 172 //RK_U32 sw_refer1_field_e : 1; 173 RK_U32 sw_refer1_base : 32; 174 } SwReg15; 175 176 struct { 177 //RK_U32 sw_refer2_topc_e : 1; 178 //RK_U32 sw_refer2_field_e : 1; 179 RK_U32 sw_refer2_base : 32; 180 } SwReg16; 181 182 struct { 183 //RK_U32 sw_refer3_topc_e : 1; 184 //RK_U32 sw_refer3_field_e : 1; 185 RK_U32 sw_refer3_base : 32; 186 } SwReg17; 187 188 struct { 189 RK_U32 sw_prev_anc_type : 1; 190 RK_U32 sw_h263_vc1_rc : 1; 191 RK_U32 sw_mv_accuracy_fwd : 1; 192 RK_U32 sw_fcode_bwd_ver : 4; 193 RK_U32 sw_fcode_bwd_hor : 4; 194 RK_U32 sw_fcode_fwd_ver : 4; 195 RK_U32 sw_fcode_fwd_hor : 4; 196 RK_U32 sw_alt_scan_flag_e : 1; 197 RK_U32 reserve0 : 12; 198 } SwReg18; 199 200 struct { 201 //RK_U32 sw_refer5_topc_e : 1; 202 //RK_U32 sw_refer5_field_e : 1; 203 RK_U32 sw_refer5_base : 32; 204 } SwReg19; 205 206 struct { 207 //RK_U32 sw_refer6_topc_e : 1; 208 //RK_U32 sw_refer6_field_e : 1; 209 RK_U32 sw_refer6_base : 32; 210 } SwReg20; 211 212 struct { 213 //RK_U32 sw_refer7_topc_e : 1; 214 //RK_U32 sw_refer7_field_e : 1; 215 RK_U32 sw_refer7_base : 32; 216 } SwReg21; 217 218 219 RK_U32 SwReg22_33[12]; 220 221 struct { 222 RK_U32 reserve : 2; 223 RK_U32 sw_pred_bc_tap_1_1 : 10; 224 RK_U32 sw_pred_bc_tap_1_0 : 10; 225 RK_U32 sw_pred_bc_tap_0_3 : 10; 226 } SwReg34; 227 228 RK_U32 SwReg35_39[5]; 229 230 struct { 231 RK_U32 sw_qtable_base : 32; 232 } SwReg40; 233 234 struct { 235 RK_U32 sw_dir_mv_base : 32; 236 } SwReg41; 237 238 RK_U32 SwReg42_47[6]; 239 240 struct { 241 RK_U32 reserve0 : 15; 242 RK_U32 sw_startmb_y : 8; 243 RK_U32 sw_startmb_x : 9; 244 } SwReg48; 245 246 struct { 247 RK_U32 reserve0 : 2; 248 RK_U32 sw_pred_bc_tap_0_2 : 10; 249 RK_U32 sw_pred_bc_tap_0_1 : 10; 250 RK_U32 sw_pred_bc_tap_0_0 : 10; 251 } SwReg49; 252 253 RK_U32 SwReg50; 254 255 struct { 256 RK_U32 sw_refbu_y_offset : 9; 257 RK_U32 reserve0 : 3; 258 RK_U32 sw_refbu_fparmod_e : 1; 259 RK_U32 sw_refbu_eval_e : 1; 260 RK_U32 sw_refbu_picid : 5; 261 RK_U32 sw_refbu_thr : 12; 262 RK_U32 sw_refbu_e : 1; 263 } SwReg51; 264 265 RK_U32 SwReg52_54[3]; 266 267 struct { 268 RK_U32 sw_apf_threshold : 14; 269 RK_U32 reserve0 : 18; 270 } SwReg55; 271 272 RK_U32 SwReg56_100[45]; 273 } Vpu1H263dRegSet_t; 274 275 #endif /*__HAL_H263_VDPU1_REG_TBL_H__*/ 276