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See the GNU General Public License 97 // for more details. 98 // 99 // You should have received a copy of the GNU General Public License along 100 // with eCos; if not, write to the Free Software Foundation, Inc., 101 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. 102 // 103 // As a special exception, if other files instantiate templates or use macros 104 // or inline functions from this file, or you compile this file and link it 105 // with other works to produce a work based on this file, this file does not 106 // by itself cause the resulting work to be covered by the GNU General Public 107 // License. However the source code for this file must still be made available 108 // in accordance with section (3) of the GNU General Public License. 109 // 110 // This exception does not invalidate any other reasons why a work based on 111 // this file might be covered by the GNU General Public License. 112 // 113 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. 114 // at http://sources.redhat.com/ecos/ecos-license/ 115 // ------------------------------------------- 116 //####ECOSGPLCOPYRIGHTEND#### 117 //========================================================================== 118 //#####DESCRIPTIONBEGIN#### 119 // 120 // Author(s): sfurman 121 // Contributors: 122 // Date: 2003-01-17 123 // Purpose: Define architecture abstractions 124 // Usage: #include <cyg/hal/hal_arch.h> 125 // 126 //####DESCRIPTIONEND#### 127 // 128 //========================================================================== 129 130 #ifndef CYGONCE_HAL_HAL_ARCH_H 131 #define CYGONCE_HAL_HAL_ARCH_H 132 133 // Include macros to access special-purpose registers (SPRs) 134 //#include "spr_defs.h" 135 //#include "AEON_SPR.h" 136 137 #define CYG_HAL_OPENRISC_REG_SIZE 4 138 139 140 // ------------------------------------------------------------------------- 141 // Some useful macros. These are defined here by default. 142 143 // externC is used in mixed C/C++ headers to force C linkage on an external 144 // definition. It avoids having to put all sorts of ifdefs in. 145 146 #ifdef __cplusplus 147 # define externC extern "C" 148 #else 149 # define externC extern 150 #endif 151 152 #define CYG_MACRO_START do { 153 #define CYG_MACRO_END } while (0) 154 155 #define CYG_EMPTY_STATEMENT CYG_MACRO_START CYG_MACRO_END 156 157 #ifndef __ASSEMBLER__ 158 //-------------------------------------------------------------------------- 159 // Processor saved states: 160 // The layout of this structure is also defined in "arch.inc", for assembly 161 // code. Do not change this without changing that (or vice versa). 162 163 #define CYG_HAL_OPENRISC_REG unsigned int 164 #define CYG_WORD unsigned int 165 #define CYG_WORD32 unsigned int 166 #define CYG_ADDRESS unsigned int 167 #define CYG_ADDRWORD unsigned int 168 #define cyg_uint32 unsigned int 169 170 typedef struct 171 { 172 // These are common to all saved states 173 CYG_HAL_OPENRISC_REG r[32]; // GPR regs 174 #ifdef __AEONR2__ 175 CYG_HAL_OPENRISC_REG machi2; // Highest 32-bits of new 32x32=64 multiplier 176 #endif 177 CYG_HAL_OPENRISC_REG machi; // High and low words of 178 CYG_HAL_OPENRISC_REG maclo; // multiply/accumulate reg 179 180 // These are only saved for exceptions and interrupts 181 CYG_WORD32 vector; /* Vector number */ 182 CYG_WORD32 sr; /* Status Reg */ 183 CYG_HAL_OPENRISC_REG pc; /* Program Counter */ 184 185 // Saved only for exceptions, and not restored when continued: 186 // Effective address of instruction/data access that caused exception 187 CYG_HAL_OPENRISC_REG eear; /* Exception effective address reg */ 188 } HAL_SavedRegisters; 189 190 //-------------------------------------------------------------------------- 191 // Utilities 192 #ifdef NOS_MIPS 193 #else //NOS_MIPS 194 // Move from architecture special register (SPR) 195 #ifdef __AEONR2__ 196 197 // Move from architecture special register (SPR) 198 #define MFSPR(_spr_) \ 199 ({ CYG_HAL_OPENRISC_REG _result_; \ 200 asm volatile ("l.mfspr %0, %1, 0;" \ 201 : "=r"(_result_) \ 202 : "r"(_spr_) \ 203 ); \ 204 _result_;}) 205 206 // Move data to architecture special registers (SPR) 207 #define MTSPR(_spr_, _val_) \ 208 CYG_MACRO_START \ 209 CYG_HAL_OPENRISC_REG val = _val_; \ 210 asm volatile ("l.mtspr %1, %0, 0;" \ 211 : \ 212 : "r"(val), "r"(_spr_) \ 213 ); \ 214 CYG_MACRO_END 215 216 #else 217 218 // Move from architecture special register (SPR) 219 #define MFSPR(_spr_) \ 220 ({ CYG_HAL_OPENRISC_REG _result_; \ 221 asm volatile ("l.mfspr %0, r0, %1;" \ 222 : "=r"(_result_) \ 223 : "K"(_spr_) \ 224 ); \ 225 _result_;}) 226 227 // Move data to architecture special registers (SPR) 228 #define MTSPR(_spr_, _val_) \ 229 CYG_MACRO_START \ 230 CYG_HAL_OPENRISC_REG val = _val_; \ 231 asm volatile ("l.mtspr r0, %0, %1;" \ 232 : \ 233 : "r"(val), "K"(_spr_) \ 234 ); \ 235 CYG_MACRO_END 236 237 #endif 238 239 240 //-------------------------------------------------------------------------- 241 // Exception handling function. 242 // This function is defined by the kernel according to this prototype. It is 243 // invoked from the HAL to deal with any CPU exceptions that the HAL does 244 // not want to deal with itself. It usually invokes the kernel's exception 245 // delivery mechanism. 246 247 externC void cyg_hal_deliver_exception( CYG_WORD __code, CYG_ADDRWORD __data ); 248 249 //-------------------------------------------------------------------------- 250 // Bit manipulation macros 251 252 externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask); 253 externC cyg_uint32 hal_msbit_index(cyg_uint32 mask); 254 255 #define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask); 256 257 // NOTE - Below can be optimized with l.ff1 instruction if that optional 258 // instruction is implemented in HW. OR12k does not implement 259 // it at this time, however. 260 #define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask); 261 262 //-------------------------------------------------------------------------- 263 // Context Initialization 264 265 266 // Initialize the context of a thread. 267 // Arguments: 268 // _sparg_ name of variable containing current sp, will be written with new sp 269 // _thread_ thread object address, passed as argument to entry point 270 // _entry_ entry point address. 271 // _id_ bit pattern used in initializing registers, for debugging. 272 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ 273 { \ 274 int _i_; \ 275 register CYG_WORD _sp_ = ((CYG_WORD)_sparg_); \ 276 register HAL_SavedRegisters *_regs_; \ 277 _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters)) & ~(CYGARC_ALIGNMENT));\ 278 _sp_ &= ~(CYGARC_ALIGNMENT); \ 279 for( _i_ = 1; _i_ < 32; _i_++ ) (_regs_)->r[_i_] = (_id_)|_i_; \ 280 (_regs_)->r[1] = (CYG_HAL_OPENRISC_REG)(_sp_); /* SP = top of stack */ \ 281 (_regs_)->r[2] = (CYG_HAL_OPENRISC_REG)(_sp_); /* FP = top of stack */ \ 282 (_regs_)->r[3] = (CYG_HAL_OPENRISC_REG)(_thread_); /* R3 = arg1 = thread ptr */ \ 283 (_regs_)->maclo = 0; /* MACLO = 0 */ \ 284 (_regs_)->machi = 0; /* MACHI = 0 */ \ 285 (_regs_)->sr = (SPR_SR_TEE|SPR_SR_IEE); /* Interrupts enabled */ \ 286 (_regs_)->pc = (CYG_HAL_OPENRISC_REG)(_entry_); /* PC = entry point */ \ 287 (_regs_)->r[9] = (CYG_HAL_OPENRISC_REG)(_entry_); /* PC = entry point */ \ 288 _sparg_ = (CYG_ADDRESS)_regs_; \ 289 } 290 291 //-------------------------------------------------------------------------- 292 // Context switch macros. 293 294 // The arguments to these macros are *pointers* to locations where the 295 // stack pointer of the thread is to be stored/retrieved, i.e. *not* 296 // the value of the stack pointer itself. 297 298 externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); 299 externC void hal_thread_load_context( CYG_ADDRESS to ) 300 __attribute__ ((noreturn)); 301 302 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \ 303 hal_thread_switch_context( (CYG_ADDRESS)_tspptr_, \ 304 (CYG_ADDRESS)_fspptr_); 305 306 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \ 307 hal_thread_load_context( (CYG_ADDRESS)_tspptr_ ); 308 309 // Translate a stack pointer as saved by the thread context macros above into 310 // a pointer to a HAL_SavedRegisters structure. 311 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ 312 (_regs_) = (HAL_SavedRegisters *)(_sp_) 313 314 //-------------------------------------------------------------------------- 315 // Execution reorder barrier. 316 // When optimizing the compiler can reorder code. In multithreaded systems 317 // where the order of actions is vital, this can sometimes cause problems. 318 // This macro may be inserted into places where reordering should not happen. 319 // The "memory" keyword is potentially unnecessary, but it is harmless to 320 // keep it. 321 322 #define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) 323 324 //-------------------------------------------------------------------------- 325 // Breakpoint support 326 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to 327 // occur if executed. 328 // HAL_BREAKINST is the value of the breakpoint instruction and... 329 // HAL_BREAKINST_SIZE is its size in bytes and... 330 // HAL_BREAKINST_TYPE is its type. 331 332 #ifdef __AEONR2__ 333 #define HAL_BREAKPOINT(_label_) \ 334 asm volatile (" .globl _" #_label_ ";" \ 335 "_" #_label_ ":" \ 336 " bt.trap 1;" \ 337 ); 338 339 #define HAL_BREAKINST (0x8000) // l.trap 1 instruction 340 341 #define HAL_BREAKINST_SIZE 2 342 343 #define HAL_BREAKINST_TYPE cyg_uint16 344 #else 345 #define HAL_BREAKPOINT(_label_) \ 346 asm volatile (" .globl _" #_label_ ";" \ 347 "_" #_label_ ":" \ 348 " l.trap 1;" \ 349 ); 350 351 #define HAL_BREAKINST (0x21000001) // l.trap 1 instruction 352 353 #define HAL_BREAKINST_SIZE 4 354 355 #define HAL_BREAKINST_TYPE cyg_uint32 356 #endif //__AEONR2__ 357 358 //-------------------------------------------------------------------------- 359 // Thread register state manipulation for GDB support. 360 361 // Default to a 32 bit register size for GDB register dumps. 362 #ifndef CYG_HAL_GDB_REG 363 #define CYG_HAL_GDB_REG CYG_WORD32 364 #endif 365 366 // Register layout expected by GDB 367 typedef struct 368 { 369 CYG_HAL_OPENRISC_REG r[32]; // GPR regs 370 CYG_HAL_OPENRISC_REG pc; // Program Counter 371 CYG_HAL_OPENRISC_REG sr; // Supervisor/Status Reg 372 } GDB_Registers; 373 374 // Copy a set of registers from a HAL_SavedRegisters structure into a 375 // GDB_Registers structure. 376 #define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \ 377 CYG_MACRO_START \ 378 GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_); \ 379 int _i_; \ 380 \ 381 for( _i_ = 0; _i_ < 32; _i_++ ) { \ 382 _gdb_->r[_i_] = (_regs_)->r[_i_]; \ 383 } \ 384 \ 385 _gdb_->pc = (_regs_)->pc; \ 386 _gdb_->sr = (_regs_)->sr; \ 387 CYG_MACRO_END 388 389 // Copy a set of registers from a GDB_Registers structure into a 390 // HAL_SavedRegisters structure. 391 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ 392 CYG_MACRO_START \ 393 GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_); \ 394 int _i_; \ 395 \ 396 for( _i_ = 0; _i_ < 32; _i_++ ) \ 397 (_regs_)->r[_i_] = _gdb_->r[_i_]; \ 398 \ 399 (_regs_)->pc = _gdb_->pc; \ 400 (_regs_)->sr = _gdb_->sr; \ 401 CYG_MACRO_END 402 403 //-------------------------------------------------------------------------- 404 // HAL setjmp 405 // Note: These definitions are repeated in context.S. If changes are 406 // required remember to update both sets. 407 408 #define CYGARC_JMP_BUF_R1 0 409 #define CYGARC_JMP_BUF_R2 1 410 #define CYGARC_JMP_BUF_R9 2 411 #define CYGARC_JMP_BUF_R10 3 412 #define CYGARC_JMP_BUF_R12 4 413 #define CYGARC_JMP_BUF_R14 5 414 #define CYGARC_JMP_BUF_R16 6 415 #define CYGARC_JMP_BUF_R18 7 416 #define CYGARC_JMP_BUF_R20 8 417 #define CYGARC_JMP_BUF_R22 9 418 #define CYGARC_JMP_BUF_R24 10 419 #define CYGARC_JMP_BUF_R26 11 420 #define CYGARC_JMP_BUF_R28 12 421 #define CYGARC_JMP_BUF_R30 13 422 423 #define CYGARC_JMP_BUF_SIZE 14 424 425 typedef CYG_HAL_OPENRISC_REG hal_jmp_buf[CYGARC_JMP_BUF_SIZE]; 426 427 externC int hal_setjmp(hal_jmp_buf env); 428 externC void hal_longjmp(hal_jmp_buf env, int val); 429 430 //------------------------------------------------------------------------- 431 // Idle thread code. 432 // This macro is called in the idle thread loop, and gives the HAL the 433 // chance to run code when no threads are runnable. Typical idle 434 // thread behaviour might be to halt the processor. 435 436 externC void hal_idle_thread_action(cyg_uint32 loop_count); 437 438 #define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_) 439 440 //-------------------------------------------------------------------------- 441 // Minimal and sensible stack sizes: the intention is that applications 442 // will use these to provide a stack size in the first instance prior to 443 // proper analysis. Idle thread stack should be this big. 444 445 // *** THESE ARE NOT INTENDED TO BE GUARANTEED SUFFICIENT STACK SIZES *** 446 // They are, however, enough to start programming. 447 // You might, for example, need to make your stacks larger if you have 448 // large "auto" variables. 449 450 // This is not a config option because it should not be adjusted except 451 // under "enough rope to hang yourself" sort of disclaimers. 452 453 // Typical case stack frame size: return link + 10 caller-saved temporaries + 4 locals. 454 #define CYGNUM_HAL_STACK_FRAME_SIZE (15 * CYG_HAL_OPENRISC_REG_SIZE) 455 456 // Stack needed for a context switch: 457 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (38 * 4) // sizeof(HAL_SavedRegisters) 458 459 // Interrupt + call to ISR, interrupt_end() and the DSR 460 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE (CYGNUM_HAL_STACK_CONTEXT_SIZE + 2*CYGNUM_HAL_STACK_FRAME_SIZE) 461 462 // We define a minimum stack size as the minimum any thread could ever 463 // legitimately get away with. We can throw asserts if users ask for less 464 // than this. Allow enough for three interrupt sources - clock, serial and 465 // one other 466 467 //#define CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK 468 // If interrupts are segregated onto their own stack... 469 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK 470 471 // An interrupt stack which is large enough for all possible interrupt 472 // conditions (and only used for that purpose) exists. "User" stacks 473 // can therefore be much smaller 474 // NOTE - interrupt stack sizes can be smaller if we don't allow interrupts 475 // to nest. 476 477 # define CYGNUM_HAL_STACK_SIZE_MINIMUM \ 478 ((3 * 5)*CYGNUM_HAL_STACK_FRAME_SIZE + 2*CYGNUM_HAL_STACK_INTERRUPT_SIZE) 479 480 #else 481 482 // No separate interrupt stack exists. Make sure all threads contain 483 // a stack sufficiently large 484 # define CYGNUM_HAL_STACK_SIZE_MINIMUM \ 485 (( 3*CYGNUM_HAL_STACK_INTERRUPT_SIZE) + \ 486 (25*CYGNUM_HAL_STACK_FRAME_SIZE)) 487 #endif 488 489 // Now make a reasonable choice for a typical thread size. Pluck figures 490 // from thin air and say 40 call frames 491 #define CYGNUM_HAL_STACK_SIZE_TYPICAL \ 492 (CYGNUM_HAL_STACK_SIZE_MINIMUM + \ 493 40 * (CYGNUM_HAL_STACK_FRAME_SIZE)) 494 495 #endif /* __ASSEMBLER__ */ 496 497 //-------------------------------------------------------------------------- 498 // Macro for finding return address of current function 499 #define CYGARC_HAL_GET_RETURN_ADDRESS(_x_, _dummy_) \ 500 asm volatile ( "l.ori %0,r9,0;" : "=r" (_x_) ) 501 502 #define CYGARC_HAL_GET_RETURN_ADDRESS_BACKUP(_dummy_) 503 #endif//NOS_MIPS 504 //-------------------------------------------------------------------------- 505 #endif // CYGONCE_HAL_HAL_ARCH_H 506 // End of hal_arch.h 507