1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2019 Cadence Design Systems Inc. 4 */ 5 6 #ifndef __PHY_DP_H_ 7 #define __PHY_DP_H_ 8 9 /** 10 * struct phy_configure_opts_dp - DisplayPort PHY configuration set 11 * 12 * This structure is used to represent the configuration state of a 13 * DisplayPort phy. 14 */ 15 struct phy_configure_opts_dp { 16 /** 17 * @link_rate: 18 * 19 * Link Rate, in Mb/s, of the main link. 20 * 21 * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s 22 */ 23 unsigned int link_rate; 24 25 /** 26 * @lanes: 27 * 28 * Number of active, consecutive, data lanes, starting from 29 * lane 0, used for the transmissions on main link. 30 * 31 * Allowed values: 1, 2, 4 32 */ 33 unsigned int lanes; 34 35 /** 36 * @voltage: 37 * 38 * Voltage swing levels, as specified by DisplayPort specification, 39 * to be used by particular lanes. One value per lane. 40 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc. 41 * 42 * Maximum value: 3 43 */ 44 unsigned int voltage[4]; 45 46 /** 47 * @pre: 48 * 49 * Pre-emphasis levels, as specified by DisplayPort specification, to be 50 * used by particular lanes. One value per lane. 51 * 52 * Maximum value: 3 53 */ 54 unsigned int pre[4]; 55 56 /** 57 * @ssc: 58 * 59 * Flag indicating, whether or not to enable spread-spectrum clocking. 60 * 61 */ 62 u8 ssc : 1; 63 64 /** 65 * @set_rate: 66 * 67 * Flag indicating, whether or not reconfigure link rate and SSC to 68 * requested values. 69 * 70 */ 71 u8 set_rate : 1; 72 73 /** 74 * @set_lanes: 75 * 76 * Flag indicating, whether or not reconfigure lane count to 77 * requested value. 78 * 79 */ 80 u8 set_lanes : 1; 81 82 /** 83 * @set_voltages: 84 * 85 * Flag indicating, whether or not reconfigure voltage swing 86 * and pre-emphasis to requested values. Only lanes specified 87 * by "lanes" parameter will be affected. 88 * 89 */ 90 u8 set_voltages : 1; 91 }; 92 93 #endif /* __PHY_DP_H_ */ 94