1 /* 2 * Header providing constants for Rockchip suspend bindings. 3 * 4 * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd 5 * Author: XiaoDong.Huang 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK322X_H__ 19 #define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK322X_H__ 20 21 #ifndef BIT 22 #define BIT(nr) (1 << (nr)) 23 #endif 24 25 /* the suspend mode */ 26 #define RKPM_CTR_PWR_DMNS BIT(0) 27 #define RKPM_CTR_GTCLKS BIT(1) 28 #define RKPM_CTR_PLLS BIT(2) 29 #define RKPM_CTR_VOLTS BIT(3) 30 #define RKPM_CTR_GPIOS BIT(4) 31 #define RKPM_CTR_DDR BIT(5) 32 #define RKPM_CTR_PMIC BIT(6) 33 34 /* system clk is 24M,and div to min */ 35 #define RKPM_CTR_SYSCLK_DIV BIT(7) 36 /* switch sysclk to 32k, need hardwart support, and div to min */ 37 #define RKPM_CTR_SYSCLK_32K BIT(8) 38 /* switch sysclk to 32k,disable 24M OSC, 39 * need hardwart susport. and div to min 40 */ 41 #define RKPM_CTR_SYSCLK_OSC_DIS BIT(9) 42 #define RKPM_CTR_VOL_PWM0 BIT(10) 43 #define RKPM_CTR_VOL_PWM1 BIT(11) 44 #define RKPM_CTR_VOL_PWM2 BIT(12) 45 #define RKPM_CTR_VOL_PWM3 BIT(13) 46 #define RKPM_CTR_BUS_IDLE BIT(14) 47 #define RKPM_CTR_SRAM BIT(15) 48 /*Low Power Function Selection*/ 49 #define RKPM_CTR_IDLESRAM_MD BIT(16) 50 #define RKPM_CTR_IDLEAUTO_MD BIT(17) 51 #define RKPM_CTR_ARMDP_LPMD BIT(18) 52 #define RKPM_CTR_ARMOFF_LPMD BIT(19) 53 #define RKPM_CTR_ARMLOGDP_LPMD BIT(20) 54 #define RKPM_CTR_ARMOFF_LOGDP_LPMD BIT(21) 55 #define RKPM_CTR_ARMLOGOFF_DLPMD BIT(22) 56 57 #endif 58