1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK1808_H 7 #define _DT_BINDINGS_DRAM_ROCKCHIP_RK1808_H 8 9 #define DDR2_DS_FULL (0) 10 #define DDR2_DS_REDUCE (1) 11 12 #define DDR2_ODT_DIS (0) 13 #define DDR2_ODT_50ohm (50) /* optional */ 14 #define DDR2_ODT_75ohm (75) 15 #define DDR2_ODT_150ohm (150) 16 17 #define DDR3_DS_34ohm (34) 18 #define DDR3_DS_40ohm (40) 19 20 #define DDR3_ODT_DIS (0) 21 #define DDR3_ODT_40ohm (40) 22 #define DDR3_ODT_60ohm (60) 23 #define DDR3_ODT_120ohm (120) 24 25 #define LP2_DS_34ohm (34) 26 #define LP2_DS_40ohm (40) 27 #define LP2_DS_48ohm (48) 28 #define LP2_DS_60ohm (60) 29 #define LP2_DS_68_6ohm (68) /* optional */ 30 #define LP2_DS_80ohm (80) 31 #define LP2_DS_120ohm (120) /* optional */ 32 33 #define LP3_DS_34ohm (34) 34 #define LP3_DS_40ohm (40) 35 #define LP3_DS_48ohm (48) 36 #define LP3_DS_60ohm (60) 37 #define LP3_DS_80ohm (80) 38 #define LP3_DS_34D_40U (3440) 39 #define LP3_DS_40D_48U (4048) 40 #define LP3_DS_34D_48U (3448) 41 42 #define LP3_ODT_DIS (0) 43 #define LP3_ODT_60ohm (60) 44 #define LP3_ODT_120ohm (120) 45 #define LP3_ODT_240ohm (240) 46 47 #define LP4_PDDS_40ohm (40) 48 #define LP4_PDDS_48ohm (48) 49 #define LP4_PDDS_60ohm (60) 50 #define LP4_PDDS_80ohm (80) 51 #define LP4_PDDS_120ohm (120) 52 #define LP4_PDDS_240ohm (240) 53 54 #define LP4_DQ_ODT_40ohm (40) 55 #define LP4_DQ_ODT_48ohm (48) 56 #define LP4_DQ_ODT_60ohm (60) 57 #define LP4_DQ_ODT_80ohm (80) 58 #define LP4_DQ_ODT_120ohm (120) 59 #define LP4_DQ_ODT_240ohm (240) 60 #define LP4_DQ_ODT_DIS (0) 61 62 #define LP4_CA_ODT_40ohm (40) 63 #define LP4_CA_ODT_48ohm (48) 64 #define LP4_CA_ODT_60ohm (60) 65 #define LP4_CA_ODT_80ohm (80) 66 #define LP4_CA_ODT_120ohm (120) 67 #define LP4_CA_ODT_240ohm (240) 68 #define LP4_CA_ODT_DIS (0) 69 70 #define DDR4_DS_34ohm (34) 71 #define DDR4_DS_48ohm (48) 72 #define DDR4_RTT_NOM_DIS (0) 73 #define DDR4_RTT_NOM_60ohm (60) 74 #define DDR4_RTT_NOM_120ohm (120) 75 #define DDR4_RTT_NOM_40ohm (40) 76 #define DDR4_RTT_NOM_240ohm (240) 77 #define DDR4_RTT_NOM_48ohm (48) 78 #define DDR4_RTT_NOM_80ohm (80) 79 #define DDR4_RTT_NOM_34ohm (34) 80 81 #define PHY_DDR3_RON_DISABLE (0) 82 #define PHY_DDR3_RON_340ohm (1) 83 #define PHY_DDR3_RON_170ohm (2) 84 #define PHY_DDR3_RON_113ohm (3) 85 #define PHY_DDR3_RON_85ohm (4) 86 #define PHY_DDR3_RON_68ohm (5) 87 #define PHY_DDR3_RON_57ohm (6) 88 #define PHY_DDR3_RON_49ohm (7) 89 #define PHY_DDR3_RON_43ohm (16) 90 #define PHY_DDR3_RON_38ohm (17) 91 #define PHY_DDR3_RON_34ohm (18) 92 #define PHY_DDR3_RON_31ohm (19) 93 #define PHY_DDR3_RON_28ohm (20) 94 #define PHY_DDR3_RON_26ohm (21) 95 #define PHY_DDR3_RON_24ohm (22) 96 #define PHY_DDR3_RON_23ohm (23) 97 #define PHY_DDR3_RON_21ohm (24) 98 #define PHY_DDR3_RON_20ohm (25) 99 #define PHY_DDR3_RON_19ohm (26) 100 #define PHY_DDR3_RON_18ohm (27) 101 #define PHY_DDR3_RON_17ohm (28) 102 #define PHY_DDR3_RON_16ohm (29) 103 #define PHY_DDR3_RON_15ohm (31) 104 105 #define PHY_DDR3_RTT_DISABLE (0) 106 #define PHY_DDR3_RTT_852ohm (1) 107 #define PHY_DDR3_RTT_427ohm (2) 108 #define PHY_DDR3_RTT_284ohm (3) 109 #define PHY_DDR3_RTT_213ohm (4) 110 #define PHY_DDR3_RTT_171ohm (5) 111 #define PHY_DDR3_RTT_142ohm (6) 112 #define PHY_DDR3_RTT_122ohm (7) 113 #define PHY_DDR3_RTT_107ohm (16) 114 #define PHY_DDR3_RTT_95ohm (17) 115 #define PHY_DDR3_RTT_85ohm (18) 116 #define PHY_DDR3_RTT_78ohm (19) 117 #define PHY_DDR3_RTT_71ohm (20) 118 #define PHY_DDR3_RTT_66ohm (21) 119 #define PHY_DDR3_RTT_61ohm (22) 120 #define PHY_DDR3_RTT_57ohm (23) 121 #define PHY_DDR3_RTT_53ohm (24) 122 #define PHY_DDR3_RTT_50ohm (25) 123 #define PHY_DDR3_RTT_47ohm (26) 124 #define PHY_DDR3_RTT_45ohm (27) 125 #define PHY_DDR3_RTT_43ohm (28) 126 #define PHY_DDR3_RTT_41ohm (29) 127 #define PHY_DDR3_RTT_39ohm (30) 128 #define PHY_DDR3_RTT_37ohm (31) 129 130 #define PHY_DDR4_LPDDR2_3_RON_DISABLE (0) 131 #define PHY_DDR4_LPDDR2_3_RON_376ohm (1) 132 #define PHY_DDR4_LPDDR2_3_RON_188ohm (2) 133 #define PHY_DDR4_LPDDR2_3_RON_125ohm (3) 134 #define PHY_DDR4_LPDDR2_3_RON_94ohm (4) 135 #define PHY_DDR4_LPDDR2_3_RON_75ohm (5) 136 #define PHY_DDR4_LPDDR2_3_RON_63ohm (6) 137 #define PHY_DDR4_LPDDR2_3_RON_54ohm (7) 138 #define PHY_DDR4_LPDDR2_3_RON_47ohm (16) 139 #define PHY_DDR4_LPDDR2_3_RON_42ohm (17) 140 #define PHY_DDR4_LPDDR2_3_RON_38ohm (18) 141 #define PHY_DDR4_LPDDR2_3_RON_34ohm (19) 142 #define PHY_DDR4_LPDDR2_3_RON_31ohm (20) 143 #define PHY_DDR4_LPDDR2_3_RON_29ohm (21) 144 #define PHY_DDR4_LPDDR2_3_RON_27ohm (22) 145 #define PHY_DDR4_LPDDR2_3_RON_25ohm (23) 146 #define PHY_DDR4_LPDDR2_3_RON_23ohm (24) 147 #define PHY_DDR4_LPDDR2_3_RON_22ohm (25) 148 #define PHY_DDR4_LPDDR2_3_RON_21ohm (26) 149 #define PHY_DDR4_LPDDR2_3_RON_20ohm (27) 150 #define PHY_DDR4_LPDDR2_3_RON_19ohm (28) 151 #define PHY_DDR4_LPDDR2_3_RON_18ohm (29) 152 #define PHY_DDR4_LPDDR2_3_RON_17ohm (30) 153 #define PHY_DDR4_LPDDR2_3_RON_16ohm (31) 154 155 #define PHY_DDR4_LPDDR2_3_RTT_DISABLE (0) 156 #define PHY_DDR4_LPDDR2_3_RTT_915ohm (1) 157 #define PHY_DDR4_LPDDR2_3_RTT_458ohm (2) 158 #define PHY_DDR4_LPDDR2_3_RTT_305ohm (3) 159 #define PHY_DDR4_LPDDR2_3_RTT_229ohm (4) 160 #define PHY_DDR4_LPDDR2_3_RTT_183ohm (5) 161 #define PHY_DDR4_LPDDR2_3_RTT_153ohm (6) 162 #define PHY_DDR4_LPDDR2_3_RTT_131ohm (7) 163 #define PHY_DDR4_LPDDR2_3_RTT_115ohm (16) 164 #define PHY_DDR4_LPDDR2_3_RTT_102ohm (17) 165 #define PHY_DDR4_LPDDR2_3_RTT_92ohm (18) 166 #define PHY_DDR4_LPDDR2_3_RTT_83ohm (19) 167 #define PHY_DDR4_LPDDR2_3_RTT_76ohm (20) 168 #define PHY_DDR4_LPDDR2_3_RTT_70ohm (21) 169 #define PHY_DDR4_LPDDR2_3_RTT_65ohm (22) 170 #define PHY_DDR4_LPDDR2_3_RTT_61ohm (23) 171 #define PHY_DDR4_LPDDR2_3_RTT_57ohm (24) 172 #define PHY_DDR4_LPDDR2_3_RTT_54ohm (25) 173 #define PHY_DDR4_LPDDR2_3_RTT_51ohm (26) 174 #define PHY_DDR4_LPDDR2_3_RTT_48ohm (27) 175 #define PHY_DDR4_LPDDR2_3_RTT_46ohm (28) 176 #define PHY_DDR4_LPDDR2_3_RTT_44ohm (29) 177 #define PHY_DDR4_LPDDR2_3_RTT_42ohm (30) 178 #define PHY_DDR4_LPDDR2_3_RTT_40ohm (31) 179 180 #endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK1808_H*/ 181