1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) STMicroelectronics 2024 - All Rights Reserved 4 */ 5 6 #ifndef _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ 7 #define _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ 8 9 #define CMD_DIV 0 10 #define CMD_MUX 1 11 #define CMD_CLK 2 12 #define CMD_FLEXGEN 3 13 #define CMD_OBS 4 14 15 #define CMD_ADDR_BIT 0x80000000 16 17 #define CMD_SHIFT 26 18 #define CMD_MASK 0xFC000000 19 #define CMD_DATA_MASK 0x03FFFFFF 20 21 #define DIV_ID_SHIFT 8 22 #define DIV_ID_MASK 0x0000FF00 23 24 #define DIV_DIVN_SHIFT 0 25 #define DIV_DIVN_MASK 0x000000FF 26 27 #define MUX_ID_SHIFT 4 28 #define MUX_ID_MASK 0x00000FF0 29 30 #define MUX_SEL_SHIFT 0 31 #define MUX_SEL_MASK 0x0000000F 32 33 /* CLK define */ 34 #define CLK_ON_MASK BIT(21) 35 #define CLK_ON_SHIFT 21 36 37 #define CLK_ID_MASK GENMASK_32(20, 12) 38 #define CLK_ID_SHIFT 12 39 40 #define CLK_NO_DIV_MASK 0x0000080 41 #define CLK_DIV_MASK GENMASK_32(10, 5) 42 #define CLK_DIV_SHIFT 5 43 44 #define CLK_NO_SEL_MASK 0x00000010 45 #define CLK_SEL_MASK GENMASK_32(3, 0) 46 #define CLK_SEL_SHIFT 0 47 48 #define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\ 49 ((state) << CLK_ON_SHIFT) |\ 50 ((clk_id) << CLK_ID_SHIFT) |\ 51 ((div) << CLK_DIV_SHIFT) |\ 52 ((sel) << CLK_SEL_SHIFT)) 53 54 #define CLK_OFF 0 55 #define CLK_ON 1 56 #define CLK_NODIV 0x00000040 57 #define CLK_NOMUX 0x00000010 58 59 /* Flexgen define */ 60 #define FLEX_ID_SHIFT 13 61 #define FLEX_SEL_SHIFT 9 62 #define FLEX_PDIV_SHIFT 6 63 #define FLEX_FDIV_SHIFT 0 64 65 #define FLEX_ID_MASK GENMASK_32(18, 13) 66 #define FLEX_SEL_MASK GENMASK_32(12, 9) 67 #define FLEX_PDIV_MASK GENMASK_32(8, 6) 68 #define FLEX_FDIV_MASK GENMASK_32(5, 0) 69 70 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ 71 ((div_id) << DIV_ID_SHIFT |\ 72 (div))) 73 74 #define MUX_CFG(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ 75 ((mux_id) << MUX_ID_SHIFT |\ 76 (sel))) 77 78 #define CLK_ADDR_SHIFT 16 79 #define CLK_ADDR_MASK 0x7FFF0000 80 #define CLK_ADDR_VAL_MASK 0xFFFF 81 82 #define DIV_LSMCU 0 83 #define DIV_APB1 1 84 #define DIV_APB2 2 85 #define DIV_APB3 3 86 #define DIV_APB4 4 87 #define DIV_APBDBG 5 88 #define DIV_RTC 6 89 #define DIV_NB 7 90 91 #define MUX_MUXSEL0 0 92 #define MUX_MUXSEL1 1 93 #define MUX_MUXSEL2 2 94 #define MUX_MUXSEL3 3 95 #define MUX_MUXSEL4 4 96 #define MUX_MUXSEL5 5 97 #define MUX_MUXSEL6 6 98 #define MUX_MUXSEL7 7 99 #define MUX_XBARSEL 8 100 #define MUX_RTC 9 101 #define MUX_MCO1 10 102 #define MUX_MCO2 11 103 #define MUX_ADC12 12 104 #define MUX_ADC3 13 105 #define MUX_USB2PHY1 14 106 #define MUX_USB2PHY2 15 107 #define MUX_USB3PCIEPHY 16 108 #define MUX_DSIBLANE 17 109 #define MUX_DSIPHY 18 110 #define MUX_LVDSPHY 19 111 #define MUX_DTS 20 112 #define MUX_D3PER 21 113 #define MUX_NB 22 114 115 #define MUXSEL_HSI 0 116 #define MUXSEL_HSE 1 117 #define MUXSEL_MSI 2 118 119 /* KERNEL source clocks */ 120 #define MUX_RTC_DISABLED 0x0 121 #define MUX_RTC_LSE 0x1 122 #define MUX_RTC_LSI 0x2 123 #define MUX_RTC_HSE 0x3 124 125 #define MUX_MCO1_FLEX61 0x0 126 #define MUX_MCO1_OBSER0 0x1 127 128 #define MUX_MCO2_FLEX62 0x0 129 #define MUX_MCO2_OBSER1 0x1 130 131 #define MUX_ADC12_FLEX46 0x0 132 #define MUX_ADC12_LSMCU 0x1 133 134 #define MUX_ADC3_FLEX47 0x0 135 #define MUX_ADC3_LSMCU 0x1 136 #define MUX_ADC3_FLEX46 0x2 137 138 #define MUX_USB2PHY1_FLEX57 0x0 139 #define MUX_USB2PHY1_HSE 0x1 140 141 #define MUX_USB2PHY2_FLEX58 0x0 142 #define MUX_USB2PHY2_HSE 0x1 143 144 #define MUX_USB3PCIEPHY_FLEX34 0x0 145 #define MUX_USB3PCIEPHY_HSE 0x1 146 147 #define MUX_DSIBLANE_DSIPHY 0x0 148 #define MUX_DSIBLANE_FLEX27 0x1 149 150 #define MUX_DSIPHY_FLEX28 0x0 151 #define MUX_DSIPHY_HSE 0x1 152 153 #define MUX_LVDSPHY_FLEX32 0x0 154 #define MUX_LVDSPHY_HSE 0x1 155 156 #define MUX_DTS_HSI 0x0 157 #define MUX_DTS_HSE 0x1 158 #define MUX_DTS_MSI 0x2 159 160 #define MUX_D3PER_MSI 0x0 161 #define MUX_D3PER_LSI 0x1 162 #define MUX_D3PER_LSE 0x2 163 164 /* PLLs source clocks */ 165 #define PLL_SRC_HSI 0x0 166 #define PLL_SRC_HSE 0x1 167 #define PLL_SRC_MSI 0x2 168 #define PLL_SRC_DISABLED 0x3 169 170 /* XBAR source clocks */ 171 #define XBAR_SRC_PLL4 0x0 172 #define XBAR_SRC_PLL5 0x1 173 #define XBAR_SRC_PLL6 0x2 174 #define XBAR_SRC_PLL7 0x3 175 #define XBAR_SRC_PLL8 0x4 176 #define XBAR_SRC_HSI 0x5 177 #define XBAR_SRC_HSE 0x6 178 #define XBAR_SRC_MSI 0x7 179 #define XBAR_SRC_HSI_KER 0x8 180 #define XBAR_SRC_HSE_KER 0x9 181 #define XBAR_SRC_MSI_KER 0xA 182 #define XBAR_SRC_SPDIF_SYMB 0xB 183 #define XBAR_SRC_I2S 0xC 184 #define XBAR_SRC_LSI 0xD 185 #define XBAR_SRC_LSE 0xE 186 187 /* 188 * Configure a XBAR channel with its clock source 189 * channel_nb: XBAR channel number from 0 to 63 190 * channel_src: one of the 15 previous XBAR source clocks defines 191 * channel_prediv: value of the PREDIV in channel RCC_PREDIVxCFGR register 192 * can be either 1, 2, 4 or 1024 193 * channel_findiv: value of the FINDIV in channel RCC_FINDIVxCFGR register 194 * from 1 to 64 195 */ 196 197 #define FLEXGEN_CFG(ch, sel, pdiv, fdiv) ((CMD_FLEXGEN << CMD_SHIFT) |\ 198 ((ch) << FLEX_ID_SHIFT) |\ 199 ((sel) << FLEX_SEL_SHIFT) |\ 200 ((pdiv) << FLEX_PDIV_SHIFT) |\ 201 ((fdiv) << FLEX_FDIV_SHIFT)) 202 203 /* Register addresses of MCO1 & MCO2 */ 204 #define MCO1 0x494 205 #define MCO2 0x498 206 207 #define MCO_OFF 0 208 #define MCO_ON 1 209 #define MCO_STATUS_SHIFT 8 210 211 #define MCO_CFG(addr, sel, status) (CMD_ADDR_BIT |\ 212 ((addr) << CLK_ADDR_SHIFT) |\ 213 ((status) << MCO_STATUS_SHIFT) |\ 214 (sel)) 215 #define OBS_ID_SHIFT 14 216 #define OBS_STATUS_SHIFT 13 217 #define OBS_INTEXT_SHIFT 12 218 #define OBS_DIV_SHIFT 9 219 #define OBS_INV_SHIFT 8 220 #define OBS_SEL_SHIFT 0 221 222 #define OBS_ID_MASK GENMASK_32(14, 14) 223 #define OBS_STATUS_MASK GENMASK_32(13, 13) 224 #define OBS_INTEXT_MASK GENMASK_32(12, 12) 225 #define OBS_DIV_MASK GENMASK_32(11, 9) 226 #define OBS_INV_MASK BIT(8) 227 #define OBS_SEL_MASK GENMASK_32(7, 0) 228 229 #define OBS_CFG(id, status, int_ext, div, inv, sel)\ 230 ((CMD_OBS << CMD_SHIFT) |\ 231 ((id) << OBS_ID_SHIFT) |\ 232 ((status) << OBS_STATUS_SHIFT) |\ 233 ((int_ext) << OBS_INTEXT_SHIFT) |\ 234 ((div) << OBS_DIV_SHIFT) |\ 235 ((inv) << OBS_INV_SHIFT) |\ 236 ((sel) << OBS_SEL_SHIFT)) 237 238 #define OBS0 0 239 #define OBS1 1 240 241 #define OBS_OFF 0 242 #define OBS_ON 1 243 244 #define OBS_INT 0 245 #define OBS_EXT 1 246 247 #define OBS_DIV1 0 248 #define OBS_DIV2 1 249 #define OBS_DIV4 2 250 #define OBS_DIV8 3 251 #define OBS_DIV16 4 252 #define OBS_DIV32 5 253 #define OBS_DIV64 6 254 #define OBS_DIV128 7 255 256 #define OBS_NO_INV 0 257 #define OBS_INV 1 258 259 #define OBS_INT_CFG(id, status, div, inv, sel)\ 260 OBS_CFG(id, status, OBS_INT, div, inv, sel) 261 262 #define OBS_EXT_CFG(id, status, div, inv, sel)\ 263 OBS_CFG(id, status, OBS_EXT, div, inv, sel) 264 265 /* define for st,pll /csg */ 266 #define SSCG_MODE_CENTER_SPREAD 0 267 #define SSCG_MODE_DOWN_SPREAD 1 268 269 /* define for st,drive */ 270 #define LSEDRV_LOWEST 0 271 #define LSEDRV_MEDIUM_LOW 2 272 #define LSEDRV_MEDIUM_HIGH 1 273 #define LSEDRV_HIGHEST 3 274 275 #endif /* _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ */ 276