1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved 4 */ 5 6 #ifndef _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_ 7 #define _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_ 8 9 #define CMD_DIV 0 10 #define CMD_MUX 1 11 #define CMD_FLEXGEN 3 12 #define CMD_OBS 4 13 14 #define CMD_ADDR_BIT (1 << 31) 15 16 #define CMD_SHIFT 26 17 #define CMD_MASK 0xFC000000 18 #define CMD_DATA_MASK 0x03FFFFFF 19 20 #define DIV_ID_SHIFT 8 21 #define DIV_ID_MASK 0x0000FF00 22 23 #define DIV_DIVN_SHIFT 0 24 #define DIV_DIVN_MASK 0x000000FF 25 26 #define MUX_ID_SHIFT 4 27 #define MUX_ID_MASK 0x00000FF0 28 29 #define MUX_SEL_SHIFT 0 30 #define MUX_SEL_MASK 0x0000000F 31 32 /* Flexgen define */ 33 #define FLEX_ID_SHIFT 20 34 #define FLEX_SEL_SHIFT 16 35 #define FLEX_PDIV_SHIFT 6 36 #define FLEX_FDIV_SHIFT 0 37 38 #define FLEX_ID_MASK GENMASK_32(25, 20) 39 #define FLEX_SEL_MASK GENMASK_32(19, 16) 40 #define FLEX_PDIV_MASK GENMASK_32(15, 6) 41 #define FLEX_FDIV_MASK GENMASK_32(5, 0) 42 43 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ 44 ((div_id) << DIV_ID_SHIFT |\ 45 (div))) 46 47 #define MUX_CFG(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ 48 ((mux_id) << MUX_ID_SHIFT |\ 49 (sel))) 50 51 #define CLK_ADDR_SHIFT 16 52 #define CLK_ADDR_MASK GENMASK_32(30, 16) 53 #define CLK_ADDR_VAL_MASK GENMASK_32(15, 0) 54 55 #define DIV_LSMCU 0 56 #define DIV_APB1 1 57 #define DIV_APB2 2 58 #define DIV_APB3 3 59 #define DIV_APB4 4 60 #define DIV_APB5 5 61 #define DIV_APBDBG 6 62 #define DIV_RTC 7 63 #define DIV_NB 8 64 65 #define MUX_MUXSEL0 0 66 #define MUX_MUXSEL1 1 67 #define MUX_MUXSEL2 2 68 #define MUX_MUXSEL3 3 69 #define MUX_MUXSEL4 4 70 #define MUX_MUXSEL5 5 71 #define MUX_MUXSEL6 6 72 #define MUX_MUXSEL7 7 73 #define MUX_XBARSEL 8 74 #define MUX_RTC 9 75 #define MUX_MCO1 10 76 #define MUX_MCO2 11 77 #define MUX_ADC1 12 78 #define MUX_ADC2 13 79 #define MUX_USB2PHY1 14 80 #define MUX_USB2PHY2 15 81 #define MUX_DTS 16 82 #define MUX_CPU1 17 83 #define MUX_NB 18 84 85 #define MUXSEL_HSI 0 86 #define MUXSEL_HSE 1 87 #define MUXSEL_MSI 2 88 89 /* KERNEL source clocks */ 90 #define MUX_RTC_DISABLED 0x0 91 #define MUX_RTC_LSE 0x1 92 #define MUX_RTC_LSI 0x2 93 #define MUX_RTC_HSE 0x3 94 95 #define MUX_MCO1_FLEX61 0x0 96 #define MUX_MCO1_OBSER0 0x1 97 98 #define MUX_MCO2_FLEX62 0x0 99 #define MUX_MCO2_OBSER1 0x1 100 101 #define MUX_ADC1_FLEX46 0x0 102 #define MUX_ADC1_LSMCU 0x1 103 104 #define MUX_ADC2_FLEX47 0x0 105 #define MUX_ADC2_LSMCU 0x1 106 #define MUX_ADC2_FLEX46 0x2 107 108 #define MUX_USB2PHY1_FLEX57 0x0 109 #define MUX_USB2PHY1_HSE 0x1 110 111 #define MUX_USB2PHY2_FLEX58 0x0 112 #define MUX_USB2PHY2_HSE 0x1 113 114 #define MUX_DTS_HSI 0x0 115 #define MUX_DTS_HSE 0x1 116 #define MUX_DTS_MSI 0x2 117 118 /* PLLs source clocks */ 119 #define PLL_SRC_HSI 0x0 120 #define PLL_SRC_HSE 0x1 121 #define PLL_SRC_MSI 0x2 122 #define PLL_SRC_DISABLED 0x3 123 124 /* XBAR source clocks */ 125 #define XBAR_SRC_PLL4 0x0 126 #define XBAR_SRC_PLL5 0x1 127 #define XBAR_SRC_PLL6 0x2 128 #define XBAR_SRC_PLL7 0x3 129 #define XBAR_SRC_PLL8 0x4 130 #define XBAR_SRC_HSI 0x5 131 #define XBAR_SRC_HSE 0x6 132 #define XBAR_SRC_MSI 0x7 133 #define XBAR_SRC_HSI_KER 0x8 134 #define XBAR_SRC_HSE_KER 0x9 135 #define XBAR_SRC_MSI_KER 0xA 136 #define XBAR_SRC_SPDIF_SYMB 0xB 137 #define XBAR_SRC_I2S 0xC 138 #define XBAR_SRC_LSI 0xD 139 #define XBAR_SRC_LSE 0xE 140 141 /* 142 * Configure a XBAR channel with its clock source 143 * ch: XBAR channel number from 0 to 63 144 * sel: one of the 15 previous XBAR source clocks defines 145 * pdiv: value of the PREDIV in channel RCC_PREDIVxCFGR register can be either 146 * 1, 2, 4 or 1024 147 * fdiv: value of the FINDIV in channel RCC_FINDIVxCFGR register from 1 to 64 148 */ 149 150 #define FLEXGEN_CFG(ch, sel, pdiv, fdiv) ((CMD_FLEXGEN << CMD_SHIFT) |\ 151 ((ch) << FLEX_ID_SHIFT) |\ 152 ((sel) << FLEX_SEL_SHIFT) |\ 153 ((pdiv) << FLEX_PDIV_SHIFT) |\ 154 ((fdiv) << FLEX_FDIV_SHIFT)) 155 156 /* Register addresses of MCO1 & MCO2 */ 157 #define MCO1 0x488 158 #define MCO2 0x48C 159 160 #define MCO_OFF 0 161 #define MCO_ON 1 162 #define MCO_STATUS_SHIFT 8 163 164 #define MCO_CFG(addr, sel, status) (CMD_ADDR_BIT |\ 165 ((addr) << CLK_ADDR_SHIFT) |\ 166 ((status) << MCO_STATUS_SHIFT) |\ 167 (sel)) 168 #define OBS_ID_SHIFT 14 169 #define OBS_STATUS_SHIFT 13 170 #define OBS_INTEXT_SHIFT 12 171 #define OBS_DIV_SHIFT 9 172 #define OBS_INV_SHIFT 8 173 #define OBS_SEL_SHIFT 0 174 175 #define OBS_ID_MASK GENMASK_32(14, 14) 176 #define OBS_STATUS_MASK GENMASK_32(13, 13) 177 #define OBS_INTEXT_MASK GENMASK_32(12, 12) 178 #define OBS_DIV_MASK GENMASK_32(11, 9) 179 #define OBS_INV_MASK (1 << 8) 180 #define OBS_SEL_MASK GENMASK_32(7, 0) 181 182 #define OBS_CFG(id, status, int_ext, div, inv, sel)\ 183 ((CMD_OBS << CMD_SHIFT) |\ 184 ((id) << OBS_ID_SHIFT) |\ 185 ((status) << OBS_STATUS_SHIFT) |\ 186 ((int_ext) << OBS_INTEXT_SHIFT) |\ 187 ((div) << OBS_DIV_SHIFT) |\ 188 ((inv) << OBS_INV_SHIFT) |\ 189 ((sel) << OBS_SEL_SHIFT)) 190 191 #define OBS0 0 192 #define OBS1 1 193 194 #define OBS_OFF 0 195 #define OBS_ON 1 196 197 #define OBS_INT 0 198 #define OBS_EXT 1 199 200 #define OBS_DIV1 0 201 #define OBS_DIV2 1 202 #define OBS_DIV4 2 203 #define OBS_DIV8 3 204 #define OBS_DIV16 4 205 #define OBS_DIV32 5 206 #define OBS_DIV64 6 207 #define OBS_DIV128 7 208 209 #define OBS_NO_INV 0 210 #define OBS_INV 1 211 212 #define OBS_INT_CFG(id, status, div, inv, sel)\ 213 OBS_CFG((id), (status), OBS_INT, (div), (inv), (sel)) 214 215 #define OBS_EXT_CFG(id, status, div, inv, sel)\ 216 OBS_CFG((id), (status), OBS_EXT, (div), (inv), (sel)) 217 218 /* define for st,pll /csg */ 219 #define SSCG_MODE_CENTER_SPREAD 0 220 #define SSCG_MODE_DOWN_SPREAD 1 221 222 /* define for st,drive */ 223 #define LSEDRV_LOWEST 0 224 #define LSEDRV_MEDIUM_LOW 2 225 #define LSEDRV_MEDIUM_HIGH 1 226 #define LSEDRV_HIGHEST 3 227 228 #endif /* _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_ */ 229