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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvDMD_DVBT_INTERN.h 98 /// @brief DVBT Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DRV_DVBT2_V2_H_ 103 #define _DRV_DVBT2_V2_H_ 104 105 //#include "MsCommon.h" 106 //#include "drvDMD_common.h" 107 #include "drvDMD_INTERN_DVBT2.h" 108 #ifdef __cplusplus 109 extern "C" 110 { 111 #endif 112 //------------------------------------------------------------------------------------------------- 113 // Driver Capability 114 //------------------------------------------------------------------------------------------------- 115 typedef enum { 116 DMD_DVBT2_DRV_CMD_Init , 117 DMD_DVBT2_DRV_CMD_Exit , 118 DMD_DVBT2_DRV_CMD_SetDbgLevel , 119 DMD_DVBT2_DRV_CMD_GetInfo , 120 DMD_DVBT2_DRV_CMD_GetLibVer , 121 DMD_DVBT2_DRV_CMD_GetFWVer , 122 DMD_DVBT2_DRV_CMD_GetReg , 123 DMD_DVBT2_DRV_CMD_SetReg , 124 DMD_DVBT2_DRV_CMD_SetSerialControl , 125 DMD_DVBT2_DRV_CMD_SetReset , 126 DMD_DVBT2_DRV_CMD_SetConfig , 127 DMD_DVBT2_DRV_CMD_SetActive , 128 DMD_DVBT2_DRV_CMD_GetLock , 129 // DMD_DVBT2_DRV_CMD_GetSignalStrengthWithRFPower, 130 // DMD_DVBT2_DRV_CMD_GetSignalQualityWithRFPower , 131 DMD_DVBT2_DRV_CMD_GetSNR , 132 DMD_DVBT2_DRV_CMD_GetPostLdpcBer , 133 DMD_DVBT2_DRV_CMD_GetPreLdpcBer , 134 DMD_DVBT2_DRV_CMD_GetPacketErr , 135 DMD_DVBT2_DRV_CMD_GetL1Info , 136 DMD_DVBT2_DRV_CMD_GetFreqOffset , 137 DMD_DVBT2_DRV_CMD_NORDIG_SSI_Table_Write , 138 DMD_DVBT2_DRV_CMD_NORDIG_SSI_Table_Read , 139 DMD_DVBT2_DRV_CMD_SetPowerState , 140 DMD_DVBT2_DRV_CMD_GetPlpBitMap , 141 DMD_DVBT2_DRV_CMD_GetPlpGroupID , 142 DMD_DVBT2_DRV_CMD_SetPlpID , 143 144 } DMD_DVBT2_DRV_COMMAND; 145 /// For demod init 146 147 148 typedef struct DLL_PACKED _DMD_DVBT2_InitData_Transform 149 { 150 // tuner parameter 151 MS_U8 u8SarChannel; 152 /* 153 DMD_RFAGC_SSI *pTuner_RfagcSsi; 154 MS_U16 u16Tuner_RfagcSsi_Size; 155 DMD_IFAGC_SSI *pTuner_IfagcSsi_LoRef; 156 MS_U16 u16Tuner_IfagcSsi_LoRef_Size; 157 DMD_IFAGC_SSI *pTuner_IfagcSsi_HiRef; 158 MS_U16 u16Tuner_IfagcSsi_HiRef_Size; 159 DMD_IFAGC_ERR *pTuner_IfagcErr_LoRef; 160 MS_U16 u16Tuner_IfagcErr_LoRef_Size; 161 DMD_IFAGC_ERR *pTuner_IfagcErr_HiRef; 162 MS_U16 u16Tuner_IfagcErr_HiRef_Size; 163 DMD_SQI_CN_NORDIGP1 *pSqiCnNordigP1; 164 MS_U16 u16SqiCnNordigP1_Size; 165 */ 166 167 // register init 168 MS_U8 *u8DMD_DVBT2_DSPRegInitExt; // TODO use system variable type 169 MS_U8 u8DMD_DVBT2_DSPRegInitSize; 170 MS_U8 *u8DMD_DVBT2_InitExt; // TODO use system variable type 171 172 MS_U32 u32EqStartAddr; 173 MS_U32 u32TdiStartAddr; 174 MS_U32 u32DjbStartAddr; 175 MS_U32 u32FwStartAddr; 176 } DMD_DVBT2_InitData_Transform; 177 178 179 typedef struct DLL_PACKED _DVBT2_INIT_PARAM 180 { 181 DMD_DVBT2_InitData_Transform *pDMD_DVBT2_InitData; 182 MS_U32 u32InitDataLen; 183 MS_BOOL ret; 184 }DVBT2_INIT_PARAM, *PDVBT2_INIT_PARAM; 185 186 187 typedef struct DLL_PACKED _DVBT2_EXIT_PARAM 188 { 189 MS_BOOL ret; 190 }DVBT2_EXIT_PARAM, *PDVBT2_EXIT_PARAM; 191 192 193 typedef struct DLL_PACKED _DVBT2_SETDBGLEVEL_PARAM 194 { 195 DMD_T2_DbgLv u8DbgLevel; 196 MS_BOOL ret; 197 }DVBT2_SETDBGLEVEL_PARAM, *PDVBT2_SETDBGLEVEL_PARAM; 198 199 typedef struct DLL_PACKED _DVBT2_GETINFO_PARAM 200 { 201 DMD_DVBT2_INFO_TYPE eInfoType; 202 DMD_DVBT2_Info* pInfo; 203 MS_BOOL ret; 204 }DVBT2_GETINFO_PARAM, *PDVBT2_GETINFO_PARAM; 205 206 207 typedef struct DLL_PACKED _DVBT2_GETLIBVER_PARAM 208 { 209 const MSIF_Version **ppVersion; 210 MS_BOOL ret; 211 }DVBT2_GETLIBVER_PARAM, *PDVBT2_GETLIBVER_PARAM; 212 213 214 typedef struct DLL_PACKED _DVBT2_GETFWVER_PARAM 215 { 216 MS_U16 *ver; 217 MS_BOOL ret; 218 }DVBT2_GETFWVER_PARAM, *PDVBT2_GETFWVER_PARAM; 219 220 typedef struct DLL_PACKED _DVBT2_GETREG_PARAM 221 { 222 MS_U16 u16Addr; 223 MS_U8 *pu8Data; 224 MS_BOOL ret; 225 }DVBT2_GETREG_PARAM, *PDVBT2_GETREG_PARAM; 226 227 typedef struct DLL_PACKED _DVBT2_SETREG_PARAM 228 { 229 MS_U16 u16Addr; 230 MS_U8 u8Data; 231 MS_BOOL ret; 232 }DVBT2_SETREG_PARAM, *PDVBT2_SETREG_PARAM; 233 234 typedef struct DLL_PACKED _DVBT2_SETSERIALCONTROL_PARAM 235 { 236 MS_BOOL bEnable; 237 MS_BOOL ret; 238 }DVBT2_SETSERIALCONTROL_PARAM,*PDVBT2_SETSERIALCONTROL_PARAM; 239 240 typedef struct DLL_PACKED _DVBT2_SETCONFIG_PARAM 241 { 242 DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW; 243 MS_BOOL bSerialTS; 244 MS_U8 u8PlpID; 245 MS_BOOL ret; 246 }DVBT2_SETCONFIG_PARAM,*PDVBT2_SETCONFIG_PARAM; 247 248 typedef struct DLL_PACKED _DVBT2_SETACTIVE_PARAM 249 { 250 MS_BOOL bEnable; 251 MS_BOOL ret; 252 }DVBT2_SETACTIVE_PARAM,*PDVBT2_SETACTIVE_PARAM; 253 254 typedef struct DLL_PACKED _DVBT2_GETLOCK_PARAM 255 { 256 DMD_DVBT2_GETLOCK_TYPE eType; 257 DMD_T2_LOCK_STATUS *eLockStatus; 258 MS_BOOL ret; 259 }DVBT2_GETLOCK_PARAM, *PDVBT2_GETLOCK_PARAM; 260 261 #if 0 262 typedef struct DLL_PACKED _DVBT2_GETSIGNALSTRENGTHWITHRFPOWER_PARAM 263 { 264 MS_U16 *u16Strength; 265 float fRFPowerDbm ; 266 MS_BOOL ret; 267 }DVBT2_GETSIGNALSTRENGTHWITHRFPOWER_PARAM,*PDVBT2_GETSIGNALSTRENGTHWITHRFPOWER_PARAM; 268 269 typedef struct DLL_PACKED _DVBT2_GETSIGNALQUALITYWITHRFPOWER_PARAM 270 { 271 MS_U16 *u16Quality; 272 float fRFPowerDbm; 273 MS_BOOL ret; 274 }DVBT2_GETSIGNALQUALITYWITHRFPOWER_PARAM,*PDVBT2_GETSIGNALQUALITYWITHRFPOWER_PARAM; 275 #endif 276 277 #if 0 278 typedef struct DLL_PACKED _DVBT2_GETSNR_PARAM 279 { 280 float *fSNR; 281 MS_BOOL ret; 282 }DVBT2_GETSNR_PARAM,*PDVBT2_GETSNR_PARAM; 283 #else 284 typedef struct DLL_PACKED _DVBT2_GETSNR_PARAM 285 { 286 MS_U16 *u16_snr100; 287 MS_U8 *snr_cali; 288 MS_U8 *u8_gi; 289 MS_BOOL ret; 290 }DVBT2_GETSNR_PARAM,*PDVBT2_GETSNR_PARAM; 291 #endif 292 293 #if 0 294 typedef struct DLL_PACKED _DVBT2_GETPOSTLDPCBER_PARAM 295 { 296 float *ber; 297 MS_BOOL ret; 298 }DVBT2_GETPOSTLDPCBER_PARAM,*PDVBT2_GETPOSTLDPCBER_PARAM; 299 #else 300 typedef struct DLL_PACKED _DVBT2_GETPOSTLDPCBER_PARAM 301 { 302 MS_U32 *BitErr_reg; 303 MS_U16 *BitErrPeriod_reg; 304 MS_U16 *FecType; 305 MS_BOOL ret; 306 }DVBT2_GETPOSTLDPCBER_PARAM,*PDVBT2_GETPOSTLDPCBER_PARAM; 307 #endif 308 309 #if 0 310 typedef struct DLL_PACKED _DVBT2_GETPRELDPCBERPARAM 311 { 312 float *ber; 313 MS_BOOL ret; 314 }DVBT2_GETPRELDPCBERPARAM,*PDVBT2_GETPRELDPCBERPARAM; 315 #else 316 typedef struct DLL_PACKED _DVBT2_GETPRELDPCBERPARAM 317 { 318 MS_U32 *BitErr_reg; 319 MS_U16 *BitErrPeriod_reg; 320 MS_U16 *FecType; 321 MS_BOOL ret; 322 }DVBT2_GETPRELDPCBERPARAM,*PDVBT2_GETPRELDPCBERPARAM; 323 #endif 324 325 typedef struct DLL_PACKED _DVBT2_GETPACKETERRPARAM 326 { 327 MS_U16 *pktErr; 328 MS_BOOL ret; 329 }DVBT2_GETPACKETERRPARAM,*PDVBT2_GETPACKETERRPARAM; 330 331 332 typedef struct DLL_PACKED _DVBT2_GETL1INFO_PARAM 333 { 334 MS_U16 *u16Info; 335 DMD_DVBT2_SIGNAL_INFO eSignalType; 336 MS_BOOL ret; 337 }DVBT2_GETL1INFO_PARAM,*PDVBT2_GETL1INFO_PARAM; 338 339 #if 0 340 typedef struct DLL_PACKED _DVBT2_GETFREQOFFSET_PARAM 341 { 342 float *pFreqOff; 343 MS_BOOL ret; 344 }DVBT2_GETFREQOFFSET_PARAM,*PDVBT2_GETFREQOFFSET_PARAM; 345 #else 346 typedef struct DLL_PACKED _DVBT2_GETFREQOFFSET_PARAM 347 { 348 MS_U32 *CfoTd_reg; 349 MS_U32 *CfoFd_reg; 350 MS_U32 *Icfo_reg; 351 MS_U8 *fft_reg; 352 MS_BOOL ret; 353 }DVBT2_GETFREQOFFSET_PARAM,*PDVBT2_GETFREQOFFSET_PARAM; 354 #endif 355 356 #if 0 357 typedef struct DLL_PACKED _DVBT2_NORDIG_SSI_TABLE_WRITE_PARAM 358 { 359 DMD_T2_CONSTEL constel; 360 DMD_T2_CODERATE code_rate; 361 float write_value; 362 MS_BOOL ret; 363 }DVBT2_NORDIG_SSI_TABLE_WRITE_PARAM,*PDVBT2_NORDIG_SSI_TABLE_WRITE_PARAM; 364 365 typedef struct DLL_PACKED _DVBT2_NORDIG_SSI_TABLE_READ 366 { 367 DMD_T2_CONSTEL constel; 368 DMD_T2_CODERATE code_rate; 369 float *read_value; 370 MS_BOOL ret; 371 }DVBT2_NORDIG_SSI_TABLE_READ_PARAM,*PDVBT2_NORDIG_SSI_TABLE_READ; 372 #endif 373 374 typedef struct DLL_PACKED _DVBT2_SETPOWERSTATE_PARAM 375 { 376 EN_POWER_MODE u16PowerState; 377 MS_U32 ret; 378 }DVBT2_SETPOWERSTATE_PARAM,*PDVBT2_SETPOWERSTATE_PARAM; 379 380 typedef struct DLL_PACKED _DVBT2_GETPLPBITMAP_PARAM 381 { 382 MS_U8* u8PlpBitMap; 383 MS_BOOL ret; 384 }DVBT2_GETPLPBITMAP_PARAM,*PDVBT2_GETPLPBITMAP_PARAM; 385 386 typedef struct DLL_PACKED _DVBT2_GETPLPGROUPID_PARAM 387 { 388 MS_U8 u8PlpID; 389 MS_U8* u8GroupID; 390 MS_BOOL ret; 391 }DVBT2_GETPLPGROUPID_PARAM,*PDVBT2_GETPLPGROUPID_PARAM; 392 393 typedef struct DLL_PACKED _DMD_DVBT2_SETPLPID_PARAM 394 { 395 MS_U8 u8PlpID; 396 MS_U8 u8GroupID; 397 MS_BOOL ret; 398 }DMD_DVBT2_SETPLPID_PARAM,*PDMD_DVBT2_SETPLPID_PARAM; 399 400 401 402 403 404 405 406 407 408 409 /*************************************************/ 410 411 412 MS_U32 DVBT2Open(void** pInstantTmp, MS_U32 u32ModuleVersion, void* pAttribute); 413 MS_U32 DVBT2Close(void* pInstantTmp); 414 MS_U32 DVBT2Ioctl(void* pInstantTmp, MS_U32 u32Cmd, void* pArgs); 415 416 417 418 #ifdef __cplusplus 419 } 420 #endif 421 422 #endif // _DRV_DVBT2_H_