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77 //<MStar Software>
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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file drvAVD.c
98 /// @brief AVD Driver Interface
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102
103 //-------------------------------------------------------------------------------------------------
104 // Include Files
105 //-------------------------------------------------------------------------------------------------
106 // Common Definition
107 #ifdef MSOS_TYPE_LINUX_KERNEL
108 #include <linux/string.h>
109 #else
110 #include <string.h>
111 #include <stdio.h>
112 #include <math.h>
113 #endif
114 #include "MsCommon.h"
115 #include "MsVersion.h"
116 #include "MsOS.h"
117
118 // Internal Definition
119 //#include "regCHIP.h"
120 //#include "regAVD.h"
121 //#include "mapi_tuner.h"
122 #include "drvSYS.h"
123 #include "drvDMD_VD_MBX.h"
124 #include "drvDMD_INTERN_DVBT.h"
125 #include "drvDMD_INTERN_DVBT_v2.h"
126
127 #include "halDMD_INTERN_DVBT.h"
128 #include "halDMD_INTERN_common.h"
129 #include "drvSAR.h" // for Utopia2
130 #include "utopia.h"
131
132 #include "utopia_dapi.h"
133
134 #include "drvSAR.h" // for Utopia2
135 #include "ULog.h"
136 //-------------------------------------------------------------------------------------------------
137 // Driver Compiler Options
138 //-------------------------------------------------------------------------------------------------
139
140
141 //-------------------------------------------------------------------------------------------------
142 // Local Defines
143 //-------------------------------------------------------------------------------------------------
144
145
146 //-------------------------------------------------------------------------------------------------
147 // Local Structurs
148 //-------------------------------------------------------------------------------------------------
149
150
151 //-------------------------------------------------------------------------------------------------
152 // Global Variables
153 //-------------------------------------------------------------------------------------------------
154 #define DMD_LOCK() \
155 do{ \
156 MS_ASSERT(MsOS_In_Interrupt() == FALSE); \
157 if (_u8DMDDbgLevel == DMD_DBGLV_DEBUG) ULOGD("DEMOD","%s lock mutex\n", __FUNCTION__);\
158 MsOS_ObtainMutex(_s32DMD_DVBT_Mutex, MSOS_WAIT_FOREVER);\
159 }while(0)
160
161 #define DMD_UNLOCK() \
162 do{ \
163 MsOS_ReleaseMutex(_s32DMD_DVBT_Mutex);\
164 if (_u8DMDDbgLevel == DMD_DBGLV_DEBUG) ULOGD("DEMOD","%s unlock mutex\n", __FUNCTION__); \
165 }while(0)
166
167 //MS_U8 DVBT_TS_PHASE_EN =0;
168 //MS_U8 DVBT_TS_PHASE_NUM = 0;
169 //-------------------------------------------------------------------------------------------------
170 // Local Variables
171 //-------------------------------------------------------------------------------------------------
172 #if 1
173 /*static MSIF_Version _drv_dmd_dvbt_intern_version = {
174 .MW = { DMD_DVBT_INTERN_VER, },
175 };*/
176 #else
177 static MSIF_Version _drv_dmd_dvbt_intern_version;
178 #endif
179
180 //static DMD_DVBT_InitData _sDMD_DVBT_InitData;
181 //static DMD_DbgLv _u8DMDDbgLevel=DMD_DBGLV_NONE;
182 //static MS_S32 _s32DMD_DVBT_Mutex=-1;
183 //static DMD_DVBT_Info sDMD_DVBT_Info;
184 //static MS_U16 u16DMD_DVBT_TPS_Timeout = 1500, u16DMD_DVBT_FEC_Timeout=6000;
185 static MS_U32 u32DMD_DVBT_IfFrequency = 36167L, u32DMD_DVBT_FsFrequency = 45474L;
186 static MS_U8 u8DMD_DVBT_IQSwap=0;
187 //static DMD_RF_CHANNEL_BANDWIDTH eDMD_DVBT_BandWidth=E_DMD_RF_CH_BAND_8MHz;
188 static DMD_SQI_CN_NORDIGP1 SqiCnNordigP1[] =
189 {
190 {_QPSK, _CR1Y2, 5.1 },
191 {_QPSK, _CR2Y3, 6.9 },
192 {_QPSK, _CR3Y4, 7.9 },
193 {_QPSK, _CR5Y6, 8.9 },
194 {_QPSK, _CR7Y8, 9.7 },
195 {_16QAM, _CR1Y2, 10.8},
196 {_16QAM, _CR2Y3, 13.1},
197 {_16QAM, _CR3Y4, 14.6},
198 {_16QAM, _CR5Y6, 15.6},
199 {_16QAM, _CR7Y8, 16.0},
200 {_64QAM, _CR1Y2, 16.5},
201 {_64QAM, _CR2Y3, 18.7},
202 {_64QAM, _CR3Y4, 20.2},
203 {_64QAM, _CR5Y6, 21.6},
204 {_64QAM, _CR7Y8, 22.5},
205 };
206
207 static DMD_SSI_DBM_NORDIGP1 dvbt_ssi_dbm_nordigp1[] =
208 {
209 { _QPSK , _CR1Y2, -93},
210 { _QPSK , _CR2Y3, -91},
211 { _QPSK , _CR3Y4, -90},
212 { _QPSK , _CR5Y6, -89},
213 { _QPSK , _CR7Y8, -88},
214
215 { _16QAM , _CR1Y2, -87},
216 { _16QAM , _CR2Y3, -85},
217 { _16QAM , _CR3Y4, -84},
218 { _16QAM , _CR5Y6, -83},
219 { _16QAM , _CR7Y8, -82},
220
221 { _64QAM , _CR1Y2, -82},
222 { _64QAM , _CR2Y3, -80},
223 { _64QAM , _CR3Y4, -78},
224 { _64QAM , _CR5Y6, -77},
225 { _64QAM , _CR7Y8, -76},
226 { _UNKNOW_QAM , _UNKNOW_CR, 0.0},
227 };
228
229 //-------------------------------------------------------------------------------------------------
230 // Debug Functions
231 //-------------------------------------------------------------------------------------------------
232 #ifdef MS_DEBUG
233 #define DMD_DBG(x) (x)
234 #else
235 #define DMD_DBG(x) //(x)
236 #endif
237
238 static DMD_DVBT_InitData AgcSsi_Para;
239 //-------------------------------------------------------------------------------------------------
240 // Local Functions
241 //-------------------------------------------------------------------------------------------------
242
243 static void* ppDVBTInstant = NULL;
244 static MS_U32 u32DVBTopen = 0;
245 static MS_U8 u8DVBTUtopiaOpen = 0; //for SetStillImagePara is earlier called than Init
246
247
248 static float fViterbiBerFiltered=-1;
249 //-------------------------------------------------------------------------------------------------
250 // Global Functions
251 //-------------------------------------------------------------------------------------------------
252 #ifndef MSOS_TYPE_LINUX
253 #if 1
254 static float _LogApproxTableX[80] =
255 { 1.00, 1.30, 1.69, 2.20, 2.86, 3.71, 4.83, 6.27, 8.16, 10.60, 13.79,
256 17.92, 23.30, 30.29, 39.37, 51.19, 66.54, 86.50, 112.46, 146.19,
257 190.05, 247.06, 321.18, 417.54, 542.80, 705.64, 917.33, 1192.53,
258 1550.29, 2015.38, 2620.00, 3405.99, 4427.79, 5756.13, 7482.97,
259 9727.86, 12646.22, 16440.08, 21372.11, 27783.74, 36118.86,
260 46954.52, 61040.88, 79353.15, 103159.09, 134106.82, 174338.86,
261 226640.52, 294632.68, 383022.48, 497929.22, 647307.99, 841500.39, 1093950.50,
262 1422135.65, 1848776.35, 2403409.25, 3124432.03, 4061761.64, 5280290.13,
263 6864377.17, 8923690.32, 11600797.42, 15081036.65, 19605347.64, 25486951.94,
264 33133037.52, 43072948.77, 55994833.40, 72793283.42, 94631268.45,
265 123020648.99, 159926843.68, 207904896.79, 270276365.82, 351359275.57,
266 456767058.24, 593797175.72, 771936328.43, 1003517226.96
267 };
268
269 static float _LogApproxTableY[80] =
270 { 0.00, 0.11, 0.23, 0.34, 0.46, 0.57, 0.68, 0.80, 0.91, 1.03, 1.14, 1.25,
271 1.37, 1.48, 1.60, 1.71, 1.82, 1.94, 2.05, 2.16, 2.28, 2.39, 2.51, 2.62,
272 2.73, 2.85, 2.96, 3.08, 3.19, 3.30, 3.42, 3.53, 3.65, 3.76, 3.87, 3.99,
273 4.10, 4.22, 4.33, 4.44, 4.56, 4.67, 4.79, 4.90, 5.01, 5.13, 5.24, 5.36,
274 5.47, 5.58, 5.70, 5.81, 5.93, 6.04, 6.15, 6.27, 6.04, 6.15, 6.27, 6.38,
275 6.49, 6.61, 6.72, 6.84, 6.95, 7.06, 7.18, 7.29, 7.41, 7.52, 7.63, 7.75,
276 7.86, 7.98, 8.09, 8.20, 8.32, 8.43, 8.55, 8.66
277 };
278
Log10Approx(float flt_x)279 static float Log10Approx(float flt_x)
280 {
281 MS_U8 indx = 0;
282
283 do {
284 if (flt_x < _LogApproxTableX[indx])
285 break;
286 indx++;
287 }while (indx < 79); //stop at indx = 80
288
289 return _LogApproxTableY[indx];
290 }
291 #else
Log10Approx(float flt_x)292 static float Log10Approx(float flt_x)
293 {
294 MS_U32 u32_temp = 1;
295 MS_U8 indx = 0;
296
297 do {
298 u32_temp = u32_temp << 1;
299 if (flt_x < (float)u32_temp)
300 break;
301 }while (++indx < 32);
302
303 // 10*log10(X) ~= 0.3*N, when X ~= 2^N
304 return (float)0.3 * indx;
305 }
306 #endif
307 #endif
308
309
310 //bryan waiting for handling
MDrv_DMD_DVBT_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)311 MS_BOOL MDrv_DMD_DVBT_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
312 {
313 MS_BOOL bRet;
314
315 DVBT_GETREG_PARAM Drv_DVBT_GETREG_PARAM;
316 Drv_DVBT_GETREG_PARAM.u16Addr=u16Addr;
317 Drv_DVBT_GETREG_PARAM.pu8Data=pu8Data;
318
319 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_GetReg\n"));
320
321 bRet=UtopiaIoctl(ppDVBTInstant,DMD_DVBT_DRV_CMD_GetReg,&Drv_DVBT_GETREG_PARAM);
322 return bRet;
323 /*
324 DMD_LOCK();
325 bRet=MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr, pu8Data);
326 DMD_UNLOCK();
327
328 #ifdef MS_DEBUG
329 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
330 {
331 ULOGD("DEMOD","MDrv_DMD_DVBT_GetReg %x %x\n", u16Addr, *pu8Data);
332 }
333 #endif
334
335 return bRet;
336 */
337 }
338
MDrv_DMD_DVBT_SetReg(MS_U16 u16Addr,MS_U8 u8Data)339 MS_BOOL MDrv_DMD_DVBT_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
340 {
341 MS_BOOL return_val;
342
343 DVBT_SETREG_PARAM Drv_DVBT_SETREG_PARAM;
344 Drv_DVBT_SETREG_PARAM.u16Addr=u16Addr;
345 Drv_DVBT_SETREG_PARAM.u8Data=u8Data;
346
347
348
349 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_SetReg\n"));
350 return_val=UtopiaIoctl(ppDVBTInstant,DMD_DVBT_DRV_CMD_SetReg,&Drv_DVBT_SETREG_PARAM);
351 return return_val;
352 /*
353 #ifdef MS_DEBUG
354 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
355 {
356 ULOGD("DEMOD","MDrv_DMD_DVBT_SetReg %x %x\n", u16Addr, u8Data);
357 }
358 #endif
359
360 DMD_LOCK();
361 bRet=MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr, u8Data);
362 DMD_UNLOCK();
363 return bRet;
364 */
365 }
366
367
368
369 /*bryan this is need to modified*/
MDrv_DMD_DVBT_Init(DMD_DVBT_InitData * pDMD_DVBT_InitData,MS_U32 u32InitDataLen)370 MS_BOOL MDrv_DMD_DVBT_Init(DMD_DVBT_InitData *pDMD_DVBT_InitData, MS_U32 u32InitDataLen)
371 {
372 // MS_BOOL return_val;
373
374
375 void* pAttribte = NULL;
376
377 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_Init\n"));
378
379 //bryan test
380 #if(0)
381 DVBT_INIT_PARAM Drv_DVBT_INIT_PARAM;
382
383 Drv_DVBT_INIT_PARAM.DMD_DVBT_InitData.u8DMD_DVBT_DSPRegInitExt=pDMD_DVBT_InitData->u8DMD_DVBT_DSPRegInitExt;
384 Drv_DVBT_INIT_PARAM.DMD_DVBT_InitData.u8DMD_DVBT_DSPRegInitSize=pDMD_DVBT_InitData->u8DMD_DVBT_DSPRegInitSize;
385 Drv_DVBT_INIT_PARAM.DMD_DVBT_InitData.u8DMD_DVBT_InitExt=pDMD_DVBT_InitData->u8DMD_DVBT_InitExt;
386 Drv_DVBT_INIT_PARAM.DMD_DVBT_InitData.u8SarChannel=pDMD_DVBT_InitData->u8SarChannel;
387 Drv_DVBT_INIT_PARAM.u32InitDataLen=sizeof(Drv_DVBT_INIT_PARAM.DMD_DVBT_InitData);
388 #else
389 DVBT_INIT_PARAM Drv_DVBT_INIT_PARAM;
390 DMD_DVBT_InitData_Transform Init_Para_Temp;
391 Drv_DVBT_INIT_PARAM.ret=false;
392
393 memcpy (&(AgcSsi_Para), pDMD_DVBT_InitData, sizeof(DMD_DVBT_InitData));
394
395 Init_Para_Temp.u8DMD_DVBT_DSPRegInitExt=pDMD_DVBT_InitData->u8DMD_DVBT_DSPRegInitExt;
396 Init_Para_Temp.u8DMD_DVBT_DSPRegInitSize=pDMD_DVBT_InitData->u8DMD_DVBT_DSPRegInitSize;
397 Init_Para_Temp.u8DMD_DVBT_InitExt=pDMD_DVBT_InitData->u8DMD_DVBT_InitExt;
398 Init_Para_Temp.u8SarChannel=pDMD_DVBT_InitData->u8SarChannel;
399
400 Drv_DVBT_INIT_PARAM.DMD_DVBT_InitData=&Init_Para_Temp;
401 Drv_DVBT_INIT_PARAM.u32InitDataLen=sizeof(Init_Para_Temp);
402 #endif
403
404 //Drv_DVBT_INIT_PARAM.pDMD_DVBT_InitData=pDMD_DVBT_InitData;
405
406 if(u8DVBTUtopiaOpen == 0) // First time open
407 {
408 // if(UtopiaOpen(MODULE_DVBT |KERNEL_MODE, &ppDVBTInstant, 0, pAttribte) == UTOPIA_STATUS_SUCCESS)
409 if(UtopiaOpen(MODULE_DVBT/*|KERNEL_MODE*/ , &ppDVBTInstant, 0, pAttribte) == UTOPIA_STATUS_SUCCESS) //kernel space
410 //if(UtopiaOpen(MODULE_DVBT , &ppDVBTInstant, 0, pAttribte) == UTOPIA_STATUS_SUCCESS) //user space
411 {
412 u32DVBTopen = 1;
413 //return_val=true;
414 //ULOGD("DEMOD","\r\n ======== DVBT Open Successful %x =========", (WORD)u32DVBTopen);
415 }
416 else
417 {
418 // ULOGD("DEMOD","\r\n ======== DVBT Open Fail %x =========", (WORD)u32DVBTopen);
419 //return_val=false;
420
421 return false;
422 }
423
424 u8DVBTUtopiaOpen = 1;
425 }
426
427
428 UtopiaIoctl(ppDVBTInstant,DMD_DVBT_DRV_CMD_Init,&Drv_DVBT_INIT_PARAM);
429 return Drv_DVBT_INIT_PARAM.ret;
430 #if(0)
431 char pDMD_DVBT_MutexString[16];
432 MS_U8 u8ADCIQMode = 0, u8PadSel = 0, bPGAEnable = 0, u8PGAGain = 5;
433 MS_BOOL bRFAGCTristateEnable = 1;
434 MS_BOOL bIFAGCTristateEnable = 0;
435
436 if (_s32DMD_DVBT_Mutex != -1)
437 {
438 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBT_Init more than once\n"));
439 return FALSE;
440 }
441
442 if (NULL == strncpy(pDMD_DVBT_MutexString,"Mutex DMD DVBT",16))
443 {
444 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBT_Init strcpy Fail\n"));
445 return FALSE;
446 }
447 _s32DMD_DVBT_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, pDMD_DVBT_MutexString, MSOS_PROCESS_SHARED);
448 if (_s32DMD_DVBT_Mutex == -1)
449 {
450 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBT_Init Create Mutex Fail\n"));
451 return FALSE;
452 }
453 //_u8DMDDbgLevel = DMD_DBGLV_DEBUG;
454 #ifdef MS_DEBUG
455 if (_u8DMDDbgLevel >= DMD_DBGLV_INFO)
456 {
457 ULOGD("DEMOD","MDrv_DMD_DVBT_Init\n");
458 }
459 #endif
460
461 if ( sizeof(_sDMD_DVBT_InitData) == u32InitDataLen)
462 {
463 memcpy(&_sDMD_DVBT_InitData, pDMD_DVBT_InitData, u32InitDataLen);
464 }
465 else
466 {
467 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBT_Init input data structure incorrect\n"));
468 return FALSE;
469 }
470
471 if (_sDMD_DVBT_InitData.u8SarChannel != 0xFF)
472 {
473 MDrv_SAR_Adc_Config(_sDMD_DVBT_InitData.u8SarChannel, TRUE);
474 }
475
476 DMD_LOCK();
477 MDrv_SYS_DMD_VD_MBX_SetType(E_DMD_VD_MBX_TYPE_DVBT);
478 HAL_DMD_RegInit();
479
480 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
481 {
482 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=2)
483 {
484 bRFAGCTristateEnable = (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[3] & (BIT_(0))) ? TRUE : FALSE; // RFAGC tristate control
485 bIFAGCTristateEnable = (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[3] & (BIT_(4))) ? TRUE : FALSE; // IFAGC tristate control
486 }
487 else
488 {
489 bRFAGCTristateEnable = 1;
490 bIFAGCTristateEnable = 0;
491 }
492 }
493 else
494 {
495 bRFAGCTristateEnable = 1;
496 bIFAGCTristateEnable = 0;
497 }
498
499 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
500 {
501 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=3)
502 {
503 u32DMD_DVBT_IfFrequency = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[4]; // IF frequency
504 u32DMD_DVBT_IfFrequency = (u32DMD_DVBT_IfFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[5]; // IF frequency
505 u32DMD_DVBT_IfFrequency = (u32DMD_DVBT_IfFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[6]; // IF frequency
506 u32DMD_DVBT_IfFrequency = (u32DMD_DVBT_IfFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[7]; // IF frequency
507 u32DMD_DVBT_FsFrequency = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[8]; // FS frequency
508 u32DMD_DVBT_FsFrequency = (u32DMD_DVBT_FsFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[9]; // FS frequency
509 u32DMD_DVBT_FsFrequency = (u32DMD_DVBT_FsFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[10]; // FS frequency
510 u32DMD_DVBT_FsFrequency = (u32DMD_DVBT_FsFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[11]; // FS frequency
511 u8DMD_DVBT_IQSwap = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[12]; // IQ Swap
512
513 u8ADCIQMode = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[13]; // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
514 u8PadSel = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[14]; // u8PadSel : 0=Normal, 1=analog pad
515 bPGAEnable = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[15]; // bPGAEnable : 0=disable, 1=enable
516 u8PGAGain = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[16]; // u8PGAGain : default 5
517 }
518 else
519 {
520
521 }
522 }
523 else
524 {
525
526 }
527 #ifdef MS_DEBUG
528 ULOGD("DEMOD","u32DMD_DVBT_IfFrequency %ld\n",u32DMD_DVBT_IfFrequency);
529 ULOGD("DEMOD","u32DMD_DVBT_FsFrequency %ld\n",u32DMD_DVBT_FsFrequency);
530 ULOGD("DEMOD","u8DMD_DVBT_IQSwap %d\n",u8DMD_DVBT_IQSwap);
531 #endif
532
533 u16DMD_DVBT_TPS_Timeout = 1500;
534 u16DMD_DVBT_FEC_Timeout = 6000;
535 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
536 {
537 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=4)
538 {
539 u16DMD_DVBT_TPS_Timeout = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[17]; // TPS timeout in ms
540 u16DMD_DVBT_TPS_Timeout = (u16DMD_DVBT_TPS_Timeout<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[18];
541 if (u16DMD_DVBT_TPS_Timeout < 700) u16DMD_DVBT_TPS_Timeout=700;
542 //ULOGD("DEMOD","u16DMD_DVBT_TPS_Timeout %d\n",u16DMD_DVBT_TPS_Timeout);
543
544 u16DMD_DVBT_FEC_Timeout = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[19]; // FEC timeout in ms
545 u16DMD_DVBT_FEC_Timeout = (u16DMD_DVBT_FEC_Timeout<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[20];
546 if (u16DMD_DVBT_FEC_Timeout < 2500) u16DMD_DVBT_FEC_Timeout=2500;
547 //ULOGD("DEMOD","u16DMD_DVBT_FEC_Timeout %d\n",u16DMD_DVBT_FEC_Timeout);
548 }
549 else
550 {
551 }
552 }
553 else
554 {
555 }
556
557 if (bIFAGCTristateEnable)
558 {
559 MDrv_SYS_SetAGCPadMux(E_SYS_DTV_AGC_PAD_SET_ALL_OFF);
560 }
561 else
562 {
563 MDrv_SYS_SetAGCPadMux(E_SYS_DTV_AGC_PAD_SET);
564 }
565
566
567 // oga
568 DVBT_TS_PHASE_EN =0;
569 DVBT_TS_PHASE_NUM = 0;
570 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
571 {
572 /*
573 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=5) // version bigger than 5, apply TS phase solution
574 {
575 DVBT_TS_PHASE_EN = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[INDEX_T_TS_PHASE_EN];
576 DVBT_TS_PHASE_NUM = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[INDEX_T_TS_PHASE_NUM];
577 ULOGD("DEMOD","##DVBT:TS check: bTsPhaseEn = %d, u16TsPhaseNum = %d\n",DVBT_TS_PHASE_EN,DVBT_TS_PHASE_NUM);
578 }
579 else
580 {
581 ULOGD("DEMOD","##DVBT:TS Phase check !!, board version smaller than 4\n");
582 }
583 */
584 }
585 else // if init board define is NULL TS phase needs check.
586 {
587 ULOGD("DEMOD","##DVBT:TS Phase check !!\n");
588 }
589
590
591
592 if (_sDMD_DVBT_InitData.u8DMD_DVBT_DSPRegInitExt != NULL)
593 {
594 if (_sDMD_DVBT_InitData.u8DMD_DVBT_DSPRegInitExt[0]>=1)
595 {
596 INTERN_DVBT_Power_On_Initialization(bRFAGCTristateEnable, u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain, _sDMD_DVBT_InitData.u8DMD_DVBT_DSPRegInitExt, _sDMD_DVBT_InitData.u8DMD_DVBT_DSPRegInitSize);
597 }
598 else
599 {
600 ULOGD("DEMOD","u8DMD_DVBT_DSPRegInitExt Error\n");
601 }
602 }
603 else
604 {
605 INTERN_DVBT_Power_On_Initialization(bRFAGCTristateEnable, u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain, NULL, 0);
606 }
607
608 INTERN_DVBT_Version(&sDMD_DVBT_Info.u16Version);
609 DMD_UNLOCK();
610 #ifdef MS_DEBUG
611 ULOGD("DEMOD","firmware version: %x\n",sDMD_DVBT_Info.u16Version);
612 #endif
613 return TRUE;
614 #endif
615 }
616
MDrv_DMD_DVBT_Exit(void)617 MS_BOOL MDrv_DMD_DVBT_Exit(void)
618 {
619 //bryan:return value need to be checked
620 //MS_BOOL return_val;
621 /*
622 #ifdef MS_DEBUG
623 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
624 {
625 ULOGD("DEMOD","MDrv_DMD_DVBT_Exit\n");
626 }
627 #endif
628
629 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_Exit\n"));
630
631 DMD_LOCK();
632 INTERN_DVBT_Exit();
633 DMD_UNLOCK();
634 MsOS_DeleteMutex(_s32DMD_DVBT_Mutex);
635 _s32DMD_DVBT_Mutex= -1;
636 return TRUE;
637 */
638 DVBT_EXIT_PARAM Drv_DVBT_EXIT_PARAM;
639 Drv_DVBT_EXIT_PARAM.ret=false;
640 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_Exit\n"));
641
642 if(u32DVBTopen==1)
643 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_Exit, &Drv_DVBT_EXIT_PARAM);
644 else
645 return false;
646
647 return Drv_DVBT_EXIT_PARAM.ret;
648 }
649
MDrv_DMD_DVBT_GetConfig(DMD_DVBT_InitData * pDMD_DVBT_InitData)650 MS_U32 MDrv_DMD_DVBT_GetConfig(DMD_DVBT_InitData *pDMD_DVBT_InitData)
651 {
652 if (!u32DVBTopen) return FALSE;
653
654 memcpy (pDMD_DVBT_InitData, &(AgcSsi_Para), sizeof(DMD_DVBT_InitData));
655
656 return UTOPIA_STATUS_SUCCESS;
657 }
658
MDrv_DMD_DVBT_SetDbgLevel(DMD_DbgLv u8DbgLevel)659 MS_BOOL MDrv_DMD_DVBT_SetDbgLevel(DMD_DbgLv u8DbgLevel)
660 {
661 //MS_BOOL return_val;
662 DVBT_SETDBG_LEVEL_PARAM Drv_DVBT_SETDBG_LEVEL_PARAM;
663 Drv_DVBT_SETDBG_LEVEL_PARAM.u8DbgLevel=u8DbgLevel;
664 Drv_DVBT_SETDBG_LEVEL_PARAM.ret=false;
665
666
667 /*
668 DMD_LOCK();
669 _u8DMDDbgLevel = u8DbgLevel;
670 DMD_UNLOCK();
671 return TRUE;
672 */
673 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_SetDbgLevel\n"));
674
675 if(u32DVBTopen==1)
676 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_SetDbgLeve, &Drv_DVBT_SETDBG_LEVEL_PARAM);
677 else
678 return false;
679
680 return Drv_DVBT_SETDBG_LEVEL_PARAM.ret;
681 }
682
MDrv_DMD_DVBT_GetInfo(DMD_DVBT_INFO_TYPE eInfoType)683 DMD_DVBT_Info* MDrv_DMD_DVBT_GetInfo(DMD_DVBT_INFO_TYPE eInfoType)
684 {
685 //MS_BOOL return_val;
686 DVBT_GETINFO_PARAM Drv_DVBT_GETINFO_PARAM;
687 Drv_DVBT_GETINFO_PARAM.eInfoType=eInfoType;
688 Drv_DVBT_GETINFO_PARAM.pInfo=NULL;
689
690 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_GetInfo\n"));
691
692 if(u32DVBTopen==1)
693 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_GetInfo, &Drv_DVBT_GETINFO_PARAM);
694
695
696 return Drv_DVBT_GETINFO_PARAM.pInfo;
697 #if(0)
698 DMD_LOCK();
699 switch (eInfoType)
700 {
701 case E_DMD_DVBT_MODULATION_INFO:
702 INTERN_DVBT_Show_Modulation_info();
703 break;
704 case E_DMD_DVBT_DEMOD_INFO:
705 INTERN_DVBT_Show_Demod_Info();
706 break;
707 case E_DMD_DVBT_LOCK_INFO:
708 INTERN_DVBT_Show_Lock_Info();
709 break;
710 case E_DMD_DVBT_PRESFO_INFO:
711 INTERN_DVBT_Show_PRESFO_Info();
712 break;
713 case E_DMD_DVBT_LOCK_TIME_INFO:
714 INTERN_DVBT_Show_Lock_Time_Info();
715 break;
716 case E_DMD_DVBT_BER_INFO:
717 INTERN_DVBT_Show_BER_Info();
718 break;
719 case E_DMD_DVBT_AGC_INFO:
720 INTERN_DVBT_Show_AGC_Info();
721 break;
722 default:
723 #ifdef MS_DEBUG
724 ULOGD("DEMOD","MDrv_DMD_DVBT_GetInfo %d Error\n", eInfoType);
725 #endif
726 break;
727 }
728 DMD_UNLOCK();
729 return &sDMD_DVBT_Info;
730
731 #endif
732 }
733
MDrv_DMD_DVBT_GetLibVer(const MSIF_Version ** ppVersion)734 MS_BOOL MDrv_DMD_DVBT_GetLibVer(const MSIF_Version **ppVersion)
735 {
736 DVBT_GETLIBVER_PARAM Drv_DVBT_GETLIBVER_PARAM;
737 Drv_DVBT_GETLIBVER_PARAM.ppVersion=ppVersion;
738 Drv_DVBT_GETLIBVER_PARAM.ret=false;
739
740 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_GetLibVer\n"));
741 if(u32DVBTopen==1)
742 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_GetLibVer, &Drv_DVBT_GETLIBVER_PARAM);
743 else
744 return false;
745
746 return Drv_DVBT_GETLIBVER_PARAM.ret;
747
748
749 /*
750 DMD_LOCK();
751 if (!ppVersion)
752 {
753 return FALSE;
754 }
755
756 *ppVersion = &_drv_dmd_dvbt_intern_version;
757 DMD_UNLOCK();
758 return TRUE;
759 */
760 }
761
MDrv_DMD_DVBTGetFWVer(MS_U16 * ver)762 MS_BOOL MDrv_DMD_DVBTGetFWVer(MS_U16 *ver)
763 {
764 //MS_BOOL return_val;
765 DVBT_GETFWVER_PARAM Drv_DVBT_GETFWVER_PARAM;
766 Drv_DVBT_GETFWVER_PARAM.ver=ver;
767 Drv_DVBT_GETFWVER_PARAM.ret=false;
768
769 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBTGetFWVer\n"));
770 if(u32DVBTopen==1)
771 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_GetFWVer, &Drv_DVBT_GETFWVER_PARAM);
772 else
773 return false;
774
775 return Drv_DVBT_GETFWVER_PARAM.ret;
776 /*
777 MS_BOOL bRet;
778
779 DMD_LOCK();
780
781 bRet = INTERN_DVBT_Version(ver);
782 //ULOGD("DEMOD","MDrv_DMD_DVBT_GetFWVer %x\n",*ver);
783 DMD_UNLOCK();
784
785 return bRet;
786 */
787 }
788
789
MDrv_DMD_DVBT_SetSerialControl(MS_BOOL bEnable)790 MS_BOOL MDrv_DMD_DVBT_SetSerialControl(MS_BOOL bEnable)
791 {
792 //MS_BOOL return_val;
793 DVBT_SetSerialControl_PARAM Drv_DVBT_SetSerialControl_PARAM;
794 Drv_DVBT_SetSerialControl_PARAM.bEnable=bEnable;
795 Drv_DVBT_SetSerialControl_PARAM.ret=false;
796
797 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_SetSerialControl\n"));
798
799 if(u32DVBTopen==1)
800 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_SetSerialControl, &Drv_DVBT_SetSerialControl_PARAM);
801 else
802 return false;
803
804 return Drv_DVBT_SetSerialControl_PARAM.ret;
805 /*
806 MS_BOOL bRet;
807 MS_U8 u8TSClk;
808
809 #ifdef MS_DEBUG
810 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
811 {
812 ULOGD("DEMOD","MDrv_DMD_DVBT_SetSerialControl %x\n", bEnable);
813 }
814 #endif
815
816 DMD_LOCK();
817 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
818 {
819 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=1)
820 {
821 u8TSClk = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[2]; // TS_CLK
822 }
823 else
824 {
825 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
826 }
827 }
828 else
829 {
830 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
831 }
832 bRet=INTERN_DVBT_Serial_Control(bEnable, u8TSClk);
833 DMD_UNLOCK();
834 return bRet;
835 */
836 }
837
MDrv_DMD_DVBT_SetConfig(DMD_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_BOOL bPalBG)838 MS_BOOL MDrv_DMD_DVBT_SetConfig(DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG)
839 {
840 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_SetConfig\n"));
841
842 return MDrv_DMD_DVBT_SetConfigHPLPSetIF(BW, bSerialTS, bPalBG, 0, u32DMD_DVBT_IfFrequency, u32DMD_DVBT_FsFrequency, u8DMD_DVBT_IQSwap);
843 }
844
845
MDrv_DMD_DVBT_SetConfigHPLP(DMD_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_BOOL bPalBG,MS_BOOL bLPSel)846 MS_BOOL MDrv_DMD_DVBT_SetConfigHPLP(DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel)
847 {
848 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_SetConfigHPLP\n"));
849
850 return MDrv_DMD_DVBT_SetConfigHPLPSetIF(BW, bSerialTS, bPalBG, bLPSel, u32DMD_DVBT_IfFrequency, u32DMD_DVBT_FsFrequency, u8DMD_DVBT_IQSwap);
851 }
852
853
MDrv_DMD_DVBT_SetConfigHPLPSetIF(DMD_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_BOOL bPalBG,MS_BOOL bLPSel,MS_U32 u32IFFreq,MS_U32 u32FSFreq,MS_U8 u8IQSwap)854 MS_BOOL MDrv_DMD_DVBT_SetConfigHPLPSetIF(DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel, MS_U32 u32IFFreq, MS_U32 u32FSFreq, MS_U8 u8IQSwap)
855 {
856 //MS_BOOL return_val;
857 DVBT_SetConfigHPLPSetIF_PARAM Drv_DVBT_SetConfigHPLPSetIF_PARAM;
858 Drv_DVBT_SetConfigHPLPSetIF_PARAM.BW=BW;
859 Drv_DVBT_SetConfigHPLPSetIF_PARAM.bSerialTS=bSerialTS;
860 Drv_DVBT_SetConfigHPLPSetIF_PARAM.bPalBG=bPalBG;
861 Drv_DVBT_SetConfigHPLPSetIF_PARAM.bLPSel=bLPSel;
862 Drv_DVBT_SetConfigHPLPSetIF_PARAM.u32IFFreq=u32IFFreq;
863 Drv_DVBT_SetConfigHPLPSetIF_PARAM.u32FSFreq=u32FSFreq;
864 Drv_DVBT_SetConfigHPLPSetIF_PARAM.u8IQSwap=u8IQSwap;
865 Drv_DVBT_SetConfigHPLPSetIF_PARAM.ret=false;
866
867 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_SetConfigHPLPSetIF\n"));
868
869 if(u32DVBTopen==1)
870 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_SetConfigHPLPSetIF, &Drv_DVBT_SetConfigHPLPSetIF_PARAM);
871 else
872 return false;
873
874 return Drv_DVBT_SetConfigHPLPSetIF_PARAM.ret;
875
876 /*
877 MS_BOOL bRet;
878 MS_U8 u8TSClk;
879
880 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_SetConfigHPLPSetIF\n"));
881
882 #ifdef MS_DEBUG
883 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
884 {
885 ULOGD("DEMOD","MDrv_DMD_DVBT_SetConfigHPLPSetIF %d %d %d %d %ld %ld %d\n", BW, bSerialTS, bPalBG, bLPSel, u32IFFreq, u32FSFreq, u8IQSwap);
886 }
887 #endif
888
889 DMD_LOCK();
890 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
891 {
892 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=1)
893 {
894 u8TSClk = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[2]; // TS_CLK
895 }
896 else
897 {
898 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
899 }
900 }
901 else
902 {
903 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
904 }
905
906 bRet=INTERN_DVBT_Config(BW, bSerialTS, bPalBG, bLPSel, u8TSClk, u32IFFreq, u32FSFreq, u8IQSwap);
907 eDMD_DVBT_BandWidth=BW;
908 DMD_UNLOCK();
909 return bRet;
910
911 */
912 }
913
MDrv_DMD_DVBT_SetActive(MS_BOOL bEnable)914 MS_BOOL MDrv_DMD_DVBT_SetActive(MS_BOOL bEnable)
915 {
916 //MS_BOOL return_val;
917 DVBT_SetActive_PARAM Drv_DVBT_SetActive_PARAM;
918 Drv_DVBT_SetActive_PARAM.bEnable=bEnable;
919 Drv_DVBT_SetActive_PARAM.ret=false;
920
921 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_SetActive\n"));
922 if(u32DVBTopen==1)
923 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_SetActive, &Drv_DVBT_SetActive_PARAM);
924 else
925 return false;
926
927 return Drv_DVBT_SetActive_PARAM.ret;
928 /*
929 MS_BOOL bRet;
930
931 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_SetActive\n"));
932
933 #ifdef MS_DEBUG
934 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
935 {
936 ULOGD("DEMOD","MDrv_DMD_DVBT_SetActive %d\n", bEnable);
937 }
938 #endif
939
940 DMD_LOCK();
941 bRet=INTERN_DVBT_Active(bEnable);
942 DMD_UNLOCK();
943 return bRet;
944 */
945
946 }
947
MDrv_DMD_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eType,DMD_LOCK_STATUS * eLockStatus)948 MS_BOOL MDrv_DMD_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eType, DMD_LOCK_STATUS *eLockStatus)
949 {
950 //MS_BOOL return_val;
951 DVBT_GetLock_PARAM Drv_DVBT_GetLock_PARAM;
952 Drv_DVBT_GetLock_PARAM.eType=eType;
953 Drv_DVBT_GetLock_PARAM.eLockStatus=eLockStatus;
954 Drv_DVBT_GetLock_PARAM.ret=false;
955 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_GetLock\n"));
956
957 if(u32DVBTopen==1)
958 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_GetLock, &Drv_DVBT_GetLock_PARAM);
959 else
960 return false;
961
962 return Drv_DVBT_GetLock_PARAM.ret;
963 }
964
965 #ifndef MSOS_TYPE_LINUX_KERNEL
MDrv_DMD_DVBT_GetSignalStrength(MS_U16 * u16Strength)966 MS_BOOL MDrv_DMD_DVBT_GetSignalStrength(MS_U16 *u16Strength)
967 {
968 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_GetSignalStrength\n"));
969
970 return MDrv_DMD_DVBT_GetSignalStrengthWithRFPower(u16Strength, 200.0f);
971 }
972 #endif
973
974 #ifndef MSOS_TYPE_LINUX_KERNEL
MDrv_DMD_DVBT_GetSignalStrengthWithRFPower(MS_U16 * u16Strength,float fRFPowerDbm)975 MS_BOOL MDrv_DMD_DVBT_GetSignalStrengthWithRFPower(MS_U16 *u16Strength, float fRFPowerDbm)
976 {
977
978 MS_BOOL status = true;
979 DMD_IFAGC_SSI *ifagc_ssi;
980 DMD_IFAGC_ERR *ifagc_err;
981 float ch_power_rf=0.0f;
982 float ch_power_db=0.0f, ch_power_db_rel=0.0f;
983 float ch_power_if=0.0f, ch_power_ifa = 0.0f, ch_power_ifb =0.0f;
984 float ch_power_ref = 11.0f;
985 MS_U16 if_agc_val =0, if_agc_vala =0, if_agc_valb =0, if_agc_val_lsb =0, i;
986 float ch_power_takeover=0.0f;
987 MS_U8 ssi_tbl_len = 0, err_tbl_len = 0;
988
989 MS_U8 ifagc_reg;
990 MS_U8 ifagc_reg_lsb;
991 MS_U16 ifagc_err_reg;
992 MS_U8 u8_index = 0;
993 MS_U16 tps_info_qam = 0,tps_info_cr = 0;
994
995 //DVBT_GetSignalStrengthWithRFPower_PARAM Drv_DVBT_GetSignalStrengthWithRFPower_PARAM;
996 //Drv_DVBT_GetSignalStrengthWithRFPower_PARAM.u16Strength=u16Strength;
997 //Drv_DVBT_GetSignalStrengthWithRFPower_PARAM.fRFPowerDbm=fRFPowerDbm;
998
999 DVBT_GetIFAGC_PARAM Drv_DVBT_GetIFAGC_PARAM;
1000 Drv_DVBT_GetIFAGC_PARAM.ifagc_reg=&ifagc_reg;
1001 Drv_DVBT_GetIFAGC_PARAM.ifagc_reg_lsb=&ifagc_reg_lsb;
1002 Drv_DVBT_GetIFAGC_PARAM.ifagc_err_reg=&ifagc_err_reg;
1003 Drv_DVBT_GetIFAGC_PARAM.ret=false;
1004
1005 if(u32DVBTopen==1)
1006 {
1007 if((AgcSsi_Para.pTuner_IfagcSsi_HiRef != NULL) && (AgcSsi_Para.pTuner_IfagcSsi_LoRef != NULL))
1008 {
1009 UtopiaIoctl(ppDVBTInstant,DMD_DVBT_DRV_CMD_GetIFAGC,&Drv_DVBT_GetIFAGC_PARAM);
1010 status &= Drv_DVBT_GetIFAGC_PARAM.ret;
1011 ch_power_rf = fRFPowerDbm;
1012
1013 if_agc_val = ifagc_reg;
1014 if_agc_val_lsb = ifagc_reg_lsb;
1015
1016 ifagc_ssi = AgcSsi_Para.pTuner_IfagcSsi_LoRef;
1017 ssi_tbl_len = AgcSsi_Para.u16Tuner_IfagcSsi_LoRef_Size;
1018 ifagc_err = AgcSsi_Para.pTuner_IfagcErr_LoRef;
1019 err_tbl_len = AgcSsi_Para.u16Tuner_IfagcErr_LoRef_Size;
1020
1021 ch_power_if=ifagc_ssi[0].power_db;
1022 if (if_agc_val >=ifagc_ssi[0].agc_val)
1023 {
1024 for(i = 1; i < ssi_tbl_len; i++)
1025 {
1026 if (if_agc_val < ifagc_ssi[i].agc_val)
1027 {
1028 if_agc_valb = ifagc_ssi[i].agc_val;
1029 ch_power_ifb = ifagc_ssi[i].power_db;
1030
1031 i--;
1032 if_agc_vala = ifagc_ssi[i].agc_val;
1033 ch_power_ifa=ifagc_ssi[i].power_db;
1034 while ((i>1) && (if_agc_vala==ifagc_ssi[i-1].agc_val))
1035 {
1036 ch_power_ifa=ifagc_ssi[i-1].power_db;
1037 i--;
1038 }
1039 ch_power_if = ch_power_ifa+(ch_power_ifb-ch_power_ifa)*(float)((if_agc_val-if_agc_vala)*256+if_agc_val_lsb)/((if_agc_valb-if_agc_vala)*256);
1040 break;
1041 }
1042 }
1043 }
1044 #ifdef MS_DEBUG
1045 ULOGD("DEMOD","if prev %f %x\n", ch_power_ifa, if_agc_vala);
1046 ULOGD("DEMOD","if next %f %x\n", ch_power_ifb, if_agc_valb);
1047 #endif
1048
1049 for(i = 0; i < ssi_tbl_len; i++)
1050 {
1051 if (ifagc_ssi[i].agc_val <= ifagc_ssi[i+1].agc_val)
1052 {
1053 ch_power_takeover = ifagc_ssi[i+1].power_db;
1054 break;
1055 }
1056 }
1057
1058 #ifdef MS_DEBUG
1059 ULOGD("DEMOD","ch_power_rf = %f\n", ch_power_rf);
1060 ULOGD("DEMOD","ch_power_if = %f\n", ch_power_if);
1061 ULOGD("DEMOD","ch_power_takeover = %f\n", ch_power_takeover);
1062 #endif
1063
1064 // ch_power_db = (ch_power_rf > ch_power_if)? ch_power_rf : ch_power_if;
1065
1066 if(ch_power_rf > (ch_power_takeover + 0.5))
1067 {
1068 ch_power_db = ch_power_rf;
1069 }
1070 else if(ch_power_if < (ch_power_takeover - 0.5))
1071 {
1072 ch_power_db = ch_power_if;
1073 }
1074 else
1075 {
1076 ch_power_db = (ch_power_if + ch_power_rf)/2;
1077 }
1078
1079 // ch_power_db = (ch_power_rf > ch_power_if)? ch_power_if : ch_power_rf;
1080
1081 if(if_agc_val == 0xff)
1082 {
1083 for(i = 0; i < err_tbl_len; i++)
1084 {
1085 if ( ifagc_err_reg <= ifagc_err[i].agc_err ) // signed char comparison
1086 {
1087 ch_power_db += ifagc_err[i].attn_db;
1088 break;
1089 }
1090 }
1091 #ifdef MS_DEBUG
1092 ULOGD("DEMOD","if_agc_err = 0x%x\n", ifagc_err_reg);
1093 #endif
1094 }
1095 }
1096 else
1097 {
1098 #ifdef MS_DEBUG
1099 if (fRFPowerDbm>=100.0) // unreasonable input value, get RF level from RFAGG
1100 {
1101 ULOGD("DEMOD","Error!! please add AGC table\n");
1102 }
1103 #endif
1104 ch_power_db = fRFPowerDbm; // from tuner
1105 }
1106
1107
1108 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_qam, TS_MODUL_MODE) == FALSE)
1109 printf("[dvbt]TPS qam parameter retrieve failure\n");
1110
1111 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_cr, TS_CODE_RATE) == FALSE)
1112 printf("[dvbt]TPS cr parameter retrieve failure\n");
1113
1114 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
1115 {
1116 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)tps_info_qam)
1117 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)tps_info_cr))
1118 {
1119 ch_power_ref = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
1120 break;
1121 }
1122 else
1123 {
1124 u8_index++;
1125 }
1126 }
1127
1128 if (ch_power_ref > 10.0f)
1129 *u16Strength = 0;
1130 else
1131 {
1132 ch_power_db_rel = ch_power_db - ch_power_ref;
1133
1134 if ( ch_power_db_rel < -15.0f )
1135 {
1136 *u16Strength = 0;
1137 }
1138 else if ( ch_power_db_rel < 0.0f )
1139 {
1140 *u16Strength = (MS_U16)(2.0f/3*(ch_power_db_rel + 15.0f));
1141 }
1142 else if ( ch_power_db_rel < 20 )
1143 {
1144 *u16Strength = (MS_U16)(4.0f*ch_power_db_rel + 10.0f);
1145 }
1146 else if ( ch_power_db_rel < 35.0f )
1147 {
1148 *u16Strength = (MS_U16)(2.0f/3*(ch_power_db_rel - 20.0f) + 90.0f);
1149 }
1150 else
1151 {
1152 *u16Strength = 100;
1153 }
1154 }
1155
1156 DMD_DBG(ULOGD("DEMOD",">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *u16Strength));
1157 DMD_DBG(ULOGD("DEMOD",">>> SSI = %d <<<\n", (int)*u16Strength));
1158
1159 return status;
1160 }
1161 else
1162 {
1163 return false;
1164 }
1165
1166 return status;
1167
1168 }
1169 #endif
1170
1171 #ifndef MSOS_TYPE_LINUX_KERNEL
MDrv_DMD_DVBT_GetSignalQuality(MS_U16 * u16Quality)1172 MS_BOOL MDrv_DMD_DVBT_GetSignalQuality(MS_U16 *u16Quality)
1173 {
1174 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_GetSignalQuality\n"));
1175
1176 return MDrv_DMD_DVBT_GetSignalQualityWithRFPower(u16Quality, 200.0f);
1177 }
1178 #endif
1179
1180 #ifndef MSOS_TYPE_LINUX_KERNEL
MDrv_DMD_DVBT_GetSignalQualityWithRFPower(MS_U16 * u16Quality,float fRFPowerDbm)1181 MS_BOOL MDrv_DMD_DVBT_GetSignalQualityWithRFPower(MS_U16 *u16Quality, float fRFPowerDbm)
1182 {
1183 float ber_sqi;
1184 float fber;
1185 float cn_rec = 0;
1186 float cn_nordig_p1 = 0;
1187 float cn_rel = 0;
1188
1189 MS_U8 status = true;
1190 MS_U8 tps_cnstl = 0, tps_cr = 0, i = 0;
1191 MS_U16 u16_tmp;
1192 DMD_LOCK_STATUS eLockStatus = E_DMD_CHECKING;
1193
1194 if(u32DVBTopen==1)
1195 {
1196 MDrv_DMD_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK, &eLockStatus);
1197 if(E_DMD_LOCK == eLockStatus)
1198 {
1199 #if 0
1200 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1201 {
1202 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
1203 }
1204 #endif
1205 ///////// Get Pre-RS (Post-Viterbi) BER to determine BER_SQI //////////
1206 MDrv_DMD_DVBT_GetPostViterbiBer(&fViterbiBerFiltered);
1207 if(fViterbiBerFiltered<= 0.0)
1208 {
1209 if (MDrv_DMD_DVBT_GetPostViterbiBer(&fber) == FALSE)
1210 {
1211 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBT_GetPostViterbiBer \n "));
1212 return FALSE;
1213 }
1214 fViterbiBerFiltered = fber;
1215 }
1216 else
1217 {
1218 fber = fViterbiBerFiltered;
1219 }
1220
1221 if (fber > 1.0E-3)
1222 ber_sqi = 0.0;
1223 else if (fber > 8.5E-7)
1224 #ifdef MSOS_TYPE_LINUX
1225 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
1226 #else
1227 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
1228 #endif
1229 else
1230 ber_sqi = 100.0;
1231
1232 MDrv_DMD_DVBT_GetSNR(&cn_rec);
1233
1234 if (cn_rec == -1) //get SNR return fail
1235 status = false;
1236
1237 #if 0 // temp mark
1238 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
1239 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
1240 tps_cnstl = 0xff;
1241 tps_cr = 0xff;
1242 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_MODUL_MODE) == TRUE)
1243 tps_cnstl = (MS_U8)u16_tmp&0x07;
1244 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_CODE_RATE) == TRUE)
1245 tps_cr = (MS_U8)u16_tmp&0x07;
1246
1247 for(i = 0; i < sDMD_DVBT_InitData->u16SqiCnNordigP1_Size; i++)
1248 {
1249 if ( (tps_cnstl == sDMD_DVBT_InitData->pSqiCnNordigP1[i].constel)
1250 && (tps_cr == sDMD_DVBT_InitData->pSqiCnNordigP1[i].code_rate) )
1251 {
1252 cn_nordig_p1 = sDMD_DVBT_InitData->pSqiCnNordigP1[i].cn_ref;
1253 break;
1254 }
1255 }
1256
1257 // 0,5, snr offset
1258 cn_rel = cn_rec - cn_nordig_p1 + 0.5f;
1259
1260 // patch....
1261 // Noridg SQI,
1262 // 64QAM, CR34, GI14, SNR 22dB.
1263 if ( (tps_cnstl == _64QAM) && (tps_cr == _CR3Y4)
1264 && (cn_rel < 2.5f) && (cn_rel > 1.5f))
1265 {
1266 cn_rel += 1.5f;
1267 }
1268
1269 if (cn_rel < -7.0f)
1270 {
1271 *quality = 0;
1272 }
1273 else if (cn_rel < 3.0)
1274 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
1275 else
1276 *quality = (MS_U16)ber_sqi;
1277 #else
1278 tps_cnstl = 0xff;
1279 tps_cr = 0xff;
1280 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_MODUL_MODE) == TRUE)
1281 tps_cnstl = (MS_U8)u16_tmp&0x07;
1282 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_CODE_RATE) == TRUE)
1283 tps_cr = (MS_U8)u16_tmp&0x07;
1284
1285 for(i = 0; i < (sizeof(SqiCnNordigP1) / sizeof(DMD_SQI_CN_NORDIGP1)); i++)
1286 {
1287 if ( (tps_cnstl == SqiCnNordigP1[i].constel)
1288 && (tps_cr == SqiCnNordigP1[i].code_rate) )
1289 {
1290 cn_nordig_p1 = SqiCnNordigP1[i].cn_ref;
1291 break;
1292 }
1293 }
1294
1295 cn_rel = cn_rec - cn_nordig_p1 + 0.5f;
1296
1297 // patch....
1298 // Noridg SQI,
1299 // 64QAM, CR34, GI14, SNR 22dB.
1300 if ( (tps_cnstl == _64QAM) && (tps_cr == _CR3Y4)
1301 && (cn_rel < 2.5f) && (cn_rel > 1.5f))
1302 {
1303 cn_rel += 1.5f;
1304 }
1305
1306 if (cn_rel < -7.0f)
1307 {
1308 *u16Quality = 0;
1309 }
1310 else if (cn_rel < 3.0)
1311 *u16Quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
1312 else
1313 *u16Quality = (MS_U16)ber_sqi;
1314
1315 #endif
1316 }
1317 else
1318 {
1319 *u16Quality = 0;
1320 }
1321
1322 DMD_DBG(ULOGD("DEMOD","BER = %8.3e\n", fber));
1323 DMD_DBG(ULOGD("DEMOD","Signal Quility = %d\n", *u16Quality));
1324
1325 return status;
1326 }
1327
1328 return status;
1329 }
1330 #endif
1331
1332
1333 #ifndef MSOS_TYPE_LINUX_KERNEL
MDrv_DMD_DVBT_GetSNR(float * fSNR)1334 MS_BOOL MDrv_DMD_DVBT_GetSNR(float *fSNR)
1335 {
1336
1337 MS_U32 noise_power = 0;
1338
1339 DVBT_GetSNR_PARAM Drv_DVBT_GetSNR_PARAM;
1340 Drv_DVBT_GetSNR_PARAM.noise_power_reg = &noise_power;
1341 Drv_DVBT_GetSNR_PARAM.ret = false;
1342
1343 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_GetSNR\n"));
1344
1345 if(u32DVBTopen==1)
1346 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_GetSNR, &Drv_DVBT_GetSNR_PARAM);
1347 else
1348 return false;
1349
1350 // caluate snr by noise power.
1351
1352 noise_power = noise_power/2;
1353 noise_power /=1280;
1354
1355 if (noise_power==0)//protect value 0
1356 noise_power=1;
1357
1358 #ifdef MSOS_TYPE_LINUX
1359 *fSNR = 10*log10f((float)noise_power);
1360 #else
1361 *fSNR = 10*Log10Approx((float)noise_power);
1362 #endif
1363
1364 return Drv_DVBT_GetSNR_PARAM.ret;
1365 }
1366 #endif
1367
1368 #ifndef MSOS_TYPE_LINUX_KERNEL
MDrv_DMD_DVBT_GetPostViterbiBer(float * ber)1369 MS_BOOL MDrv_DMD_DVBT_GetPostViterbiBer(float *ber)
1370 {
1371 //DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_GetPostViterbiBer\n"));
1372
1373 //MS_BOOL status = true;
1374 //MS_U8 reg=0, reg_frz=0;
1375 MS_U16 BitErrPeriod;
1376 MS_U32 BitErr;
1377 MS_U16 PktErr;
1378
1379 DVBT_GetPostViterbiBer_PARAM Drv_DVBT_GetPostViterbiBer_PARAM;
1380 Drv_DVBT_GetPostViterbiBer_PARAM.BitErr_reg = &BitErr;
1381 Drv_DVBT_GetPostViterbiBer_PARAM.BitErrPeriod_reg = &BitErrPeriod;
1382 Drv_DVBT_GetPostViterbiBer_PARAM.PktErr_reg= &PktErr;
1383 Drv_DVBT_GetPostViterbiBer_PARAM.ret=false;
1384
1385 if(u32DVBTopen==1)
1386 {
1387 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_GetPostViterbiBer, &Drv_DVBT_GetPostViterbiBer_PARAM);
1388
1389 /////////// Post-Viterbi BER /////////////
1390 #if 0
1391 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1392 {
1393 *ber = (float)-1.0;
1394 return false;
1395 }
1396 #endif
1397
1398 if (BitErrPeriod == 0 ) //protect 0
1399 BitErrPeriod = 1;
1400
1401 if (BitErr <=0 )
1402 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1403 else
1404 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1405
1406 //DBG_GET_SIGNAL(ULOGD("DEMOD","INTERN_DVBT PostVitBER = %8.3e \n ", *ber));
1407 //DBG_GET_SIGNAL(ULOGD("DEMOD","INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1408
1409 return Drv_DVBT_GetPostViterbiBer_PARAM.ret;
1410
1411 }
1412 else
1413 {
1414 return false;
1415 }
1416 }
1417 #endif
1418
1419 #ifndef MSOS_TYPE_LINUX_KERNEL
MDrv_DMD_DVBT_GetPreViterbiBer(float * ber)1420 MS_BOOL MDrv_DMD_DVBT_GetPreViterbiBer(float *ber)
1421 {
1422 // MS_BOOL return_val;
1423 /*bryan temp mark*/
1424 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_GetPreViterbiBer\n"));
1425
1426 #if(0)
1427 DVBT_GetPreViterbiBer_PARAM Drv_DVBT_GetPreViterbiBer_PARAM;
1428 Drv_DVBT_GetPreViterbiBer_PARAM.ber=ber;
1429 #endif
1430
1431 //bryan temp mark
1432 #if(0)
1433 if(u32DVBTopen==1)
1434 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_GetPreViterbiBer, &Drv_DVBT_GetPreViterbiBer_PARAM);
1435 else
1436 return false;
1437
1438 return Drv_DVBT_GetPreViterbiBer_PARAM.ret;
1439 #else
1440 *ber=0;
1441 return true;
1442 #endif
1443
1444
1445 /*
1446 MS_BOOL bRet;
1447
1448 DMD_LOCK();
1449 bRet=INTERN_DVBT_GetPreViterbiBer(ber);
1450 DMD_UNLOCK();
1451
1452 return bRet;
1453 */
1454 }
1455 #endif
1456
1457
MDrv_DMD_DVBT_GetPacketErr(MS_U16 * pktErr)1458 MS_BOOL MDrv_DMD_DVBT_GetPacketErr(MS_U16 *pktErr)
1459 {
1460 // MS_BOOL return_val;
1461 DVBT_GetPacketErr_PARAM Drv_DVBT_GetPacketErr_PARAM;
1462 Drv_DVBT_GetPacketErr_PARAM.pktErr=pktErr;
1463 Drv_DVBT_GetPacketErr_PARAM.ret=false;
1464
1465 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_GetPacketErr\n"));
1466 if(u32DVBTopen==1)
1467 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_GetPacketErr, &Drv_DVBT_GetPacketErr_PARAM);
1468 else
1469 return false;
1470
1471 return Drv_DVBT_GetPacketErr_PARAM.ret;
1472
1473 /*
1474 MS_BOOL bRet;
1475 float fBER;
1476
1477 DMD_LOCK();
1478 INTERN_DVBT_GetPostViterbiBer(&fBER);
1479 bRet=INTERN_DVBT_GetPacketErr(pktErr);
1480 if ((*pktErr ==1) && (fBER<= 0.000001)) // for no signal case, from Oga
1481 {
1482 *pktErr = 0x3FF;
1483 }
1484 #ifdef MS_DEBUG
1485 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
1486 {
1487 ULOGD("DEMOD","MDrv_DMD_DVBT_GetPacketErr %d\n", *pktErr);
1488 }
1489 #endif
1490 DMD_UNLOCK();
1491
1492 return bRet;
1493 */
1494 }
1495
MDrv_DMD_DVBT_GetTPSInfo(MS_U16 * u16Info)1496 MS_BOOL MDrv_DMD_DVBT_GetTPSInfo(MS_U16 *u16Info)
1497 {
1498 //MS_BOOL return_val;
1499 DVBT_GetTPSInfo_PARAM Drv_DVBT_GetTPSInfo_PARAM;
1500 Drv_DVBT_GetTPSInfo_PARAM.u16Info=u16Info;
1501 Drv_DVBT_GetTPSInfo_PARAM.ret=false;
1502
1503 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_GetTPSInfo\n"));
1504 if(u32DVBTopen==1)
1505 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_GetTPSInfo, &Drv_DVBT_GetTPSInfo_PARAM);
1506 else
1507 return false;
1508
1509 return Drv_DVBT_GetTPSInfo_PARAM.ret;
1510 /*
1511 MS_BOOL bRet;
1512
1513 DMD_LOCK();
1514 bRet=INTERN_DVBT_Get_TPS_Info(u16Info);
1515 DMD_UNLOCK();
1516
1517 return bRet;
1518 */
1519 }
1520
MDrv_DMD_DVBT_GetCellID(MS_U16 * u16CellID)1521 MS_BOOL MDrv_DMD_DVBT_GetCellID(MS_U16 *u16CellID)
1522 {
1523 // MS_BOOL return_val;
1524
1525 DVBT_GetCellID_PARAM Drv_DVBT_GetCellID_PARAM;
1526 Drv_DVBT_GetCellID_PARAM.u16CellID=u16CellID;
1527 Drv_DVBT_GetCellID_PARAM.ret=false;
1528
1529 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_GetCellID\n"));
1530 if(u32DVBTopen==1)
1531 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_GetCellID, &Drv_DVBT_GetCellID_PARAM);
1532 else
1533 return false;
1534
1535 return Drv_DVBT_GetCellID_PARAM.ret;
1536
1537 /*
1538 MS_BOOL bRet;
1539
1540 DMD_LOCK();
1541 bRet=INTERN_DVBT_Get_CELL_ID(u16CellID);
1542 DMD_UNLOCK();
1543 #ifdef MS_DEBUG
1544 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
1545 {
1546 ULOGD("DEMOD","MDrv_DMD_DVBT_GetCellID %d\n", *u16CellID);
1547 }
1548 #endif
1549 return bRet;
1550 */
1551 }
1552
1553 #ifndef MSOS_TYPE_LINUX_KERNEL
MDrv_DMD_DVBT_GetFreqOffset(float * pFreqOff)1554 MS_BOOL MDrv_DMD_DVBT_GetFreqOffset(float *pFreqOff)
1555 {
1556 // MS_BOOL return_val;
1557 /*bryam temp mark*/
1558 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_GetFreqOffset\n"));
1559 #if(0)
1560 DVBT_GetFreqOffset_PARAM Drv_DVBT_GetFreqOffset_PARAM;
1561 Drv_DVBT_GetFreqOffset_PARAM.pFreqOff=pFreqOff;
1562 #endif
1563
1564 /*bryan temp mark*/
1565 #if(0)
1566 if(u32DVBTopen==1)
1567 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_GetFreqOffset, &Drv_DVBT_GetFreqOffset_PARAM);
1568 else
1569 return false;
1570
1571 return Drv_DVBT_GetFreqOffset_PARAM.ret;
1572 #else
1573 //Drv_DVBT_GetFreqOffset_PARAM.ret=true;
1574 return true;
1575 #endif
1576
1577
1578
1579
1580 /*
1581 MS_BOOL bRet=TRUE;
1582 MS_U8 u8BW=8;
1583
1584 DMD_LOCK();
1585 switch (eDMD_DVBT_BandWidth)
1586 {
1587 case E_DMD_RF_CH_BAND_6MHz:
1588 u8BW=6;
1589 break;
1590
1591 case E_DMD_RF_CH_BAND_7MHz:
1592 u8BW=7;
1593 break;
1594
1595 case E_DMD_RF_CH_BAND_8MHz:
1596 default:
1597 u8BW=8;
1598 break;
1599 }
1600 bRet=INTERN_DVBT_Get_FreqOffset(pFreqOff, u8BW);
1601 DMD_UNLOCK();
1602
1603 #ifdef MS_DEBUG
1604 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
1605 {
1606 ULOGD("DEMOD","MDrv_DMD_DVBT_GetStatus %d %f\n", u8BW, *pFreqOff);
1607 }
1608 #endif
1609 return bRet;
1610 */
1611 }
1612 #endif
1613
1614
1615 #ifndef MSOS_TYPE_LINUX_KERNEL
MDrv_DMD_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel,DMD_CODERATE code_rate,float write_value)1616 MS_BOOL MDrv_DMD_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel, DMD_CODERATE code_rate, float write_value)
1617 {
1618 // MS_BOOL return_val;
1619 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_NORDIG_SSI_Table_Write\n"));
1620
1621 /*bryan temp mark*/
1622 #if(0)
1623 DVBT_NORDIGSSITableWrite_PARAM Drv_DVBT_NORDIGSSITableWrite_PARAM;
1624 Drv_DVBT_NORDIGSSITableWrite_PARAM.constel=constel;
1625 Drv_DVBT_NORDIGSSITableWrite_PARAM.code_rate=code_rate;
1626 Drv_DVBT_NORDIGSSITableWrite_PARAM.write_value=write_value;
1627 #endif
1628 //bryan temp mark
1629 #if(0)
1630 if(u32DVBTopen==1)
1631 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_NORDIGSSITableWrite, &Drv_DVBT_NORDIGSSITableWrite_PARAM);
1632 else
1633 return false;
1634
1635 return Drv_DVBT_NORDIGSSITableWrite_PARAM.ret;
1636 #else
1637 // Drv_DVBT_NORDIGSSITableWrite_PARAM.ret=true;
1638 return true;
1639 #endif
1640
1641
1642 /*
1643 return INTERN_DVBT_NORDIG_SSI_Table_Write(constel, code_rate, write_value);
1644 */
1645 }
1646 #endif
1647
1648 #ifndef MSOS_TYPE_LINUX_KERNEL
MDrv_DMD_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel,DMD_CODERATE code_rate,float * read_value)1649 MS_BOOL MDrv_DMD_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel, DMD_CODERATE code_rate, float *read_value)
1650 {
1651 //return INTERN_DVBT_NORDIG_SSI_Table_Read(constel, code_rate, read_value);
1652 // MS_BOOL return_val;
1653 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_NORDIG_SSI_Table_Read\n"));
1654
1655 /*bryan temp mark*/
1656 #if(0)
1657 DVBT_NORDIGSSITableRead_PARAM Drv_DVBT_NORDIGSSITableRead_PARAM;
1658 Drv_DVBT_NORDIGSSITableRead_PARAM.constel=constel;
1659 Drv_DVBT_NORDIGSSITableRead_PARAM.code_rate=code_rate;
1660 Drv_DVBT_NORDIGSSITableRead_PARAM.read_value=read_value;
1661 #endif
1662
1663 //bryan temp mark
1664 #if(0)
1665 if(u32DVBTopen==1)
1666 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_NORDIGSSITableRead, &Drv_DVBT_NORDIGSSITableRead_PARAM);
1667 else
1668 return false;
1669
1670 return Drv_DVBT_NORDIGSSITableRead_PARAM.ret;
1671 #else
1672 //Drv_DVBT_NORDIGSSITableRead_PARAM.ret=true;
1673 return true;
1674 #endif
1675
1676
1677
1678 }
1679 #endif
MDrv_DMD_DVBT_SetPowerState(EN_POWER_MODE u16PowerState)1680 MS_U32 MDrv_DMD_DVBT_SetPowerState(EN_POWER_MODE u16PowerState)
1681 {
1682 // MS_BOOL return_val;
1683 DVBT_SetPowerState_PARAM Drv_DVBT_SetPowerState_PARAM;
1684 Drv_DVBT_SetPowerState_PARAM.u16PowerState=u16PowerState;
1685 Drv_DVBT_SetPowerState_PARAM.ret=false;
1686
1687 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_SetPowerState\n"));
1688 if(u32DVBTopen==1)
1689 UtopiaIoctl(ppDVBTInstant, DMD_DVBT_DRV_CMD_SetPowerState, &Drv_DVBT_SetPowerState_PARAM);
1690 else
1691 return false;
1692
1693 return Drv_DVBT_SetPowerState_PARAM.ret;
1694 /*
1695 static EN_POWER_MODE _prev_u16PowerState = E_POWER_MECHANICAL;
1696 MS_U32 u32Return = UTOPIA_STATUS_FAIL;
1697
1698 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_SetPowerState\n"));
1699
1700 u32Return = u32Return;
1701 if (u16PowerState == E_POWER_SUSPEND)
1702 {
1703 MDrv_DMD_DVBT_Exit();
1704 _prev_u16PowerState = u16PowerState;
1705 u32Return = UTOPIA_STATUS_SUCCESS;//SUSPEND_OK;
1706 }
1707 else if (u16PowerState == E_POWER_RESUME)
1708 {
1709 if (_prev_u16PowerState == E_POWER_SUSPEND)
1710 {
1711 MDrv_DMD_DVBT_Init(&_sDMD_DVBT_InitData, sizeof(_sDMD_DVBT_InitData));
1712 _prev_u16PowerState = u16PowerState;
1713 u32Return = UTOPIA_STATUS_SUCCESS;//RESUME_OK;
1714 }
1715 else
1716 {
1717 ULOGD("DEMOD","[%s,%5d]It is not suspended yet. We shouldn't resume\n",__FUNCTION__,__LINE__);
1718 u32Return = UTOPIA_STATUS_FAIL;//SUSPEND_FAILED;
1719 }
1720 }
1721 else
1722 {
1723 ULOGD("DEMOD","[%s,%5d]Do Nothing: %d\n",__FUNCTION__,__LINE__,u16PowerState);
1724 u32Return = FALSE;
1725 }
1726 return UTOPIA_STATUS_SUCCESS;
1727 */
1728 }
1729