1 //<MStar Software>
2 //******************************************************************************
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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file drvAVD.c
98 /// @brief AVD Driver Interface
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102
103 //-------------------------------------------------------------------------------------------------
104 // Include Files
105 //-------------------------------------------------------------------------------------------------
106 // Common Definition
107 #ifdef MSOS_TYPE_LINUX_KERNEL
108 #include <linux/string.h>
109 #else
110 #include <string.h>
111 #include <stdio.h>
112 #include <math.h>
113 #endif
114 #include "MsCommon.h"
115 #include "MsVersion.h"
116 #include "MsOS.h"
117
118 // Internal Definition
119 //#include "regCHIP.h"
120 //#include "regAVD.h"
121 //#include "mapi_tuner.h"
122 #include "drvSYS.h"
123 #include "drvDMD_VD_MBX.h"
124 #include "drvDMD_INTERN_DVBC_v2.h"
125 #include "halDMD_INTERN_DVBC.h"
126 #include "halDMD_INTERN_common.h"
127 #include "drvSAR.h" // for Utopia2
128 #include "utopia.h"
129 #include "utopia_dapi.h"
130 #include "../../utopia_core/utopia_driver_id.h"
131 #include "ULog.h"
132 //-------------------------------------------------------------------------------------------------
133 // Driver Compiler Options
134 //-------------------------------------------------------------------------------------------------
135
136
137 //-------------------------------------------------------------------------------------------------
138 // Local Defines
139 //-------------------------------------------------------------------------------------------------
140
141
142 //-------------------------------------------------------------------------------------------------
143 // Local Structurs
144 //-------------------------------------------------------------------------------------------------
145
146 // share memory setting
147 typedef enum _DVBC_POOL_ID
148 {
149 DVBC_POOL_ID_DMD0 = 0
150 } DVBC_POOL_ID;
151
152 typedef struct DLL_PACKED _DVBC_RESOURCE_PRIVATE
153 {
154 DMD_DVBC_ResData sDMD_DVBC_ResData[DMD_DVBC_MAX_DEMOD_NUM];
155 } DVBC_RESOURCE_PRIVATE, *PDVBC_RESOURCE_PRIVATE;
156 // end share memory setting
157
158 DMD_DVBC_ResData *psDMD_DVBC_ResData; // pointer to share memory
159
160 static EN_POWER_MODE _prev_u16PowerState = E_POWER_MECHANICAL;
161 //-------------------------------------------------------------------------------------------------
162 // Global Variables
163 //-------------------------------------------------------------------------------------------------
164 #define DMD_LOCK() \
165 do{ \
166 MS_ASSERT(MsOS_In_Interrupt() == FALSE); \
167 if (_s32DMD_DVBC_Mutex == -1) return FALSE; \
168 if (_u8DMD_DVBC_DbgLevel == DMD_DVBC_DBGLV_DEBUG) ULOGD("DEMOD","%s lock mutex\n", __FUNCTION__);\
169 MsOS_ObtainMutex(_s32DMD_DVBC_Mutex, MSOS_WAIT_FOREVER);\
170 }while(0)
171
172 #define DMD_UNLOCK() \
173 do{ \
174 MsOS_ReleaseMutex(_s32DMD_DVBC_Mutex);\
175 if (_u8DMD_DVBC_DbgLevel == DMD_DVBC_DBGLV_DEBUG) ULOGD("DEMOD","%s unlock mutex\n", __FUNCTION__); \
176 }while(0)
177 #if 0
178 MS_U8 DVBT_TS_PHASE_EN =0;
179 MS_U8 DVBT_TS_PHASE_NUM = 0;
180 #endif
181
182 //-------------------------------------------------------------------------------------------------
183 // Local Variables
184 //-------------------------------------------------------------------------------------------------
185
186
187 // YP mark
188 #if 0
189
190 #if 1
191 static MSIF_Version _drv_dmd_dvbt_intern_version = {
192 .MW = { DMD_DVBT_INTERN_VER, },
193 };
194 #else
195 static MSIF_Version _drv_dmd_dvbt_intern_version;
196 #endif
197
198 static DMD_DVBT_InitData _sDMD_DVBT_InitData;
199 static DMD_DbgLv _u8DMDDbgLevel=DMD_DBGLV_NONE;
200 static MS_S32 _s32DMD_DVBT_Mutex=-1;
201 static DMD_DVBT_Info sDMD_DVBT_Info;
202 static MS_U16 u16DMD_DVBT_TPS_Timeout = 1500, u16DMD_DVBT_FEC_Timeout=6000;
203 static MS_U32 u32DMD_DVBT_IfFrequency = 36167L, u32DMD_DVBT_FsFrequency = 45474L;
204 static MS_U8 u8DMD_DVBT_IQSwap=0;
205 static DMD_RF_CHANNEL_BANDWIDTH eDMD_DVBT_BandWidth=E_DMD_RF_CH_BAND_8MHz;
206 #endif
207 //-------------------------------------------------------------------------------------------------
208 // Debug Functions
209 //-------------------------------------------------------------------------------------------------
210 //-------------------------------------------------------------------------------------------------
211 // Local Functions
212 //-------------------------------------------------------------------------------------------------
213
214 typedef MS_BOOL (*IOCTL_DVBC_Dual_Individual_Init)(DMD_DVBC_InitData_Transform*pDMD_DVBC_InitData, MS_U32 u32InitDataLen);
215 typedef MS_BOOL (*IOCTL_DVBC_Dual_Public_Init)(MS_U8 u8AGC_Tristate_Ctrl,MS_U8 u8Sar_Channel);
216 typedef MS_BOOL (*IOCTL_DVBC_Init)(DMD_DVBC_InitData_Transform *pDMD_DVBC_InitData, MS_U32 u32InitDataLen);
217 typedef MS_BOOL (*IOCTL_DVBC_Exit)(void);
218 typedef MS_BOOL (*IOCTL_DVBC_SetDbgLevel)(DMD_DVBC_DbgLv u8DbgLevel);
219 typedef const DMD_DVBC_Info* (*IOCTL_DVBC_GetInfo)(void);
220 typedef MS_BOOL (*IOCTL_DVBC_GetLibVer)(const MSIF_Version **ppVersion);
221 typedef MS_BOOL (*IOCTL_DVBC_GetFWVer)(MS_U16 *ver);
222 typedef MS_BOOL (*IOCTL_DVBC_GetDSPReg)(MS_U16 u16Addr, MS_U8 *pu8Data);
223 typedef MS_BOOL (*IOCTL_DVBC_SetDSPReg)(MS_U16 u16Addr, MS_U8 pu8Data);
224 typedef MS_BOOL (*IOCTL_DVBC_GetReg)(MS_U16 u16Addr, MS_U8 *pu8Data);
225 typedef MS_BOOL (*IOCTL_DVBC_SetReg)(MS_U16 u16Addr, MS_U8 u8Data);
226 typedef MS_BOOL (*IOCTL_DVBC_SetSerialControl)(MS_BOOL bEnable);
227 typedef MS_BOOL (*IOCTL_DVBC_SetConfig_symbol_rate_list)(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num);
228 typedef MS_BOOL (*IOCTL_DVBC_SetActive)(MS_BOOL bEnable);
229 typedef MS_BOOL (*IOCTL_DVBC_GetLockWithRFPower)(DMD_DVBC_GETLOCK_TYPE eType, MS_U32 u32CurrRFPowerDbm, MS_U32 u32NoChannelRFPowerDbm, DMD_DVBC_LOCK_STATUS *eLockStatus);
230 //typedef MS_BOOL (*IOCTL_DVBC_GetSignalStrengthWithRFPower)(MS_U16 *u16Strength);
231 //typedef MS_BOOL (*IOCTL_DVBC_GetSignalQualityWithRFPower)(MS_U16 *u16Quality);
232
233 typedef MS_BOOL (*IOCTL_DVBC_ActiveDmdSwitch)(MS_U8 demod_no);
234
235 typedef MS_BOOL (*IOCTL_DVBC_GetSNR)(MS_U16 *snr_reg);
236 //waiting add
237 typedef MS_BOOL (*IOCTL_DVBC_GetPostViterbiBer)(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg);
238 typedef MS_BOOL (*IOCTL_DVBC_GetIFAGC)(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err);
239
240 typedef MS_BOOL (*IOCTL_DVBC_GetPacketErr)(MS_U16 *pktErr);
241 typedef MS_BOOL (*IOCTL_DVBC_GetCellID)(MS_U16 *u16CellID);
242
243 typedef MS_BOOL (*IOCTL_DVBC_GetStatus)(DMD_DVBC_MODULATION_TYPE *pQAMMode, MS_U16 *u16SymbolRate, MS_U32 *config_Fc_reg, MS_U32 *Fc_over_Fs_reg, MS_U16 *Cfo_offset_reg);
244 //typedef MS_BOOL (*IOCTL_DVBC_GetStatus)(DMD_DVBC_MODULATION_TYPE *pQAMMode, MS_U16 *u16SymbolRate);
245 typedef MS_U32 (*IOCTL_DVBC_SetPowerState)(EN_POWER_MODE u16PowerState);
246
247 #ifdef UFO_DEMOD_DVBC_GET_AGC_INFO
248 typedef MS_BOOL (*IOCTL_DVBC_GetAGCInfo)(MS_U8 u8dbg_mode, MS_U16* pu16Data);
249 #endif
250
251
252
253 typedef struct DVBC_INSTANT_PRIVATE
254 {
255 IOCTL_DVBC_Dual_Individual_Init fpDVBC_Dual_Individual_Init;
256 IOCTL_DVBC_Dual_Public_Init fpDVBC_Dual_Public_Init;
257 IOCTL_DVBC_Init fpDVBC_Init;
258 IOCTL_DVBC_Exit fpDVBC_Exit;
259 IOCTL_DVBC_SetDbgLevel fpDVBC_SetDbgLevel;
260 IOCTL_DVBC_GetInfo fpDVBC_GetInfo;
261 IOCTL_DVBC_GetLibVer fpDVBC_GetLibVer;
262 IOCTL_DVBC_GetFWVer fpDVBC_GetFWVer;
263 IOCTL_DVBC_GetDSPReg fpDVBC_GetDSPReg;
264 IOCTL_DVBC_SetDSPReg fpDVBC_SetDSPReg;
265 IOCTL_DVBC_GetReg fpDVBC_GetReg;
266 IOCTL_DVBC_SetReg fpDVBC_SetReg;
267 IOCTL_DVBC_SetSerialControl fpDVBCSetSerialControl;
268 IOCTL_DVBC_SetConfig_symbol_rate_list fpDVBC_SetConfig_symbol_rate_list;
269 IOCTL_DVBC_SetActive fpDVBC_SetActive;
270 IOCTL_DVBC_GetLockWithRFPower fpDVBC_GetLockWithRFPower;
271 //IOCTL_DVBC_GetSignalStrengthWithRFPower fpDVBC_GetSignalStrengthWithRFPower;
272 //IOCTL_DVBC_GetSignalQualityWithRFPower fpDVBC_GetSignalQualityWithRFPower;
273 IOCTL_DVBC_ActiveDmdSwitch fpDVBC_ActiveDmdSwitch;
274 IOCTL_DVBC_GetSNR fpDVBC_GetSNR;
275 IOCTL_DVBC_GetPostViterbiBer fpDVBC_GetPostViterbiBer;
276 IOCTL_DVBC_GetPacketErr fpDVBC_GetPacketErr;
277 IOCTL_DVBC_GetCellID fpDVBC_GetCellID;
278 IOCTL_DVBC_GetStatus fpDVBC_GetStatus;
279 IOCTL_DVBC_SetPowerState fpDVBC_SetPowerState;
280
281 //waiting add
282 IOCTL_DVBC_GetIFAGC fpDVBC_GetIFAGC;
283
284 #ifdef UFO_DEMOD_DVBC_GET_AGC_INFO
285 IOCTL_DVBC_GetAGCInfo fpDVBC_GetAGCInfo;
286 #endif
287
288
289 } DVBC_INSTANT_PRIVATE;
290
291
292 MS_U8 DVBC_TS_PHASE_EN =0;
293 MS_U8 DVBC_TS_PHASE_NUM = 0;
294 //-------------------------------------------------------------------------------------------------
295 // Local Variables
296 //-------------------------------------------------------------------------------------------------
297 #if 1
298 static MSIF_Version _drv_dmd_dvbc_intern_version = {
299 .MW = { DMD_DVBC_INTERN_VER, },
300 };
301 #else
302 static MSIF_Version _drv_dmd_dvbt_intern_version;
303 #endif
304
305 static const char pDMD_DVBC_MutexString[]={"Mutex DMD DVBC"};
306 //bryan temp mark static DMD_DVBC_InitData _sDMD_DVBC_InitData;
307 static DMD_DVBC_InitData_Transform _sDMD_DVBC_InitData;
308 static DMD_DVBC_DbgLv _u8DMD_DVBC_DbgLevel=DMD_DVBC_DBGLV_NONE;
309 static MS_S32 _s32DMD_DVBC_Mutex=-1;
310 static DMD_DVBC_Info sDMD_DVBC_Info;
311 static MS_U16 u16DMD_DVBC_AutoSymbol_Timeout = 10000, u16DMD_DVBC_FixSymbol_AutoQam_Timeout=2000, u16DMD_DVBC_FixSymbol_FixQam_Timeout=1000;
312 static MS_U32 u32DMD_DVBC_PrevScanTime=0, u32DMD_DVBC_ScanCount=0;
313
314 #if defined(CHIP_KAISER)||defined(CHIP_K6LITE)
315 //for dual demod setting
316
317 //demod NO0
318 static DMD_DVBC_InitData_Transform _sDMD_DVBC_InitData_dmd0;
319 //static DMD_DVBC_DbgLv _u8DMD_DVBC_DbgLevel=DMD_DVBC_DBGLV_NONE;
320 //static MS_S32 _s32DMD_DVBC_Mutex=-1;
321 static DMD_DVBC_Info sDMD_DVBC_Info_dmd0;
322 static MS_U16 u16DMD_DVBC_AutoSymbol_Timeout_dmd0 = 10000, u16DMD_DVBC_FixSymbol_AutoQam_Timeout_dmd0=2000, u16DMD_DVBC_FixSymbol_FixQam_Timeout_dmd0=1000;
323 static MS_U32 u32DMD_DVBC_PrevScanTime_dmd0=0, u32DMD_DVBC_ScanCount_dmd0=0;
324
325 //demod NO1
326 static DMD_DVBC_InitData_Transform _sDMD_DVBC_InitData_dmd1;
327 //static DMD_DVBC_DbgLv _u8DMD_DVBC_DbgLevel=DMD_DVBC_DBGLV_NONE;
328 //static MS_S32 _s32DMD_DVBC_Mutex=-1;
329 static DMD_DVBC_Info sDMD_DVBC_Info_dmd1;
330 static MS_U16 u16DMD_DVBC_AutoSymbol_Timeout_dmd1 = 10000, u16DMD_DVBC_FixSymbol_AutoQam_Timeout_dmd1=2000, u16DMD_DVBC_FixSymbol_FixQam_Timeout_dmd1=1000;
331 static MS_U32 u32DMD_DVBC_PrevScanTime_dmd1=0, u32DMD_DVBC_ScanCount_dmd1=0;
332
333 static MS_U8 drv_demod_swtich_status=0xff; //
334 #endif
335 //-------------------------------------------------------------------------------------------------
336 // Debug Functions
337 //-------------------------------------------------------------------------------------------------
338 #ifdef MS_DEBUG
339 #define DMD_DBG(x) (x)
340 #else
341 #define DMD_DBG(x) //(x)
342 #endif
343
344 #if defined(CHIP_KAISER)||defined(CHIP_K6LITE)
DMD_DVBC_Dual_Public_Init(MS_U8 u8AGC_Tristate_Ctrl,MS_U8 u8Sar_Channel)345 MS_BOOL DMD_DVBC_Dual_Public_Init(MS_U8 u8AGC_Tristate_Ctrl,MS_U8 u8Sar_Channel)
346 {
347 char pDMD_DVBC_MutexString[16];
348 // MS_U32 u32IfFrequency = 36167L, u32FsFrequency = 45474L;
349 // MS_U8 u8IQSwap=0, u8ADCIQMode = 0, u8PadSel = 0, bPGAEnable = 0, u8PGAGain = 5;
350 MS_BOOL bRFAGCTristateEnable = 1;
351 MS_BOOL bIFAGCTristateEnable = 0;
352
353 if (_s32DMD_DVBC_Mutex != -1)
354 {
355 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBC_Init more than once\n"));
356 return FALSE;
357 }
358
359 if (NULL == strncpy(pDMD_DVBC_MutexString,"Mutex DMD DVBC",16))
360 {
361 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBC_Init strcpy Fail\n"));
362 return FALSE;
363 }
364 _s32DMD_DVBC_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, pDMD_DVBC_MutexString, MSOS_PROCESS_SHARED);
365 if ( _s32DMD_DVBC_Mutex == -1)
366 {
367 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBC_Init Create Mutex Fail\n"));
368 return FALSE;
369 }
370
371 #ifdef MS_DEBUG
372 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
373 {
374 ULOGD("DEMOD","MDrv_DMD_DVBC_Init\n");
375 }
376 #endif
377
378 if (u8Sar_Channel != 0xFF)
379 {
380 //bryan temp mark
381 // MDrv_SAR_Adc_Config(u8Sar_Channel, TRUE);
382 }
383 DMD_LOCK();
384 //_u8DMD_DVBC_DbgLevel=DMD_DVBC_DBGLV_DEBUG;
385 MDrv_SYS_DMD_VD_MBX_SetType(E_DMD_VD_MBX_TYPE_DVBC);
386 HAL_DMD_RegInit();
387
388
389 bRFAGCTristateEnable = (u8AGC_Tristate_Ctrl& (BIT_(0))) ? TRUE : FALSE; // RFAGC tristate control
390 bIFAGCTristateEnable = (u8AGC_Tristate_Ctrl & (BIT_(4))) ? TRUE : FALSE; // IFAGC tristate control
391
392
393 if (bIFAGCTristateEnable)
394 {
395 MDrv_SYS_SetAGCPadMux(E_SYS_DTV_AGC_PAD_SET_ALL_OFF);
396 }
397 else
398 {
399 MDrv_SYS_SetAGCPadMux(E_SYS_DTV_AGC_PAD_SET);
400 }
401
402 INTERN_DVBC_InitClkgen(bRFAGCTristateEnable); //RF_AGC control no use in initclkgen
403 DMD_UNLOCK();
404
405 return TRUE;
406 }
407
408
DMD_DVBC_Dual_Individual_Init(DMD_DVBC_InitData_Transform * pDMD_DVBC_InitData,MS_U32 u32InitDataLen)409 MS_BOOL DMD_DVBC_Dual_Individual_Init(DMD_DVBC_InitData_Transform*pDMD_DVBC_InitData, MS_U32 u32InitDataLen)
410 {
411 DMD_LOCK();
412
413 if ( sizeof(_sDMD_DVBC_InitData) == u32InitDataLen)
414 {
415 memcpy(&_sDMD_DVBC_InitData, pDMD_DVBC_InitData, u32InitDataLen);
416 }
417 else
418 {
419 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBC_Init input data structure incorrect\n"));
420 return FALSE;
421 }
422
423 u16DMD_DVBC_AutoSymbol_Timeout = 10000;
424 u16DMD_DVBC_FixSymbol_AutoQam_Timeout=2000;
425 u16DMD_DVBC_FixSymbol_FixQam_Timeout=2000;
426 if (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt != NULL)
427 {
428 if (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[0]>=4)
429 {
430 u16DMD_DVBC_AutoSymbol_Timeout = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[3];
431 u16DMD_DVBC_AutoSymbol_Timeout = (u16DMD_DVBC_AutoSymbol_Timeout<<8)+_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[4];
432 if (u16DMD_DVBC_AutoSymbol_Timeout < 5000) u16DMD_DVBC_AutoSymbol_Timeout=5000;
433 //ULOGD("DEMOD","u16DMD_DVBC_AutoSymbol_Timeout %d\n",u16DMD_DVBC_AutoSymbol_Timeout);
434
435 u16DMD_DVBC_FixSymbol_AutoQam_Timeout = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[5];
436 u16DMD_DVBC_FixSymbol_AutoQam_Timeout = (u16DMD_DVBC_FixSymbol_AutoQam_Timeout<<8)+_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[6];
437 if (u16DMD_DVBC_FixSymbol_AutoQam_Timeout < 2000) u16DMD_DVBC_FixSymbol_AutoQam_Timeout=2000;
438 //ULOGD("DEMOD","u16DMD_DVBC_FixSymbol_AutoQam_Timeout %d\n",u16DMD_DVBC_FixSymbol_AutoQam_Timeout);
439
440 u16DMD_DVBC_FixSymbol_FixQam_Timeout = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[7];
441 u16DMD_DVBC_FixSymbol_FixQam_Timeout = (u16DMD_DVBC_FixSymbol_FixQam_Timeout<<8)+_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[8];
442 if (u16DMD_DVBC_FixSymbol_FixQam_Timeout < 1000) u16DMD_DVBC_FixSymbol_FixQam_Timeout=1000;
443 //ULOGD("DEMOD","u16DMD_DVBC_FixSymbol_FixQam_Timeout %d\n",u16DMD_DVBC_FixSymbol_FixQam_Timeout);
444 }
445 else
446 {
447 }
448 }
449 else
450 {
451 }
452
453
454
455 if (_sDMD_DVBC_InitData.u8DMD_DVBC_DSPRegInitExt != NULL)
456 {
457 if (_sDMD_DVBC_InitData.u8DMD_DVBC_DSPRegInitExt[0]>=1)
458 {
459 INTERN_DVBC_DMD51_Individual_Initialization(_sDMD_DVBC_InitData.u8DMD_DVBC_DSPRegInitExt, _sDMD_DVBC_InitData.u8DMD_DVBC_DSPRegInitSize);
460 }
461 else
462 {
463 ULOGD("DEMOD","u8DMD_DVBT_DSPRegInitExt Error\n");
464 }
465 }
466 else
467 {
468 INTERN_DVBC_DMD51_Individual_Initialization( NULL, 0);
469 }
470
471 INTERN_DVBC_Version(&sDMD_DVBC_Info.u16Version);
472 DMD_UNLOCK();
473 #ifdef MS_DEBUG
474 ULOGD("DEMOD","firmware version: %x\n",sDMD_DVBC_Info.u16Version);
475 #endif
476 return TRUE;
477 }
478 #else
DMD_DVBC_Dual_Individual_Init(DMD_DVBC_InitData_Transform * pDMD_DVBC_InitData,MS_U32 u32InitDataLen)479 MS_BOOL DMD_DVBC_Dual_Individual_Init(DMD_DVBC_InitData_Transform *pDMD_DVBC_InitData, MS_U32 u32InitDataLen)
480 {
481 ULOGD("DEMOD","Doesn't support DVBC_Dual_Individual_Init function!!!\n");
482 return false;
483 }
484
DMD_DVBC_Dual_Public_Init(MS_U8 u8AGC_Tristate_Ctrl,MS_U8 u8Sar_Channel)485 MS_BOOL DMD_DVBC_Dual_Public_Init(MS_U8 u8AGC_Tristate_Ctrl,MS_U8 u8Sar_Channel)
486 {
487 ULOGD("DEMOD","Doesn't support DVBC_Dual_Public_Init function!!!\n");
488 return false;
489 }
490 #endif
DMD_DVBC_Init(DMD_DVBC_InitData_Transform * pDMD_DVBC_InitData,MS_U32 u32InitDataLen)491 MS_BOOL DMD_DVBC_Init(DMD_DVBC_InitData_Transform *pDMD_DVBC_InitData, MS_U32 u32InitDataLen)
492 {
493 char pDMD_DVBC_MutexString[16];
494 // MS_U32 u32IfFrequency = 36167L, u32FsFrequency = 45474L;
495 MS_U32 u32IfFrequency =5000L, u32FsFrequency = 48000L;
496 MS_U8 u8IQSwap = 0, u8ADCIQMode = 0, u8PadSel = 0, bPGAEnable = 0, u8PGAGain = 5;
497 MS_BOOL bRFAGCTristateEnable = 1;
498 MS_BOOL bIFAGCTristateEnable = 0;
499 DMD_DVBC_ResData *pRes = psDMD_DVBC_ResData;
500
501
502 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DMD_DVBC_Init\n"));
503
504 if (_s32DMD_DVBC_Mutex != -1)
505 {
506 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBC_Init more than once\n"));
507 return FALSE;
508 }
509
510 if (NULL == strncpy(pDMD_DVBC_MutexString,"Mutex DMD DVBC",16))
511 {
512 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBC_Init strcpy Fail\n"));
513 return FALSE;
514 }
515 _s32DMD_DVBC_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, pDMD_DVBC_MutexString, MSOS_PROCESS_SHARED);
516 if ( _s32DMD_DVBC_Mutex == -1)
517 {
518 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBC_Init Create Mutex Fail\n"));
519 return FALSE;
520 }
521
522 #ifdef MS_DEBUG
523 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
524 {
525 ULOGD("DEMOD","MDrv_DMD_DVBC_Init\n");
526 }
527 #endif
528
529
530
531 DMD_DBG(printf("[DEMOD][DMD_DVBC_INIT] _prev_u16PowerState is %d \n", _prev_u16PowerState));
532
533 if(E_POWER_MECHANICAL==_prev_u16PowerState)
534 {
535
536 DMD_DBG(printf("memcpy(&(pRes->sDMD_DVBC_InitData_Transform) 1111 enter \n"));
537 memcpy(&(pRes->sDMD_DVBC_InitData_Transform), pDMD_DVBC_InitData, sizeof(DMD_DVBC_InitData_Transform));
538 DMD_DBG(printf("memcpy(&(pRes->sDMD_DVBC_InitData_Transform) 2222 exit \n"));
539
540 DMD_DBG(printf("memcpy(&_sDMD_DVBC_InitData, pDMD_DVBC_InitData, u32InitDataLen) 3333 enter \n"));
541 memcpy(&_sDMD_DVBC_InitData, pDMD_DVBC_InitData, sizeof(_sDMD_DVBC_InitData));
542 DMD_DBG(printf("memcpy(&_sDMD_DVBC_InitData, pDMD_DVBC_InitData, u32InitDataLen) 4444 exit \n"));
543
544 }
545 else if(E_POWER_RESUME==_prev_u16PowerState)
546 {
547 DMD_DBG(printf("memcpy E_POWER_RESUME Enter \n"));
548 memcpy(&_sDMD_DVBC_InitData, &(pRes->sDMD_DVBC_InitData_Transform), sizeof(DMD_DVBC_InitData_Transform));
549 DMD_DBG(printf("memcpy E_POWER_RESUME Exit \n"));
550 }
551 else
552 {
553 ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c][DMD_DVBC_Init][check !!!]\n");
554 }
555
556
557 pRes->sDMD_DVBC_SHARE_MEMORY_InitData.b_IsInit_DVBCCreat = 1;
558 ULOGD("DEMOD","[DMD_DVBC_Init] b_IsInit_DVBCCreat = %d;\n", pRes->sDMD_DVBC_SHARE_MEMORY_InitData.b_IsInit_DVBCCreat);
559
560
561
562 if (_sDMD_DVBC_InitData.u8SarChannel != 0xFF)
563 {
564 //bryan temp mark
565 // MDrv_SAR_Adc_Config(_sDMD_DVBC_InitData.u8SarChannel, TRUE);
566 }
567 DMD_LOCK();
568 //_u8DMD_DVBC_DbgLevel=DMD_DVBC_DBGLV_DEBUG;
569 MDrv_SYS_DMD_VD_MBX_SetType(E_DMD_VD_MBX_TYPE_DVBC);
570 HAL_DMD_RegInit();
571
572 if (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt != NULL)
573 {
574 if (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[0]>=2)
575 {
576 bRFAGCTristateEnable = (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[3] & (BIT_(0))) ? TRUE : FALSE; // RFAGC tristate control
577 bIFAGCTristateEnable = (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[3] & (BIT_(4))) ? TRUE : FALSE; // IFAGC tristate control
578 }
579 else
580 {
581 bRFAGCTristateEnable = 1;
582 bIFAGCTristateEnable = 0;
583 }
584 }
585 else
586 {
587 bRFAGCTristateEnable = 1;
588 bIFAGCTristateEnable = 0;
589 }
590
591 if (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt != NULL)
592 {
593 if (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[0]>=3)
594 {
595 u32IfFrequency = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[4]; // IF frequency
596 u32IfFrequency = (u32IfFrequency<<8)+_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[5]; // IF frequency
597 u32IfFrequency = (u32IfFrequency<<8)+_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[6]; // IF frequency
598 u32IfFrequency = (u32IfFrequency<<8)+_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[7]; // IF frequency
599 u32FsFrequency = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[8]; // FS frequency
600 u32FsFrequency = (u32FsFrequency<<8)+_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[9]; // FS frequency
601 u32FsFrequency = (u32FsFrequency<<8)+_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[10]; // FS frequency
602 u32FsFrequency = (u32FsFrequency<<8)+_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[11]; // FS frequency
603 u8IQSwap = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[12]; // IQ Swap
604 u8IQSwap = u8IQSwap;
605 u8ADCIQMode = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[13]; // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
606 u8PadSel = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[14]; // u8PadSel : 0=Normal, 1=analog pad
607 bPGAEnable = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[15]; // bPGAEnable : 0=disable, 1=enable
608 u8PGAGain = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[16]; // u8PGAGain : default 5
609 }
610 else
611 {
612
613 }
614 }
615 else
616 {
617
618 }
619
620 u16DMD_DVBC_AutoSymbol_Timeout = 10000;
621 u16DMD_DVBC_FixSymbol_AutoQam_Timeout=2000;
622 u16DMD_DVBC_FixSymbol_FixQam_Timeout=2000;
623 if (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt != NULL)
624 {
625 if (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[0]>=4)
626 {
627 u16DMD_DVBC_AutoSymbol_Timeout = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[17];
628 u16DMD_DVBC_AutoSymbol_Timeout = (u16DMD_DVBC_AutoSymbol_Timeout<<8)+_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[18];
629 if (u16DMD_DVBC_AutoSymbol_Timeout < 5000) u16DMD_DVBC_AutoSymbol_Timeout=5000;
630 //ULOGD("DEMOD","u16DMD_DVBC_AutoSymbol_Timeout %d\n",u16DMD_DVBC_AutoSymbol_Timeout);
631
632 u16DMD_DVBC_FixSymbol_AutoQam_Timeout = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[19];
633 u16DMD_DVBC_FixSymbol_AutoQam_Timeout = (u16DMD_DVBC_FixSymbol_AutoQam_Timeout<<8)+_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[20];
634 if (u16DMD_DVBC_FixSymbol_AutoQam_Timeout < 2000) u16DMD_DVBC_FixSymbol_AutoQam_Timeout=2000;
635 //ULOGD("DEMOD","u16DMD_DVBC_FixSymbol_AutoQam_Timeout %d\n",u16DMD_DVBC_FixSymbol_AutoQam_Timeout);
636
637 u16DMD_DVBC_FixSymbol_FixQam_Timeout = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[21];
638 u16DMD_DVBC_FixSymbol_FixQam_Timeout = (u16DMD_DVBC_FixSymbol_FixQam_Timeout<<8)+_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[22];
639 if (u16DMD_DVBC_FixSymbol_FixQam_Timeout < 1000) u16DMD_DVBC_FixSymbol_FixQam_Timeout=1000;
640 //ULOGD("DEMOD","u16DMD_DVBC_FixSymbol_FixQam_Timeout %d\n",u16DMD_DVBC_FixSymbol_FixQam_Timeout);
641 }
642 else
643 {
644 }
645 }
646 else
647 {
648 }
649
650 #ifdef MS_DEBUG
651 ULOGD("DEMOD","u32IfFrequency %ld\n",u32IfFrequency);
652 ULOGD("DEMOD","u32FsFrequency %ld\n",u32FsFrequency);
653 ULOGD("DEMOD","u8IQSwap %d\n",u8IQSwap);
654 #endif
655
656 if (bIFAGCTristateEnable)
657 {
658 MDrv_SYS_SetAGCPadMux(E_SYS_DTV_AGC_PAD_SET_ALL_OFF);
659 }
660 else
661 {
662 MDrv_SYS_SetAGCPadMux(E_SYS_DTV_AGC_PAD_SET);
663 }
664
665 // oga
666 DVBC_TS_PHASE_EN = 0;
667 DVBC_TS_PHASE_NUM = 0;
668 if (0)//(_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt != NULL)
669 {
670 if (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[0]>=5) // version bigger than 5, apply TS phase solution
671 {
672 DVBC_TS_PHASE_EN = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[INDEX_C_TS_PHASE_EN];
673 DVBC_TS_PHASE_NUM = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[INDEX_C_TS_PHASE_NUM];
674 ULOGD("DEMOD","##DVBC: TS check: bTsPhaseEn = %d, u16TsPhaseNum = %d\n",DVBC_TS_PHASE_EN,DVBC_TS_PHASE_NUM);
675 }
676 else
677 {
678 ULOGD("DEMOD","##DVBC:TS Phase check !!, board version smaller than 4\n");
679 }
680 }
681 else // if init board define is NULL TS phase needs check.
682 {
683 ULOGD("DEMOD","##DVBC: TS Phase check !!\n");
684 }
685
686 if(0)// (_sDMD_DVBC_InitData.u8DMD_DVBC_DSPRegInitExt != NULL)
687 {
688 if (_sDMD_DVBC_InitData.u8DMD_DVBC_DSPRegInitExt[0]>=1)
689 {
690 INTERN_DVBC_Power_On_Initialization(bRFAGCTristateEnable, u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain, _sDMD_DVBC_InitData.u8DMD_DVBC_DSPRegInitExt, _sDMD_DVBC_InitData.u8DMD_DVBC_DSPRegInitSize);
691 }
692 else
693 {
694 ULOGD("DEMOD","u8DMD_DVBT_DSPRegInitExt Error\n");
695 }
696 }
697 else
698 {
699 ULOGD("DEMOD","[DMD_DVBC_Init]INTERN_DVBC_Power_On_Initialization Enter \n");
700 INTERN_DVBC_Power_On_Initialization(bRFAGCTristateEnable, u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain, NULL, 0);
701 ULOGD("DEMOD","[DMD_DVBC_Init]INTERN_DVBC_Power_On_Initialization exit \n");
702 }
703 INTERN_DVBC_Version(&sDMD_DVBC_Info.u16Version);
704 pRes->sDMD_DVBC_SHARE_MEMORY_PreviousData.u16Version = sDMD_DVBC_Info.u16Version;
705
706 DMD_UNLOCK();
707 #ifdef MS_DEBUG
708 ULOGD("DEMOD","firmware version: %x\n",sDMD_DVBC_Info.u16Version);
709 #endif
710 return TRUE;
711 }
712
DMD_DVBC_Exit(void)713 MS_BOOL DMD_DVBC_Exit(void)
714 {
715 DMD_DVBC_ResData *pRes = psDMD_DVBC_ResData;
716 MS_BOOL bRet;
717
718 #ifdef MS_DEBUG
719 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
720 {
721 ULOGD("DEMOD","MDrv_DMD_DVBC_Exit\n");
722 }
723 #endif
724 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DMD_DVBC_Exit\n"));
725 pRes->sDMD_DVBC_SHARE_MEMORY_InitData.b_IsInit_DVBCCreat = 0;
726 ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c] DVBCCreat = %d\n", pRes->sDMD_DVBC_SHARE_MEMORY_InitData.b_IsInit_DVBCCreat);
727 DMD_LOCK();
728 bRet = INTERN_DVBC_Exit();
729 DMD_UNLOCK();
730 MsOS_DeleteMutex(_s32DMD_DVBC_Mutex);
731 _s32DMD_DVBC_Mutex= -1;
732 return bRet;
733 }
734
DMD_DVBC_SetDbgLevel(DMD_DVBC_DbgLv u8DbgLevel)735 MS_BOOL DMD_DVBC_SetDbgLevel(DMD_DVBC_DbgLv u8DbgLevel)
736 {
737 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DMD_DVBC_SetDbgLevel\n"));
738
739 DMD_LOCK();
740 _u8DMD_DVBC_DbgLevel = u8DbgLevel;
741 DMD_UNLOCK();
742 return TRUE;
743 }
744
DMD_DVBC_GetInfo(void)745 const DMD_DVBC_Info* DMD_DVBC_GetInfo(void)
746 {
747 #ifdef MS_DEBUG
748 MS_U8 state = 0;
749 #endif
750
751 #ifdef MS_DEBUG
752 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
753 {
754 ULOGD("DEMOD","MDrv_DMD_DVBC_GetInfo\n");
755 }
756 #endif
757 //for DBG
758 #ifdef MS_DEBUG
759 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &state);
760 ULOGD("DEMOD"," @INTERN_DVBC_GetLock FSM 0x%x\n",state);
761 INTERN_DVBC_Show_AGC_Info();
762 INTERN_DVBC_info();
763 #endif
764
765 return (const DMD_DVBC_Info*)&sDMD_DVBC_Info;
766 }
767
DMD_DVBC_GetLibVer(const MSIF_Version ** ppVersion)768 MS_BOOL DMD_DVBC_GetLibVer(const MSIF_Version **ppVersion)
769 {
770 #ifdef MS_DEBUG
771 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
772 {
773 ULOGD("DEMOD","MDrv_DMD_DVBC_GetLibVer\n");
774 }
775 #endif
776 DMD_LOCK();
777 if (!ppVersion)
778 {
779 return FALSE;
780 }
781
782 *ppVersion = &_drv_dmd_dvbc_intern_version;
783 DMD_UNLOCK();
784 return TRUE;
785 }
786
DMD_DVBC_GetFWVer(MS_U16 * ver)787 MS_BOOL DMD_DVBC_GetFWVer(MS_U16 *ver)
788 {
789
790 MS_BOOL bRet;
791
792 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DMD_DVBC_GetFWVer\n"));
793
794 DMD_LOCK();
795
796 bRet = INTERN_DVBC_Version(ver);
797 //ULOGD("DEMOD","MDrv_DMD_DVBC_GetFWVer %x\n", *ver);
798 DMD_UNLOCK();
799
800 return bRet;
801
802 }
803
DMD_DVBC_GetDSPReg(MS_U16 u16Addr,MS_U8 * pu8Data)804 MS_BOOL DMD_DVBC_GetDSPReg(MS_U16 u16Addr, MS_U8 *pu8Data)
805 {
806 #if defined(CHIP_K1)||defined(CHIP_KENYA)
807 MS_BOOL bRet;
808
809 DMD_LOCK();
810 bRet=MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16Addr, pu8Data);
811 DMD_UNLOCK();
812
813 #ifdef MS_DEBUG
814 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
815 {
816 ULOGD("DEMOD","MDrv_DMD_DVBC_GetDSPReg %x %x\n", u16Addr, *pu8Data);
817 }
818 #endif
819
820 return bRet;
821 #else
822 ULOGD("DEMOD","Not Support function: MDrv_DMD_DVBC_GetDSPReg\n");
823 return FALSE;
824 #endif
825 }
826
DMD_DVBC_SetDSPReg(MS_U16 u16Addr,MS_U8 pu8Data)827 MS_BOOL DMD_DVBC_SetDSPReg(MS_U16 u16Addr, MS_U8 pu8Data)
828 {
829 #if defined(CHIP_K1)||defined(CHIP_KENYA)
830 MS_BOOL bRet;
831
832 DMD_LOCK();
833 bRet=MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16Addr, pu8Data);
834 DMD_UNLOCK();
835
836 #ifdef MS_DEBUG
837 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
838 {
839 ULOGD("DEMOD","MDrv_DMD_DVBC_SetDSPReg %x %x\n", u16Addr, pu8Data);
840 }
841 #endif
842
843 return bRet;
844 #else
845 ULOGD("DEMOD","Not Support function: MDrv_DMD_DVBC_SetDSPReg\n");
846 return FALSE;
847 #endif
848 }
849
850
DMD_DVBC_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)851 MS_BOOL DMD_DVBC_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
852 {
853 MS_BOOL bRet;
854
855 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DMD_DVBC_GetReg\n"));
856
857 DMD_LOCK();
858 bRet=MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr, pu8Data);
859 DMD_UNLOCK();
860
861 #ifdef MS_DEBUG
862 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
863 {
864 ULOGD("DEMOD","MDrv_DMD_DVBC_GetReg %x %x\n", u16Addr, *pu8Data);
865 }
866 #endif
867 return bRet;
868 }
869
DMD_DVBC_SetReg(MS_U16 u16Addr,MS_U8 u8Data)870 MS_BOOL DMD_DVBC_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
871 {
872 MS_BOOL bRet;
873
874 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DMD_DVBC_SetReg\n"));
875
876 #ifdef MS_DEBUG
877 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
878 {
879 ULOGD("DEMOD","MDrv_DMD_DVBC_SetReg %x %x\n", u16Addr, u8Data);
880 }
881 #endif
882 DMD_LOCK();
883 bRet=MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr, u8Data);
884 DMD_UNLOCK();
885 return bRet;
886 }
887
DMD_DVBC_SetSerialControl(MS_BOOL bEnable)888 MS_BOOL DMD_DVBC_SetSerialControl(MS_BOOL bEnable)
889 {
890 MS_BOOL bRet;
891 MS_U8 u8TSClk;
892
893 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DMD_DVBC_SetSerialControl\n"));
894
895 #ifdef MS_DEBUG
896 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
897 {
898 ULOGD("DEMOD","MDrv_DMD_DVBC_SetSerialControl %d\n", bEnable);
899 }
900 #endif
901
902 DMD_LOCK();
903 if (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt != NULL)
904 {
905 if (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[0]>=1)
906 {
907 u8TSClk = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[2];
908 }
909 else
910 {
911 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
912 }
913 }
914 else
915 {
916 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
917 }
918 bRet=INTERN_DVBC_Serial_Control(bEnable, u8TSClk);
919 DMD_UNLOCK();
920 return bRet;
921 }
922
DMD_DVBC_SetConfig(MS_U16 u16SymbolRate,DMD_DVBC_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS)923 MS_BOOL DMD_DVBC_SetConfig(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS)
924 {
925 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DMD_DVBC_SetConfig\n"));
926
927 return MDrv_DMD_DVBC_SetConfig_symbol_rate_list(u16SymbolRate, eQamMode, u32IFFreq, bSpecInv, bSerialTS, NULL, 0);
928 }
929
DMD_DVBC_SetConfig_symbol_rate_list(MS_U16 u16SymbolRate,DMD_DVBC_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)930 MS_BOOL DMD_DVBC_SetConfig_symbol_rate_list(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
931 {
932 MS_BOOL bRet;
933 MS_U8 u8TSClk;
934 DMD_DVBC_ResData *pRes = psDMD_DVBC_ResData;
935
936 ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c][_prev_u16PowerState = %d] DMD_DVBC_SetConfig_symbol_rate_list\n", _prev_u16PowerState);
937
938
939 if(E_POWER_MECHANICAL==_prev_u16PowerState)
940 {
941 pRes->sDMD_DVBC_SHARE_MEMORY_PreviousData.u16SymbolRate = u16SymbolRate;
942 pRes->sDMD_DVBC_SHARE_MEMORY_PreviousData.eQamMode = eQamMode;
943 pRes->sDMD_DVBC_SHARE_MEMORY_PreviousData.u32IFFreq = u32IFFreq;
944 pRes->sDMD_DVBC_SHARE_MEMORY_PreviousData.bSpecInv = bSpecInv;
945 pRes->sDMD_DVBC_SHARE_MEMORY_PreviousData.bSerialTS = bSerialTS;
946
947 ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c][E_POWER_MECHANICAL]DMD_DVBC_SetConfig_symbol_rate_list\n");
948 ULOGD("DEMOD","SR = %d, QamMode = %d, IFFreq = %d, SpecInv = %d, SerialTS = %d\n",(int)u16SymbolRate, (int)eQamMode,(int) u32IFFreq, (int)bSpecInv, bSerialTS);
949 }
950 else if(E_POWER_RESUME==_prev_u16PowerState)
951 {
952 u16SymbolRate = pRes->sDMD_DVBC_SHARE_MEMORY_PreviousData.u16SymbolRate;
953 eQamMode = pRes->sDMD_DVBC_SHARE_MEMORY_PreviousData.eQamMode;
954 u32IFFreq = pRes->sDMD_DVBC_SHARE_MEMORY_PreviousData.u32IFFreq;
955 bSpecInv = pRes->sDMD_DVBC_SHARE_MEMORY_PreviousData.bSpecInv;
956 bSerialTS = pRes->sDMD_DVBC_SHARE_MEMORY_PreviousData.bSerialTS;
957 ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c][E_POWER_RESUME]DMD_DVBC_SetConfig_symbol_rate_list\n");
958 ULOGD("DEMOD","SR = %d, QamMode = %d, IFFreq = %d, SpecInv = %d, SerialTS = %d\n",(int)u16SymbolRate, (int)eQamMode, (int)u32IFFreq, (int)bSpecInv, (int)bSerialTS);
959 }
960 else
961 {
962 ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c][check!!]DMD_DVBC_SetConfig_symbol_rate_list\n");
963 }
964
965 #ifdef MS_DEBUG
966 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
967 {
968 ULOGD("DEMOD","MDrv_DMD_DVBC_SetConfig %d %d %ld %d %d\n", u16SymbolRate, eQamMode, u32IFFreq, bSpecInv, bSerialTS);
969 }
970 #endif
971
972 ULOGD("DEMOD","bryan check QAM mode=%d in V2\n",eQamMode);
973
974
975 DMD_LOCK();
976 if (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt != NULL)
977 {
978 if (_sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[0]>=1)
979 {
980 u8TSClk = _sDMD_DVBC_InitData.u8DMD_DVBC_InitExt[2];
981 }
982 else
983 {
984 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
985 }
986 }
987 else
988 {
989 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
990 }
991 bRet=INTERN_DVBC_Config(u16SymbolRate, eQamMode, u32IFFreq, bSpecInv, bSerialTS, u8TSClk, pu16_symbol_rate_list,u8_symbol_rate_list_num);
992 sDMD_DVBC_Info.u16SymbolRate = u16SymbolRate;
993 sDMD_DVBC_Info.eQamMode = eQamMode;
994 sDMD_DVBC_Info.u32IFFreq = u32IFFreq;
995 sDMD_DVBC_Info.bSpecInv = bSpecInv;
996 sDMD_DVBC_Info.bSerialTS = bSerialTS;
997
998
999
1000
1001
1002 DMD_UNLOCK();
1003 return bRet;
1004 }
1005
DMD_DVBC_SetActive(MS_BOOL bEnable)1006 MS_BOOL DMD_DVBC_SetActive(MS_BOOL bEnable)
1007 {
1008 MS_BOOL bRet;
1009
1010 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DMD_DVBC_SetActive\n"));
1011
1012 #ifdef MS_DEBUG
1013 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
1014 {
1015 ULOGD("DEMOD","MDrv_DMD_DVBC_SetActive %d\n", bEnable);
1016 }
1017 #endif
1018
1019 DMD_LOCK();
1020 bRet=INTERN_DVBC_Active(bEnable);
1021 sDMD_DVBC_Info.u32ChkScanTimeStart = MsOS_GetSystemTime();
1022 u32DMD_DVBC_ScanCount=0;
1023 #ifdef MS_DEBUG
1024 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
1025 {
1026 ULOGD("DEMOD","%s %ld\n", __FUNCTION__, sDMD_DVBC_Info.u32ChkScanTimeStart);
1027 }
1028 #endif
1029 DMD_UNLOCK();
1030 return bRet;
1031 }
1032
1033
1034
DMD_DVBC_GetLockWithRFPower(DMD_DVBC_GETLOCK_TYPE eType,MS_U32 u32CurrRFPowerDbm,MS_U32 u32NoChannelRFPowerDbm,DMD_DVBC_LOCK_STATUS * eLockStatus)1035 MS_BOOL DMD_DVBC_GetLockWithRFPower(DMD_DVBC_GETLOCK_TYPE eType, MS_U32 u32CurrRFPowerDbm, MS_U32 u32NoChannelRFPowerDbm, DMD_DVBC_LOCK_STATUS *eLockStatus)
1036 {
1037 MS_U32 u32CurrScanTime=0;
1038 MS_BOOL bRet=FALSE;
1039
1040 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DMD_DVBC_GetLockWithRFPower\n"));
1041
1042 DMD_LOCK();
1043 if ( eType == DMD_DVBC_GETLOCK ) // for channel scan
1044 {
1045 if (INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_FEC_LOCK, 2000, -2000, 0))
1046 {
1047 *eLockStatus = DMD_DVBC_LOCK;
1048 }
1049 else
1050 {
1051 MS_U32 u32Timeout = 10000;//(sDMD_DVBC_Info.u16SymbolRate) ? 5000 : 15000;
1052 if (sDMD_DVBC_Info.u16SymbolRate == 0)
1053 {
1054 u32Timeout = u16DMD_DVBC_AutoSymbol_Timeout;
1055 }
1056 else
1057 {
1058 u32Timeout = (sDMD_DVBC_Info.eQamMode == DMD_DVBC_QAMAUTO) ? u16DMD_DVBC_FixSymbol_AutoQam_Timeout : u16DMD_DVBC_FixSymbol_FixQam_Timeout;
1059 }
1060
1061 u32CurrScanTime=MsOS_GetSystemTime();
1062 if (u32CurrScanTime - sDMD_DVBC_Info.u32ChkScanTimeStart < u32Timeout)
1063 {
1064 if (u32DMD_DVBC_ScanCount==0)
1065 {
1066 u32DMD_DVBC_PrevScanTime=u32CurrScanTime;
1067 u32DMD_DVBC_ScanCount++;
1068 }
1069
1070 if (_sDMD_DVBC_InitData.u8SarChannel != 0xFF)
1071 {
1072 //bryan temp mark
1073 // sDMD_DVBC_Info.u8SarValue=MDrv_SAR_Adc_GetValue(_sDMD_DVBC_InitData.u8SarChannel);
1074 }
1075 else
1076 {
1077 sDMD_DVBC_Info.u8SarValue=0xFF;
1078 }
1079
1080 /*bRet=HAL_DMD_GetRFLevel(&fCurrRFPowerDbm, fCurrRFPowerDbm, sDMD_DVBC_Info.u8SarValue,
1081 _sDMD_DVBC_InitData.pTuner_RfagcSsi, _sDMD_DVBC_InitData.u16Tuner_RfagcSsi_Size,
1082 _sDMD_DVBC_InitData.pTuner_IfagcSsi_HiRef, _sDMD_DVBC_InitData.u16Tuner_IfagcSsi_HiRef_Size,
1083 _sDMD_DVBC_InitData.pTuner_IfagcSsi_LoRef, _sDMD_DVBC_InitData.u16Tuner_IfagcSsi_LoRef_Size,
1084 _sDMD_DVBC_InitData.pTuner_IfagcErr_HiRef, _sDMD_DVBC_InitData.u16Tuner_IfagcErr_HiRef_Size,
1085 _sDMD_DVBC_InitData.pTuner_IfagcErr_LoRef, _sDMD_DVBC_InitData.u16Tuner_IfagcErr_LoRef_Size);
1086 */
1087 //if (INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_NO_CHANNEL, u32CurrScanTime-u32DMD_DVBC_PrevScanTime))
1088 if (INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_NO_CHANNEL, u32CurrRFPowerDbm, u32NoChannelRFPowerDbm, u32CurrScanTime-u32DMD_DVBC_PrevScanTime))
1089 {
1090 #ifdef MS_DEBUG
1091 ULOGD("DEMOD","%s %ld UNLOCK:NO_CHANNEL\n", __FUNCTION__, u32CurrScanTime-sDMD_DVBC_Info.u32ChkScanTimeStart);
1092 #endif
1093 *eLockStatus = DMD_DVBC_UNLOCK;
1094 }
1095 else if (INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_ATV_DETECT, 2000, -2000, 0))
1096 {
1097 #ifdef MS_DEBUG
1098 ULOGD("DEMOD","%s %ld UNLOCK:ATV_DETECT\n", __FUNCTION__, u32CurrScanTime-sDMD_DVBC_Info.u32ChkScanTimeStart);
1099 #endif
1100 *eLockStatus = DMD_DVBC_UNLOCK;
1101 }
1102 #ifdef NEW_TR_MODULE
1103 else if ((INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TR_EVER_LOCK, 2000, -2000, 0) == FALSE) && ((u32CurrScanTime - sDMD_DVBC_Info.u32ChkScanTimeStart) > 500))
1104
1105 #else
1106 else if ((INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TR_EVER_LOCK, 2000, -2000, 0) == FALSE) && ((u32CurrScanTime - sDMD_DVBC_Info.u32ChkScanTimeStart) > 5000))
1107 #endif
1108 {
1109 #ifdef MS_DEBUG
1110 ULOGD("DEMOD","%s %ld UNLOCK:TR\n", __FUNCTION__, u32CurrScanTime-sDMD_DVBC_Info.u32ChkScanTimeStart);
1111 #endif
1112 *eLockStatus = DMD_DVBC_UNLOCK;
1113 }
1114 else
1115 {
1116 *eLockStatus = DMD_DVBC_CHECKING;
1117 }
1118 }
1119 else
1120 {
1121 #ifdef MS_DEBUG
1122 ULOGD("DEMOD","%s %ld UNLOCK:TIMEOUT %ld\n", __FUNCTION__, MsOS_GetSystemTime(), u32Timeout);
1123 #endif
1124 *eLockStatus = DMD_DVBC_UNLOCK;
1125 }
1126 u32DMD_DVBC_PrevScanTime=u32CurrScanTime;
1127 }
1128 sDMD_DVBC_Info.eLockStatus = *eLockStatus;
1129 #ifdef MS_DEBUG
1130 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
1131 {
1132 ULOGD("DEMOD","%s %ld %d\n", __FUNCTION__, MsOS_GetSystemTime(), sDMD_DVBC_Info.eLockStatus);
1133 }
1134 #endif
1135 }
1136 else
1137 {
1138 if (INTERN_DVBC_GetLock(eType, 2000, -2000, 0) == TRUE)
1139 {
1140 *eLockStatus = DMD_DVBC_LOCK;
1141 }
1142 else
1143 {
1144 *eLockStatus = DMD_DVBC_UNLOCK;
1145 }
1146 }
1147 DMD_UNLOCK();
1148
1149 #ifdef MS_DEBUG
1150 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
1151 {
1152 ULOGD("DEMOD","MDrv_DMD_DVBC_GetLock %x %x\n", eType, *eLockStatus);
1153 }
1154 #endif
1155 bRet=TRUE;
1156
1157
1158 #ifdef MS_DEBUG
1159
1160 if(*eLockStatus ==DMD_DVBC_LOCK)
1161 ULOGD("DEMOD","check kernel driver DVBC locked!!\n");
1162 else
1163 ULOGD("DEMOD","check kernel driver DVBC unlock!!\n");
1164 #endif
1165
1166 return bRet;
1167 }
1168
1169
1170 /*
1171 MS_BOOL DMD_DVBC_GetSignalStrength(MS_U16 *u16Strength)
1172 {
1173 return MDrv_DMD_DVBC_GetSignalStrengthWithRFPower(u16Strength);
1174 }
1175
1176 MS_BOOL DMD_DVBC_GetSignalStrengthWithRFPower(MS_U16 *u16Strength)
1177 {
1178 MS_BOOL bRet;
1179
1180 DMD_LOCK();
1181 if (_sDMD_DVBC_InitData.u8SarChannel != 0xFF)
1182 {
1183 sDMD_DVBC_Info.u8SarValue=MDrv_SAR_Adc_GetValue(_sDMD_DVBC_InitData.u8SarChannel);
1184 }
1185 else
1186 {
1187 sDMD_DVBC_Info.u8SarValue=0xFF;
1188 }
1189 bRet=INTERN_DVBC_GetSignalStrength(u16Strength, (const DMD_DVBC_InitData *)(&_sDMD_DVBC_InitData), sDMD_DVBC_Info.u8SarValue);
1190 sDMD_DVBC_Info.u16Strength=*u16Strength;
1191 DMD_UNLOCK();
1192
1193 #ifdef MS_DEBUG
1194 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
1195 {
1196 ULOGD("DEMOD","MDrv_DMD_DVBC_GetSignalStrength %d\n", *u16Strength);
1197 }
1198 #endif
1199 return bRet;
1200 }
1201
1202 MS_BOOL DMD_DVBC_GetSignalQuality(MS_U16 *u16Quality)
1203 {
1204 return MDrv_DMD_DVBC_GetSignalQualityWithRFPower(u16Quality);
1205 }
1206
1207 MS_BOOL DMD_DVBC_GetSignalQualityWithRFPower(MS_U16 *u16Quality)
1208 {
1209 MS_BOOL bRet;
1210
1211 DMD_LOCK();
1212 if (_sDMD_DVBC_InitData.u8SarChannel != 0xFF)
1213 {
1214 sDMD_DVBC_Info.u8SarValue=MDrv_SAR_Adc_GetValue(_sDMD_DVBC_InitData.u8SarChannel);
1215 }
1216 else
1217 {
1218 sDMD_DVBC_Info.u8SarValue=0xFF;
1219 }
1220 bRet=INTERN_DVBC_GetSignalQuality(u16Quality, (const DMD_DVBC_InitData *)(&_sDMD_DVBC_InitData), sDMD_DVBC_Info.u8SarValue);
1221 sDMD_DVBC_Info.u16Quality=*u16Quality;
1222 DMD_UNLOCK();
1223 #ifdef MS_DEBUG
1224 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
1225 {
1226 ULOGD("DEMOD","%s %d %d\n", __FUNCTION__, bRet, sDMD_DVBC_Info.u16Quality);
1227 }
1228 #endif
1229
1230 #ifdef MS_DEBUG
1231 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
1232 {
1233 ULOGD("DEMOD","MDrv_DMD_DVBC_GetSignalQuality %d\n", *u16Quality);
1234 }
1235 #endif
1236 return bRet;
1237 }
1238 */
1239
1240 #if defined(CHIP_KAISER)||defined(CHIP_K6LITE)
DMD_DVBC_ActiveDmdSwitch(MS_U8 demod_no)1241 MS_BOOL DMD_DVBC_ActiveDmdSwitch(MS_U8 demod_no)
1242 {
1243 MS_BOOL bRet=TRUE;
1244 DMD_LOCK();
1245 if((demod_no==0) &&(drv_demod_swtich_status!=0))
1246 {
1247 //save the demod 1 parameter back
1248 _sDMD_DVBC_InitData_dmd1=_sDMD_DVBC_InitData;
1249 sDMD_DVBC_Info_dmd1=sDMD_DVBC_Info;
1250 u16DMD_DVBC_AutoSymbol_Timeout_dmd1=u16DMD_DVBC_AutoSymbol_Timeout;
1251 u16DMD_DVBC_FixSymbol_AutoQam_Timeout_dmd1=u16DMD_DVBC_FixSymbol_AutoQam_Timeout;
1252 u16DMD_DVBC_FixSymbol_FixQam_Timeout_dmd1=u16DMD_DVBC_FixSymbol_FixQam_Timeout;
1253 u32DMD_DVBC_PrevScanTime_dmd1=u32DMD_DVBC_PrevScanTime;
1254 u32DMD_DVBC_ScanCount_dmd1=u32DMD_DVBC_ScanCount;
1255 }
1256 else if((demod_no==1) &&(drv_demod_swtich_status!=1))
1257 {
1258 //save the demod 0 parameter back
1259 _sDMD_DVBC_InitData_dmd0=_sDMD_DVBC_InitData;
1260 sDMD_DVBC_Info_dmd0=sDMD_DVBC_Info;
1261 u16DMD_DVBC_AutoSymbol_Timeout_dmd0=u16DMD_DVBC_AutoSymbol_Timeout;
1262 u16DMD_DVBC_FixSymbol_AutoQam_Timeout_dmd0=u16DMD_DVBC_FixSymbol_AutoQam_Timeout;
1263 u16DMD_DVBC_FixSymbol_FixQam_Timeout_dmd0=u16DMD_DVBC_FixSymbol_FixQam_Timeout;
1264 u32DMD_DVBC_PrevScanTime_dmd0=u32DMD_DVBC_PrevScanTime;
1265 u32DMD_DVBC_ScanCount_dmd0=u32DMD_DVBC_ScanCount;
1266 }
1267
1268
1269 bRet=INTERN_DVBC_ActiveDmdSwitch(demod_no);
1270
1271 if((demod_no==0) &&(drv_demod_swtich_status!=0))
1272 {
1273 //insert the demod 0 parameter
1274 _sDMD_DVBC_InitData=_sDMD_DVBC_InitData_dmd0;
1275 sDMD_DVBC_Info=sDMD_DVBC_Info_dmd0;
1276 u16DMD_DVBC_AutoSymbol_Timeout=u16DMD_DVBC_AutoSymbol_Timeout_dmd0;
1277 u16DMD_DVBC_FixSymbol_AutoQam_Timeout=u16DMD_DVBC_FixSymbol_AutoQam_Timeout_dmd0;
1278 u16DMD_DVBC_FixSymbol_FixQam_Timeout=u16DMD_DVBC_FixSymbol_FixQam_Timeout_dmd0;
1279 u32DMD_DVBC_PrevScanTime=u32DMD_DVBC_PrevScanTime_dmd0;
1280 u32DMD_DVBC_ScanCount=u32DMD_DVBC_ScanCount_dmd0;
1281 }
1282 else if((demod_no==1) &&(drv_demod_swtich_status!=1))
1283 {
1284 //insert the demod 1 parameter
1285 _sDMD_DVBC_InitData=_sDMD_DVBC_InitData_dmd1;
1286 sDMD_DVBC_Info=sDMD_DVBC_Info_dmd1;
1287 u16DMD_DVBC_AutoSymbol_Timeout=u16DMD_DVBC_AutoSymbol_Timeout_dmd1;
1288 u16DMD_DVBC_FixSymbol_AutoQam_Timeout=u16DMD_DVBC_FixSymbol_AutoQam_Timeout_dmd1;
1289 u16DMD_DVBC_FixSymbol_FixQam_Timeout=u16DMD_DVBC_FixSymbol_FixQam_Timeout_dmd1;
1290 u32DMD_DVBC_PrevScanTime=u32DMD_DVBC_PrevScanTime_dmd1;
1291 u32DMD_DVBC_ScanCount=u32DMD_DVBC_ScanCount_dmd1;
1292 }
1293
1294 drv_demod_swtich_status=demod_no;
1295 DMD_UNLOCK();
1296 return bRet;
1297 }
1298 #else
DMD_DVBC_ActiveDmdSwitch(MS_U8 demod_no)1299 MS_BOOL DMD_DVBC_ActiveDmdSwitch(MS_U8 demod_no)
1300 {
1301 ULOGD("DEMOD","Doesn't support DVBC_ActiveDmdSwitch function!!!\n");
1302 return false;
1303 }
1304 #endif
1305
DMD_DVBC_GetSNR(MS_U16 * snr_reg)1306 MS_BOOL DMD_DVBC_GetSNR(MS_U16 *snr_reg)
1307 {
1308 MS_BOOL bRet;
1309 DMD_LOCK();
1310 bRet=INTERN_DVBC_GetSNR(snr_reg);
1311 DMD_UNLOCK();
1312
1313 return bRet;
1314 }
1315
1316 //waiting add
DMD_DVBC_GetPostViterbiBer(MS_U32 * BitErr_reg,MS_U16 * BitErrPeriod_reg)1317 MS_BOOL DMD_DVBC_GetPostViterbiBer(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg)
1318 {
1319 MS_BOOL bRet;
1320
1321 DMD_LOCK();
1322 bRet=INTERN_DVBC_GetPostViterbiBer(BitErr_reg, BitErrPeriod_reg);
1323 DMD_UNLOCK();
1324
1325 return bRet;
1326 }
1327
1328
1329 #ifdef UFO_DEMOD_DVBC_GET_AGC_INFO
DMD_DVBC_GetAGCInfo(MS_U8 u8dbg_mode,MS_U16 * pu16Data)1330 MS_BOOL DMD_DVBC_GetAGCInfo(MS_U8 u8dbg_mode, MS_U16 *pu16Data)
1331 {
1332 MS_BOOL bRet;
1333 DMD_LOCK();
1334 bRet = INTERN_DVBC_AGC_Info(u8dbg_mode, pu16Data);
1335 DMD_UNLOCK();
1336 return bRet;
1337 }
1338 #endif
1339
1340 //waiting add
DMD_DVBC_GetIFAGC(MS_U8 * ifagc_reg,MS_U8 * ifagc_reg_lsb,MS_U16 * ifagc_err)1341 MS_BOOL DMD_DVBC_GetIFAGC(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err)
1342 {
1343 MS_BOOL bRet;
1344
1345 DMD_LOCK();
1346 bRet=INTERN_DVBC_GetIFAGC(ifagc_reg, ifagc_reg_lsb, ifagc_err);
1347 DMD_UNLOCK();
1348
1349 return bRet;
1350 }
1351
1352
DMD_DVBC_GetPacketErr(MS_U16 * pktErr)1353 MS_BOOL DMD_DVBC_GetPacketErr(MS_U16 *pktErr)
1354 {
1355 MS_BOOL bRet;
1356
1357 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DMD_DVBC_GetPacketErr\n"));
1358
1359 DMD_LOCK();
1360 bRet=INTERN_DVBC_GetPacketErr(pktErr);
1361 DMD_UNLOCK();
1362
1363 return bRet;
1364 }
1365
DMD_DVBC_GetCellID(MS_U16 * u16CellID)1366 MS_BOOL DMD_DVBC_GetCellID(MS_U16 *u16CellID)
1367 {
1368 MS_BOOL bRet;
1369
1370 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DMD_DVBC_GetCellID\n"));
1371
1372 DMD_LOCK();
1373 bRet=INTERN_DVBC_Get_CELL_ID(u16CellID);
1374 DMD_UNLOCK();
1375
1376 #ifdef MS_DEBUG
1377 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
1378 {
1379 ULOGD("DEMOD","MDrv_DMD_DVBC_GetCellID %x\n", *u16CellID);
1380 }
1381 #endif
1382 return bRet;
1383 }
1384
1385
1386 //bryan temp mark
1387 #if(1)
DMD_DVBC_GetStatus(DMD_DVBC_MODULATION_TYPE * pQAMMode,MS_U16 * u16SymbolRate,MS_U32 * config_Fc_reg,MS_U32 * Fc_over_Fs_reg,MS_U16 * Cfo_offset_reg)1388 MS_BOOL DMD_DVBC_GetStatus(DMD_DVBC_MODULATION_TYPE *pQAMMode, MS_U16 *u16SymbolRate, MS_U32 *config_Fc_reg, MS_U32 *Fc_over_Fs_reg, MS_U16 *Cfo_offset_reg)
1389 {
1390 MS_BOOL bRet=TRUE;
1391
1392 DMD_LOCK();
1393 INTERN_DVBC_GetCurrentModulationType(pQAMMode);
1394 INTERN_DVBC_GetCurrentSymbolRate(u16SymbolRate);
1395 INTERN_DVBC_Get_FreqOffset(config_Fc_reg, Fc_over_Fs_reg, Cfo_offset_reg, 8);
1396 DMD_UNLOCK();
1397
1398 #ifdef MS_DEBUG
1399 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
1400 {
1401 //ULOGD("DEMOD","MDrv_DMD_DVBC_GetStatus %d %d\n", *pQAMMode, *u16SymbolRate, *pFreqOff_reg);
1402 }
1403 #endif
1404 return bRet;
1405 }
1406 #else
DMD_DVBC_GetStatus(DMD_DVBC_MODULATION_TYPE * pQAMMode,MS_U16 * u16SymbolRate)1407 MS_BOOL DMD_DVBC_GetStatus(DMD_DVBC_MODULATION_TYPE *pQAMMode, MS_U16 *u16SymbolRate)
1408 {
1409 MS_BOOL bRet=TRUE;
1410
1411 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DMD_DVBC_GetStatus\n"));
1412
1413 DMD_LOCK();
1414 INTERN_DVBC_GetCurrentModulationType(pQAMMode);
1415 INTERN_DVBC_GetCurrentSymbolRate(u16SymbolRate);
1416 // INTERN_DVBC_Get_FreqOffset(pFreqOff,8);
1417 DMD_UNLOCK();
1418 //ULOGD("DEMOD","bryan get status QAM mode=%d in V2\n",*pQAMMode);
1419 #ifdef MS_DEBUG
1420 if (_u8DMD_DVBC_DbgLevel >= DMD_DVBC_DBGLV_INFO)
1421 {
1422 // ULOGD("DEMOD","MDrv_DMD_DVBC_GetStatus %d %d %f\n", *pQAMMode, *u16SymbolRate, *pFreqOff);
1423 }
1424 #endif
1425 return bRet;
1426 }
1427 #endif
1428
DMD_DVBC_SetPowerState(EN_POWER_MODE u16PowerState)1429 MS_U32 DMD_DVBC_SetPowerState(EN_POWER_MODE u16PowerState)
1430 {
1431
1432 MS_U32 u32Return = UTOPIA_STATUS_FAIL;
1433 DMD_DVBC_ResData *pRes = psDMD_DVBC_ResData;
1434
1435
1436 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DMD_DVBC_SetPowerState\n"));
1437
1438 u32Return = u32Return;
1439
1440 if (u16PowerState == E_POWER_SUSPEND)
1441 {
1442 pRes->sDMD_DVBC_SHARE_MEMORY_InitData.b_DCOFF_IsDVBC = pRes->sDMD_DVBC_SHARE_MEMORY_InitData.b_IsInit_DVBCCreat;
1443 pRes->sDMD_DVBC_SHARE_MEMORY_InitData.eLastState = u16PowerState;
1444 _prev_u16PowerState = u16PowerState;
1445
1446 ULOGD("DEMOD","[E_POWER_SUSPEND] DVBCCreat =%d \n",pRes->sDMD_DVBC_SHARE_MEMORY_InitData.b_IsInit_DVBCCreat);
1447 ULOGD("DEMOD","[E_POWER_SUSPEND] b_DCOFF_IsDVBC =%d \n",pRes->sDMD_DVBC_SHARE_MEMORY_InitData.b_DCOFF_IsDVBC);
1448 if(pRes->sDMD_DVBC_SHARE_MEMORY_InitData.b_IsInit_DVBCCreat)
1449 {
1450 DMD_DVBC_Exit();
1451 }
1452 else
1453 {
1454 }
1455
1456
1457
1458 u32Return = UTOPIA_STATUS_SUCCESS;//SUSPEND_OK;
1459 }
1460 else if (u16PowerState == E_POWER_RESUME)
1461 {
1462 if (_prev_u16PowerState == E_POWER_SUSPEND)
1463 {
1464 _prev_u16PowerState = u16PowerState;
1465 pRes->sDMD_DVBC_SHARE_MEMORY_InitData.eLastState = u16PowerState;
1466 ULOGD("DEMOD","[E_POWER_RESUME + E_POWER_SUSPEND] b_DCOFF_IsDVBC = %d \n",pRes->sDMD_DVBC_SHARE_MEMORY_InitData.b_DCOFF_IsDVBC);
1467 if(pRes->sDMD_DVBC_SHARE_MEMORY_InitData.b_DCOFF_IsDVBC)
1468 {
1469
1470 DMD_DVBC_Init(&_sDMD_DVBC_InitData, sizeof(_sDMD_DVBC_InitData));
1471 DMD_DVBC_SetConfig_symbol_rate_list(1,2,3,0,0,NULL,0);
1472 DMD_DVBC_SetActive(1);
1473 }
1474 else
1475 {
1476 }
1477
1478 u32Return = UTOPIA_STATUS_SUCCESS;//RESUME_OK;
1479 }
1480 else
1481 {
1482 ULOGD("DEMOD","[%s,%5d]It is not suspended yet. We shouldn't resume\n",__FUNCTION__,__LINE__);
1483 u32Return = UTOPIA_STATUS_FAIL;//SUSPEND_FAILED;
1484 }
1485 }
1486 else
1487 {
1488 ULOGD("DEMOD","\r\n ====== DVBC doesn't need to Suspend/Resume at Non-DVBC mode ====== \r\n");
1489 u32Return = UTOPIA_STATUS_FAIL;
1490 }
1491
1492 return u32Return;
1493 }
1494
1495 //-------------------------------------------------------------------------------------------------
1496 // Global Functions
1497 //-------------------------------------------------------------------------------------------------
DVBCOpen(void ** ppInstance,MS_U32 u32ModuleVersion,void * pAttribute)1498 MS_U32 DVBCOpen(void** ppInstance, MS_U32 u32ModuleVersion, void* pAttribute)
1499 {
1500
1501 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCOpen\n"));
1502
1503 DVBC_INSTANT_PRIVATE *pDvbcPri= NULL;
1504
1505 UtopiaInstanceCreate(sizeof(DVBC_INSTANT_PRIVATE), ppInstance);
1506 UtopiaInstanceGetPrivate(*ppInstance, (void*)&pDvbcPri);
1507
1508
1509 pDvbcPri->fpDVBC_Init=DMD_DVBC_Init;
1510 pDvbcPri->fpDVBC_Dual_Individual_Init=DMD_DVBC_Dual_Individual_Init;
1511 pDvbcPri->fpDVBC_Dual_Public_Init=DMD_DVBC_Dual_Public_Init;
1512 pDvbcPri->fpDVBC_Exit=DMD_DVBC_Exit;
1513 pDvbcPri->fpDVBC_SetDbgLevel=DMD_DVBC_SetDbgLevel;
1514
1515 pDvbcPri->fpDVBC_GetInfo=DMD_DVBC_GetInfo;
1516 pDvbcPri->fpDVBC_GetLibVer=DMD_DVBC_GetLibVer;
1517
1518 pDvbcPri->fpDVBC_GetFWVer=DMD_DVBC_GetFWVer;
1519 pDvbcPri->fpDVBC_GetDSPReg=DMD_DVBC_GetDSPReg;
1520 pDvbcPri->fpDVBC_SetDSPReg=DMD_DVBC_SetDSPReg;
1521 pDvbcPri->fpDVBC_GetReg=DMD_DVBC_GetReg;
1522 pDvbcPri->fpDVBC_SetReg=DMD_DVBC_SetReg;
1523
1524 pDvbcPri->fpDVBCSetSerialControl=DMD_DVBC_SetSerialControl;
1525 pDvbcPri->fpDVBC_SetConfig_symbol_rate_list=DMD_DVBC_SetConfig_symbol_rate_list;
1526 pDvbcPri->fpDVBC_SetActive=DMD_DVBC_SetActive;
1527
1528 pDvbcPri->fpDVBC_GetLockWithRFPower=DMD_DVBC_GetLockWithRFPower;
1529
1530 //pDvbcPri->fpDVBC_GetSignalStrengthWithRFPower=DMD_DVBC_GetSignalStrengthWithRFPower;
1531 //pDvbcPri->fpDVBC_GetSignalQualityWithRFPower=DMD_DVBC_GetSignalQualityWithRFPower;
1532
1533 pDvbcPri->fpDVBC_ActiveDmdSwitch=DMD_DVBC_ActiveDmdSwitch;
1534
1535 pDvbcPri->fpDVBC_GetSNR=DMD_DVBC_GetSNR;
1536 pDvbcPri->fpDVBC_GetPostViterbiBer=DMD_DVBC_GetPostViterbiBer;
1537
1538 pDvbcPri->fpDVBC_GetPacketErr=DMD_DVBC_GetPacketErr;
1539
1540 pDvbcPri->fpDVBC_GetCellID=DMD_DVBC_GetCellID;
1541 //bryan temp mark pDvbcPri->fpDVBC_GetStatus=DMD_DVBC_GetStatus;
1542 pDvbcPri->fpDVBC_GetStatus=DMD_DVBC_GetStatus;
1543
1544 pDvbcPri->fpDVBC_SetPowerState=DMD_DVBC_SetPowerState;
1545
1546 //waiting add
1547 pDvbcPri->fpDVBC_GetIFAGC=DMD_DVBC_GetIFAGC;
1548
1549 #ifdef UFO_DEMOD_DVBC_GET_AGC_INFO
1550 pDvbcPri->fpDVBC_GetAGCInfo=DMD_DVBC_GetAGCInfo;
1551 #endif
1552
1553 //return TRUE;
1554 return UTOPIA_STATUS_SUCCESS;
1555 }
1556
DVBCIoctl(void * pInstance,MS_U32 u32Cmd,void * pArgs)1557 MS_U32 DVBCIoctl(void* pInstance, MS_U32 u32Cmd, void* pArgs)
1558 {
1559 //ULOGD("DEMOD","\n[drvDMD_INTERN_DVBC_v2.c][DVBC INFO] DVBC Ioctl \n");
1560 void* pModule = NULL;
1561 UtopiaInstanceGetModule(pInstance, &pModule);
1562
1563 void* pResource = NULL;
1564 DVBC_RESOURCE_PRIVATE* psDVBCResPri = NULL;
1565 DVBC_INSTANT_PRIVATE* psDVBCInstPri = NULL;
1566 void* psDVBCInstPriVoid = NULL;
1567 UtopiaInstanceGetPrivate(pInstance, (void**)&psDVBCInstPriVoid);
1568 psDVBCInstPri = (DVBC_INSTANT_PRIVATE*)psDVBCInstPriVoid;
1569
1570 MS_BOOL bRet = FALSE;
1571
1572 if (UtopiaResourceObtain(pModule, DVBC_POOL_ID_DMD0, &pResource) != 0)
1573 {
1574 DMD_DBG(ULOGD("DEMOD","UtopiaResourceObtainToInstant fail\n"));
1575 return UTOPIA_STATUS_ERR_RESOURCE;
1576 }
1577
1578 if(UtopiaResourceGetPrivate(pResource,(void*)&psDVBCResPri) != 0)
1579 {
1580 printf("UtopiaResourceGetPrivate fail\n");
1581 return UTOPIA_STATUS_FAIL;
1582 }
1583
1584
1585 psDMD_DVBC_ResData = ((PDVBC_RESOURCE_PRIVATE)psDVBCResPri)->sDMD_DVBC_ResData;
1586
1587 switch (u32Cmd)
1588 {
1589 #if defined(CHIP_KAISER)||defined(CHIP_K6LITE)
1590
1591 case DMD_DVBC_DRV_CMD_Dual_Public_Init:
1592 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - u8AGC_Tristate_Ctrl\n"));
1593 bRet=psDVBCInstPri->fpDVBC_Dual_Public_Init(((PDVBC_Dual_Public_Init_PARAM)pArgs)->u8AGC_Tristate_Ctrl,
1594 ((PDVBC_Dual_Public_Init_PARAM)pArgs)->u8Sar_Channel);
1595
1596 ((PDVBC_Dual_Public_Init_PARAM)pArgs)->ret=bRet;
1597 break;
1598 case DMD_DVBC_DRV_CMD_Dual_Individual_Init:
1599 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - pDMD_DVBC_InitData\n"));
1600 bRet=psDVBCInstPri->fpDVBC_Dual_Individual_Init(((PDVBC_Dual_Individual_Init_PARAM)pArgs)->pDMD_DVBC_InitData,
1601 ((PDVBC_Dual_Individual_Init_PARAM)pArgs)->u32InitDataLen);
1602
1603 ((PDVBC_Dual_Individual_Init_PARAM)pArgs)->ret=bRet;
1604 break;
1605 #endif
1606
1607 case DMD_DVBC_DRV_CMD_Init:
1608 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_Init\n"));
1609 bRet = psDVBCInstPri->fpDVBC_Init( (((PDVBC_Init_PARAM)pArgs)->pDMD_DVBC_InitData), ((PDVBC_Init_PARAM)pArgs)->u32InitDataLen);
1610 ((PDVBC_Init_PARAM)pArgs)->ret=bRet;
1611 break;
1612 case DMD_DVBC_DRV_CMD_Exit:
1613 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_Exit\n"));
1614 bRet= psDVBCInstPri->fpDVBC_Exit();
1615 ((PDVBC_EXIT_PARAM_PARAM)pArgs)->ret=bRet;
1616 break;
1617 case DMD_DVBC_DRV_CMD_SetDbgLevel:
1618 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_SetDbgLevel\n"));
1619 bRet= psDVBCInstPri->fpDVBC_SetDbgLevel(((PDVBC_SetDbgLevel_PARAM)pArgs)->u8DbgLevel);
1620 ((PDVBC_SetDbgLevel_PARAM)pArgs)->ret=bRet;
1621 break;
1622 case DMD_DVBC_DRV_CMD_GetInfo:
1623 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_GetInfo\n"));
1624 ((PDVBC_GetInfo_PARAM)pArgs)->ret_info=psDVBCInstPri->fpDVBC_GetInfo();
1625 break;
1626 case DMD_DVBC_DRV_CMD_GetLibVer:
1627 bRet=psDVBCInstPri->fpDVBC_GetLibVer(((PDVBC_GetLibVer_PARAM)pArgs)->ppVersion);
1628 ((PDVBC_GetLibVer_PARAM)pArgs)->ret=bRet;
1629 break;
1630 case DMD_DVBC_DRV_CMD_GetFWVer:
1631 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_GetFWVer\n"));
1632 bRet=psDVBCInstPri->fpDVBC_GetFWVer(((PDVBC_GetFWVer_PARAM)pArgs)->ver);
1633 ((PDVBC_GetFWVer_PARAM)pArgs)->ret=bRet;
1634 break;
1635 case DMD_DVBC_DRV_CMD_GetDSPReg:
1636 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_GetDSPReg\n"));
1637 bRet=psDVBCInstPri->fpDVBC_GetDSPReg(((PDVBC_GetDSPReg_PARAM)pArgs)->u16Addr,((PDVBC_GetDSPReg_PARAM)pArgs)->pu8Data);
1638 ((PDVBC_GetDSPReg_PARAM)pArgs)->ret=bRet;
1639 break;
1640
1641 case DMD_DVBC_DRV_CMD_SetDSPReg:
1642 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_SetDSPReg\n"));
1643 bRet=psDVBCInstPri->fpDVBC_SetDSPReg(((PDVBC_SetDSPReg_PARAM)pArgs)->u16Addr,((PDVBC_SetDSPReg_PARAM)pArgs)->pu8Data);
1644 ((PDVBC_SetDSPReg_PARAM)pArgs)->ret=bRet;
1645 break;
1646 case DMD_DVBC_DRV_CMD_GetReg:
1647 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_GetReg\n"));
1648 bRet=psDVBCInstPri->fpDVBC_GetReg(((PDVBC_GetReg_PARAM)pArgs)->u16Addr,((PDVBC_GetReg_PARAM)pArgs)->pu8Data);
1649 ((PDVBC_GetReg_PARAM)pArgs)->ret=bRet;
1650 break;
1651 case DMD_DVBC_DRV_CMD_SetReg:
1652 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_SetReg\n"));
1653 bRet=psDVBCInstPri->fpDVBC_SetReg(((PDVBC_SetReg_PARAM)pArgs)->u16Addr,((PDVBC_SetReg_PARAM)pArgs)->u8Data);
1654 ((PDVBC_SetReg_PARAM)pArgs)->ret=bRet;
1655 break;
1656
1657 case DMD_DVBC_DRV_CMD_SetSerialControl:
1658 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_SetSerialControl\n"));
1659 bRet=psDVBCInstPri->fpDVBCSetSerialControl(((PDVBC_SetSerialControl_PARAM)pArgs)->bEnable);
1660 ((PDVBC_SetSerialControl_PARAM)pArgs)->ret=bRet;
1661 break;
1662
1663 case DMD_DVBC_DRV_CMD_SetSetConfig_symbol_rate_list:
1664 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_SetSetConfig_symbol_rate_list\n"));
1665 bRet=psDVBCInstPri->fpDVBC_SetConfig_symbol_rate_list(((PDVBC_SetConfig_Symbol_rate_list_PARAM)pArgs)->u16SymbolRate,\
1666 ((PDVBC_SetConfig_Symbol_rate_list_PARAM)pArgs)->eQamMode,((PDVBC_SetConfig_Symbol_rate_list_PARAM)pArgs)->u32IFFreq,\
1667 ((PDVBC_SetConfig_Symbol_rate_list_PARAM)pArgs)->bSpecInv,\
1668 ((PDVBC_SetConfig_Symbol_rate_list_PARAM)pArgs)->bSerialTS,((PDVBC_SetConfig_Symbol_rate_list_PARAM)pArgs)->pu16_symbol_rate_list,\
1669 ((PDVBC_SetConfig_Symbol_rate_list_PARAM)pArgs)->u8_symbol_rate_list_num
1670 );
1671
1672 ((PDVBC_SetConfig_Symbol_rate_list_PARAM)pArgs)->ret=bRet;
1673
1674 break;
1675 case DMD_DVBC_DRV_CMD_SetActive:
1676 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_SetActive\n"));
1677 bRet=psDVBCInstPri->fpDVBC_SetActive(((PDVBC_SetActive_PARAM)pArgs)->bEnable);
1678 ((PDVBC_SetActive_PARAM)pArgs)->ret=bRet;
1679 break;
1680
1681
1682 case DMD_DVBC_DRV_CMD_GetLockWithRFPower:
1683 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_GetLockWithRFPower\n"));
1684
1685 //ULOGD("DEMOD","bryan check DVBC in V2 layer DMD_DVBC_DRV_CMD_GetLockWithRFPower\n");
1686 bRet=psDVBCInstPri->fpDVBC_GetLockWithRFPower(((PDVBC_GetLockWithRFPower)pArgs)->eType,\
1687 ((PDVBC_GetLockWithRFPower)pArgs)->u32CurrRFPowerDbm,\
1688 ((PDVBC_GetLockWithRFPower)pArgs)->u32NoChannelRFPowerDbm,\
1689 ((PDVBC_GetLockWithRFPower)pArgs)->eLockStatus);
1690 ((PDVBC_GetLockWithRFPower)pArgs)->ret=bRet;
1691
1692 break;
1693 /*
1694 case DMD_DVBC_DRV_CMD_GetSignalStrengthWithRFPower:
1695 bRet=psDVBCInstPri->fpDVBC_GetSignalStrengthWithRFPower(((PDVBC_GetSignalStrengthWithRFPower_PARAM)pArgs)->u16Strength);
1696 ((PDVBC_GetSignalStrengthWithRFPower_PARAM)pArgs)->ret=bRet;
1697 break;
1698
1699 case DMD_DVBC_DRV_CMD_GetSignalQualityWithRFPower:
1700 bRet=psDVBCInstPri->fpDVBC_GetSignalQualityWithRFPower((PDVBC_GetSignalStrengthWithRFPower_PARAM)pArgs->u16Strength);
1701 (PDVBC_GetSignalStrengthWithRFPower_PARAM)pArgs->ret=bRet;
1702 break;
1703 #endif
1704 */
1705
1706 case DMD_DVBC_DRV_CMD_ActiveDmdSwitch:
1707 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_ActiveDmdSwitch\n"));
1708 bRet=psDVBCInstPri->fpDVBC_ActiveDmdSwitch(((PDVBC_ActiveDmdSwitch_PARAM)pArgs)->demod_no);
1709 ((PDVBC_ActiveDmdSwitch_PARAM)pArgs)->ret=bRet;
1710 break;
1711
1712
1713 case DMD_DVBC_DRV_CMD_GetSNR:
1714 bRet=psDVBCInstPri->fpDVBC_GetSNR(((PDVBC_GetSNR_PARAM)pArgs)->snr_reg);
1715 ((PDVBC_GetSNR_PARAM)pArgs)->ret=bRet;
1716 break;
1717
1718 // waiting add
1719 case DMD_DVBC_DRV_CMD_GetPostViterbiBer:
1720 bRet=psDVBCInstPri->fpDVBC_GetPostViterbiBer(((PDVBC_GetPostViterbiBer_PARAM)pArgs)->BitErr_reg,\
1721 ((PDVBC_GetPostViterbiBer_PARAM)pArgs)->BitErrPeriod_reg);
1722 ((PDVBC_GetPostViterbiBer_PARAM)pArgs)->ret=bRet;
1723 break;
1724
1725
1726 case DMD_DVBC_DRV_CMD_GetPacketErr:
1727 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_GetPacketErr\n"));
1728 bRet=psDVBCInstPri->fpDVBC_GetPacketErr(((PDVBC_GetPacketErr_PARAM)pArgs)->pktErr);
1729 ((PDVBC_GetPacketErr_PARAM)pArgs)->ret=bRet;
1730 break;
1731
1732 case DMD_DVBC_DRV_CMD_GetCellID:
1733 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_GetCellID\n"));
1734 bRet=psDVBCInstPri->fpDVBC_GetCellID(((PDVBC_GetCellID_PARAM)pArgs)->u16CellID);
1735 ((PDVBC_GetCellID_PARAM)pArgs)->ret=bRet;
1736 break;
1737
1738 case DMD_DVBC_DRV_CMD_GetStatus:
1739 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_GetStatus\n"));
1740 bRet=psDVBCInstPri->fpDVBC_GetStatus(((PDVBC_GetStatus_PARAM)pArgs)->pQAMMode,((PDVBC_GetStatus_PARAM)pArgs)->u16SymbolRate,\
1741 ((PDVBC_GetStatus_PARAM)pArgs)->config_Fc_reg,\
1742 ((PDVBC_GetStatus_PARAM)pArgs)->Fc_over_Fs_reg,\
1743 ((PDVBC_GetStatus_PARAM)pArgs)->Cfo_offset_reg);
1744 ((PDVBC_GetStatus_PARAM)pArgs)->ret=bRet;
1745 break;
1746
1747
1748 case DMD_DVBC_DRV_CMD_SetPowerState:
1749 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_SetPowerState\n"));
1750 ((PDVBC_SetPowerState_PARAM)pArgs)->ret_U32=psDVBCInstPri->fpDVBC_SetPowerState(((PDVBC_SetPowerState_PARAM)pArgs)->u16PowerState);
1751
1752 break;
1753
1754
1755 // waiting add
1756 case DMD_DVBC_DRV_CMD_GetIFAGC:
1757 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_GetIFAGC\n"));
1758 bRet=psDVBCInstPri->fpDVBC_GetIFAGC(((PDVBC_GetIFAGC_PARAM)pArgs)->ifagc_reg,\
1759 ((PDVBC_GetIFAGC_PARAM)pArgs)->ifagc_reg_lsb,\
1760 ((PDVBC_GetIFAGC_PARAM)pArgs)->ifagc_err_reg);
1761 ((PDVBC_GetIFAGC_PARAM)pArgs)->ret=bRet;
1762 break;
1763
1764 #ifdef UFO_DEMOD_DVBC_GET_AGC_INFO
1765 case DMD_DVBC_DRV_CMD_GetAGCInfo:
1766 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCIoctl - MDrv_DMD_DVBC_GetAGCInfo\n"));
1767 bRet=psDVBCInstPri->fpDVBC_GetAGCInfo(((PDVBC_GetAGCInfo_PARAM)pArgs)->u8dbg_mode,\
1768 ((PDVBC_GetAGCInfo_PARAM)pArgs)->pu16Data);
1769 ((PDVBC_GetAGCInfo_PARAM)pArgs)->ret=bRet;
1770 break;
1771 #endif
1772
1773 default:
1774 break;
1775 }
1776
1777 //jway suggest UtopiaResourceRelease(pResource);
1778 UtopiaResourceRelease(pResource);
1779
1780 return (bRet ? UTOPIA_STATUS_SUCCESS : UTOPIA_STATUS_FAIL);
1781 }
1782
DVBCClose(void * pInstance)1783 MS_U32 DVBCClose(void* pInstance)
1784 {
1785 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCClose\n"));
1786
1787 UtopiaInstanceDelete(pInstance);
1788
1789 return UTOPIA_STATUS_SUCCESS;
1790 }
1791
DVBCStr(MS_U32 u32PowerState,void * pModule)1792 MS_U32 DVBCStr(MS_U32 u32PowerState, void* pModule)
1793 {
1794 MS_U32 u32Return = UTOPIA_STATUS_FAIL;
1795 MS_U32 u32Ret = 0;
1796
1797 void* pResource = NULL;
1798 DVBC_RESOURCE_PRIVATE* psDVBCResPri = NULL;
1799
1800
1801 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCStr\n"));
1802
1803 //UtopiaModuleGetSTRPrivate(pModule, (void**));
1804
1805 if (UtopiaResourceObtain(pModule, DVBC_POOL_ID_DMD0, &pResource) != 0)
1806 {
1807 printf("DVBC - UtopiaResourceObtainToInstant fail\n");
1808 return UTOPIA_STATUS_ERR_RESOURCE;
1809 }
1810
1811 if(UtopiaResourceGetPrivate(pResource,(void*)&psDVBCResPri) != 0)
1812 {
1813 printf("DVBC - UtopiaResourceGetPrivate fail\n");
1814 return UTOPIA_STATUS_FAIL;
1815 }
1816
1817 psDMD_DVBC_ResData = ((PDVBC_RESOURCE_PRIVATE)psDVBCResPri)->sDMD_DVBC_ResData;
1818
1819
1820
1821 if (u32PowerState == E_POWER_SUSPEND)
1822 {
1823 /* Please Implement Module Suspend Flow Here. */
1824 u32Ret = DMD_DVBC_SetPowerState(E_POWER_SUSPEND);
1825
1826 if(u32Ret == TRUE)
1827 u32Return = UTOPIA_STATUS_SUCCESS;//SUSPEND_OK;
1828 else
1829 u32Return = UTOPIA_STATUS_FAIL;
1830 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c][DVBCStr] SUSPEND !\n"));
1831 }
1832 else if (u32PowerState == E_POWER_RESUME)
1833 {
1834 /* Please Implement Module Resume Flow Here. */
1835 u32Ret = DMD_DVBC_SetPowerState(E_POWER_RESUME);
1836
1837 if(u32Ret == TRUE)
1838 u32Return = UTOPIA_STATUS_SUCCESS;//RESUME_OK;
1839 else
1840 u32Return = UTOPIA_STATUS_FAIL;
1841 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c][DVBCStr] RESUME !\n"));
1842 }
1843 else
1844 {
1845 u32Return = UTOPIA_STATUS_FAIL;
1846 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c][DVBCStr] OTHERS !\n"));
1847 }
1848
1849 UtopiaResourceRelease(pResource);
1850
1851 return u32Return;// for success
1852 }
1853
DVBCRegisterToUtopia(void)1854 void DVBCRegisterToUtopia(void)
1855 {
1856 // 1. deal with module
1857
1858 void* pUtopiaModule = NULL;
1859 // UtopiaModuleCreate(MODULE_DVBT, 8, &pUtopiaModule);
1860 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c]DVBCRegisterToUtopia\n"));
1861
1862 UtopiaModuleCreate(MODULE_DVBC, 8, &pUtopiaModule);
1863 UtopiaModuleRegister(pUtopiaModule);
1864 UtopiaModuleSetupFunctionPtr(pUtopiaModule, (FUtopiaOpen)DVBCOpen, (FUtopiaClose)DVBCClose, (FUtopiaIOctl)DVBCIoctl);
1865
1866 // Utopia2K STR
1867 #if defined(MSOS_TYPE_LINUX_KERNEL)
1868 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBC_v2.c][DVBCRegisterToUtopia] KERNEL DVBCStr!\n"));
1869 UtopiaModuleSetupSTRFunctionPtr(pUtopiaModule,(FUtopiaSTR)DVBCStr);
1870 #endif
1871
1872 // 20160107 oga. add share memory to control DC ON/OFF variable
1873
1874 // 2. deal with resource
1875 void* psResource = NULL;
1876 // start func to add res, call once will create 2 access in resource. Also can declare BDMA_POOL_ID_BDMA1 for another channel depend on driver owner.
1877 UtopiaModuleAddResourceStart(pUtopiaModule, DVBC_POOL_ID_DMD0);
1878 // resource can alloc private for internal use, ex, BDMA_RESOURCE_PRIVATE
1879 UtopiaResourceCreate("dvbc0", sizeof(DVBC_RESOURCE_PRIVATE), &psResource);
1880 // func to reg res
1881 UtopiaResourceRegister(pUtopiaModule, psResource, DVBC_POOL_ID_DMD0);
1882 // end function to add res
1883 UtopiaModuleAddResourceEnd(pUtopiaModule, DVBC_POOL_ID_DMD0);
1884
1885
1886 }
1887
1888
1889