1 /** 2 * \file drm.h 3 * Header for the Direct Rendering Manager 4 * 5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 6 * 7 * \par Acknowledgments: 8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. 9 */ 10 11 /* 12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 14 * All rights reserved. 15 * 16 * Permission is hereby granted, free of charge, to any person obtaining a 17 * copy of this software and associated documentation files (the "Software"), 18 * to deal in the Software without restriction, including without limitation 19 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 20 * and/or sell copies of the Software, and to permit persons to whom the 21 * Software is furnished to do so, subject to the following conditions: 22 * 23 * The above copyright notice and this permission notice (including the next 24 * paragraph) shall be included in all copies or substantial portions of the 25 * Software. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 33 * OTHER DEALINGS IN THE SOFTWARE. 34 */ 35 36 #ifndef _DRM_H_ 37 #define _DRM_H_ 38 39 #if defined(__KERNEL__) 40 41 #include <linux/types.h> 42 #include <asm/ioctl.h> 43 typedef unsigned int drm_handle_t; 44 45 #elif defined(__linux__) 46 47 #include <linux/types.h> 48 #include <asm/ioctl.h> 49 typedef unsigned int drm_handle_t; 50 51 #else /* One of the BSDs */ 52 53 #include <sys/ioccom.h> 54 #include <sys/types.h> 55 typedef int8_t __s8; 56 typedef uint8_t __u8; 57 typedef int16_t __s16; 58 typedef uint16_t __u16; 59 typedef int32_t __s32; 60 typedef uint32_t __u32; 61 typedef int64_t __s64; 62 typedef uint64_t __u64; 63 typedef size_t __kernel_size_t; 64 typedef unsigned long drm_handle_t; 65 66 #endif 67 68 #if defined(__cplusplus) 69 extern "C" { 70 #endif 71 72 #define __user 73 74 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ 75 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ 76 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ 77 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ 78 79 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ 80 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ 81 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) 82 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 83 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 84 85 typedef unsigned int drm_context_t; 86 typedef unsigned int drm_drawable_t; 87 typedef unsigned int drm_magic_t; 88 89 /** 90 * Cliprect. 91 * 92 * \warning: If you change this structure, make sure you change 93 * XF86DRIClipRectRec in the server as well 94 * 95 * \note KW: Actually it's illegal to change either for 96 * backwards-compatibility reasons. 97 */ 98 struct drm_clip_rect { 99 unsigned short x1; 100 unsigned short y1; 101 unsigned short x2; 102 unsigned short y2; 103 }; 104 105 /** 106 * Drawable information. 107 */ 108 struct drm_drawable_info { 109 unsigned int num_rects; 110 struct drm_clip_rect *rects; 111 }; 112 113 /** 114 * Texture region, 115 */ 116 struct drm_tex_region { 117 unsigned char next; 118 unsigned char prev; 119 unsigned char in_use; 120 unsigned char padding; 121 unsigned int age; 122 }; 123 124 /** 125 * Hardware lock. 126 * 127 * The lock structure is a simple cache-line aligned integer. To avoid 128 * processor bus contention on a multiprocessor system, there should not be any 129 * other data stored in the same cache line. 130 */ 131 struct drm_hw_lock { 132 __volatile__ unsigned int lock; /**< lock variable */ 133 char padding[60]; /**< Pad to cache line */ 134 }; 135 136 /** 137 * DRM_IOCTL_VERSION ioctl argument type. 138 * 139 * \sa drmGetVersion(). 140 */ 141 struct drm_version { 142 int version_major; /**< Major version */ 143 int version_minor; /**< Minor version */ 144 int version_patchlevel; /**< Patch level */ 145 __kernel_size_t name_len; /**< Length of name buffer */ 146 char __user *name; /**< Name of driver */ 147 __kernel_size_t date_len; /**< Length of date buffer */ 148 char __user *date; /**< User-space buffer to hold date */ 149 __kernel_size_t desc_len; /**< Length of desc buffer */ 150 char __user *desc; /**< User-space buffer to hold desc */ 151 }; 152 153 /** 154 * DRM_IOCTL_GET_UNIQUE ioctl argument type. 155 * 156 * \sa drmGetBusid() and drmSetBusId(). 157 */ 158 struct drm_unique { 159 __kernel_size_t unique_len; /**< Length of unique */ 160 char __user *unique; /**< Unique name for driver instantiation */ 161 }; 162 163 struct drm_list { 164 int count; /**< Length of user-space structures */ 165 struct drm_version __user *version; 166 }; 167 168 struct drm_block { 169 int unused; 170 }; 171 172 /** 173 * DRM_IOCTL_CONTROL ioctl argument type. 174 * 175 * \sa drmCtlInstHandler() and drmCtlUninstHandler(). 176 */ 177 struct drm_control { 178 enum { 179 DRM_ADD_COMMAND, 180 DRM_RM_COMMAND, 181 DRM_INST_HANDLER, 182 DRM_UNINST_HANDLER 183 } func; 184 int irq; 185 }; 186 187 /** 188 * Type of memory to map. 189 */ 190 enum drm_map_type { 191 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ 192 _DRM_REGISTERS = 1, /**< no caching, no core dump */ 193 _DRM_SHM = 2, /**< shared, cached */ 194 _DRM_AGP = 3, /**< AGP/GART */ 195 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ 196 _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */ 197 }; 198 199 /** 200 * Memory mapping flags. 201 */ 202 enum drm_map_flags { 203 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ 204 _DRM_READ_ONLY = 0x02, 205 _DRM_LOCKED = 0x04, /**< shared, cached, locked */ 206 _DRM_KERNEL = 0x08, /**< kernel requires access */ 207 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ 208 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ 209 _DRM_REMOVABLE = 0x40, /**< Removable mapping */ 210 _DRM_DRIVER = 0x80 /**< Managed by driver */ 211 }; 212 213 struct drm_ctx_priv_map { 214 unsigned int ctx_id; /**< Context requesting private mapping */ 215 void *handle; /**< Handle of map */ 216 }; 217 218 /** 219 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls 220 * argument type. 221 * 222 * \sa drmAddMap(). 223 */ 224 struct drm_map { 225 unsigned long offset; /**< Requested physical address (0 for SAREA)*/ 226 unsigned long size; /**< Requested physical size (bytes) */ 227 enum drm_map_type type; /**< Type of memory to map */ 228 enum drm_map_flags flags; /**< Flags */ 229 void *handle; /**< User-space: "Handle" to pass to mmap() */ 230 /**< Kernel-space: kernel-virtual address */ 231 int mtrr; /**< MTRR slot used */ 232 /* Private data */ 233 }; 234 235 /** 236 * DRM_IOCTL_GET_CLIENT ioctl argument type. 237 */ 238 struct drm_client { 239 int idx; /**< Which client desired? */ 240 int auth; /**< Is client authenticated? */ 241 unsigned long pid; /**< Process ID */ 242 unsigned long uid; /**< User ID */ 243 unsigned long magic; /**< Magic */ 244 unsigned long iocs; /**< Ioctl count */ 245 }; 246 247 enum drm_stat_type { 248 _DRM_STAT_LOCK, 249 _DRM_STAT_OPENS, 250 _DRM_STAT_CLOSES, 251 _DRM_STAT_IOCTLS, 252 _DRM_STAT_LOCKS, 253 _DRM_STAT_UNLOCKS, 254 _DRM_STAT_VALUE, /**< Generic value */ 255 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ 256 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ 257 258 _DRM_STAT_IRQ, /**< IRQ */ 259 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ 260 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ 261 _DRM_STAT_DMA, /**< DMA */ 262 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ 263 _DRM_STAT_MISSED /**< Missed DMA opportunity */ 264 /* Add to the *END* of the list */ 265 }; 266 267 /** 268 * DRM_IOCTL_GET_STATS ioctl argument type. 269 */ 270 struct drm_stats { 271 unsigned long count; 272 struct { 273 unsigned long value; 274 enum drm_stat_type type; 275 } data[15]; 276 }; 277 278 /** 279 * Hardware locking flags. 280 */ 281 enum drm_lock_flags { 282 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 283 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 284 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 285 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 286 /* These *HALT* flags aren't supported yet 287 -- they will be used to support the 288 full-screen DGA-like mode. */ 289 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 290 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 291 }; 292 293 /** 294 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. 295 * 296 * \sa drmGetLock() and drmUnlock(). 297 */ 298 struct drm_lock { 299 int context; 300 enum drm_lock_flags flags; 301 }; 302 303 /** 304 * DMA flags 305 * 306 * \warning 307 * These values \e must match xf86drm.h. 308 * 309 * \sa drm_dma. 310 */ 311 enum drm_dma_flags { 312 /* Flags for DMA buffer dispatch */ 313 _DRM_DMA_BLOCK = 0x01, /**< 314 * Block until buffer dispatched. 315 * 316 * \note The buffer may not yet have 317 * been processed by the hardware -- 318 * getting a hardware lock with the 319 * hardware quiescent will ensure 320 * that the buffer has been 321 * processed. 322 */ 323 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 324 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 325 326 /* Flags for DMA buffer request */ 327 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 328 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 329 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 330 }; 331 332 /** 333 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. 334 * 335 * \sa drmAddBufs(). 336 */ 337 struct drm_buf_desc { 338 int count; /**< Number of buffers of this size */ 339 int size; /**< Size in bytes */ 340 int low_mark; /**< Low water mark */ 341 int high_mark; /**< High water mark */ 342 enum { 343 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ 344 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ 345 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ 346 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ 347 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ 348 } flags; 349 unsigned long agp_start; /**< 350 * Start address of where the AGP buffers are 351 * in the AGP aperture 352 */ 353 }; 354 355 /** 356 * DRM_IOCTL_INFO_BUFS ioctl argument type. 357 */ 358 struct drm_buf_info { 359 int count; /**< Entries in list */ 360 struct drm_buf_desc __user *list; 361 }; 362 363 /** 364 * DRM_IOCTL_FREE_BUFS ioctl argument type. 365 */ 366 struct drm_buf_free { 367 int count; 368 int __user *list; 369 }; 370 371 /** 372 * Buffer information 373 * 374 * \sa drm_buf_map. 375 */ 376 struct drm_buf_pub { 377 int idx; /**< Index into the master buffer list */ 378 int total; /**< Buffer size */ 379 int used; /**< Amount of buffer in use (for DMA) */ 380 void __user *address; /**< Address of buffer */ 381 }; 382 383 /** 384 * DRM_IOCTL_MAP_BUFS ioctl argument type. 385 */ 386 struct drm_buf_map { 387 int count; /**< Length of the buffer list */ 388 #ifdef __cplusplus 389 void __user *virt; 390 #else 391 void __user *virtual; /**< Mmap'd area in user-virtual */ 392 #endif 393 struct drm_buf_pub __user *list; /**< Buffer information */ 394 }; 395 396 /** 397 * DRM_IOCTL_DMA ioctl argument type. 398 * 399 * Indices here refer to the offset into the buffer list in drm_buf_get. 400 * 401 * \sa drmDMA(). 402 */ 403 struct drm_dma { 404 int context; /**< Context handle */ 405 int send_count; /**< Number of buffers to send */ 406 int __user *send_indices; /**< List of handles to buffers */ 407 int __user *send_sizes; /**< Lengths of data to send */ 408 enum drm_dma_flags flags; /**< Flags */ 409 int request_count; /**< Number of buffers requested */ 410 int request_size; /**< Desired size for buffers */ 411 int __user *request_indices; /**< Buffer information */ 412 int __user *request_sizes; 413 int granted_count; /**< Number of buffers granted */ 414 }; 415 416 enum drm_ctx_flags { 417 _DRM_CONTEXT_PRESERVED = 0x01, 418 _DRM_CONTEXT_2DONLY = 0x02 419 }; 420 421 /** 422 * DRM_IOCTL_ADD_CTX ioctl argument type. 423 * 424 * \sa drmCreateContext() and drmDestroyContext(). 425 */ 426 struct drm_ctx { 427 drm_context_t handle; 428 enum drm_ctx_flags flags; 429 }; 430 431 /** 432 * DRM_IOCTL_RES_CTX ioctl argument type. 433 */ 434 struct drm_ctx_res { 435 int count; 436 struct drm_ctx __user *contexts; 437 }; 438 439 /** 440 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. 441 */ 442 struct drm_draw { 443 drm_drawable_t handle; 444 }; 445 446 /** 447 * DRM_IOCTL_UPDATE_DRAW ioctl argument type. 448 */ 449 typedef enum { 450 DRM_DRAWABLE_CLIPRECTS 451 } drm_drawable_info_type_t; 452 453 struct drm_update_draw { 454 drm_drawable_t handle; 455 unsigned int type; 456 unsigned int num; 457 unsigned long long data; 458 }; 459 460 /** 461 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. 462 */ 463 struct drm_auth { 464 drm_magic_t magic; 465 }; 466 467 /** 468 * DRM_IOCTL_IRQ_BUSID ioctl argument type. 469 * 470 * \sa drmGetInterruptFromBusID(). 471 */ 472 struct drm_irq_busid { 473 int irq; /**< IRQ number */ 474 int busnum; /**< bus number */ 475 int devnum; /**< device number */ 476 int funcnum; /**< function number */ 477 }; 478 479 enum drm_vblank_seq_type { 480 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 481 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 482 /* bits 1-6 are reserved for high crtcs */ 483 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, 484 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ 485 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ 486 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 487 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 488 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ 489 }; 490 #define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 491 492 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) 493 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ 494 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) 495 496 struct drm_wait_vblank_request { 497 enum drm_vblank_seq_type type; 498 unsigned int sequence; 499 unsigned long signal; 500 }; 501 502 struct drm_wait_vblank_reply { 503 enum drm_vblank_seq_type type; 504 unsigned int sequence; 505 long tval_sec; 506 long tval_usec; 507 }; 508 509 /** 510 * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 511 * 512 * \sa drmWaitVBlank(). 513 */ 514 union drm_wait_vblank { 515 struct drm_wait_vblank_request request; 516 struct drm_wait_vblank_reply reply; 517 }; 518 519 #define _DRM_PRE_MODESET 1 520 #define _DRM_POST_MODESET 2 521 522 /** 523 * DRM_IOCTL_MODESET_CTL ioctl argument type 524 * 525 * \sa drmModesetCtl(). 526 */ 527 struct drm_modeset_ctl { 528 __u32 crtc; 529 __u32 cmd; 530 }; 531 532 /** 533 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 534 * 535 * \sa drmAgpEnable(). 536 */ 537 struct drm_agp_mode { 538 unsigned long mode; /**< AGP mode */ 539 }; 540 541 /** 542 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. 543 * 544 * \sa drmAgpAlloc() and drmAgpFree(). 545 */ 546 struct drm_agp_buffer { 547 unsigned long size; /**< In bytes -- will round to page boundary */ 548 unsigned long handle; /**< Used for binding / unbinding */ 549 unsigned long type; /**< Type of memory to allocate */ 550 unsigned long physical; /**< Physical used by i810 */ 551 }; 552 553 /** 554 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. 555 * 556 * \sa drmAgpBind() and drmAgpUnbind(). 557 */ 558 struct drm_agp_binding { 559 unsigned long handle; /**< From drm_agp_buffer */ 560 unsigned long offset; /**< In bytes -- will round to page boundary */ 561 }; 562 563 /** 564 * DRM_IOCTL_AGP_INFO ioctl argument type. 565 * 566 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), 567 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), 568 * drmAgpVendorId() and drmAgpDeviceId(). 569 */ 570 struct drm_agp_info { 571 int agp_version_major; 572 int agp_version_minor; 573 unsigned long mode; 574 unsigned long aperture_base; /* physical address */ 575 unsigned long aperture_size; /* bytes */ 576 unsigned long memory_allowed; /* bytes */ 577 unsigned long memory_used; 578 579 /* PCI information */ 580 unsigned short id_vendor; 581 unsigned short id_device; 582 }; 583 584 /** 585 * DRM_IOCTL_SG_ALLOC ioctl argument type. 586 */ 587 struct drm_scatter_gather { 588 unsigned long size; /**< In bytes -- will round to page boundary */ 589 unsigned long handle; /**< Used for mapping / unmapping */ 590 }; 591 592 /** 593 * DRM_IOCTL_SET_VERSION ioctl argument type. 594 */ 595 struct drm_set_version { 596 int drm_di_major; 597 int drm_di_minor; 598 int drm_dd_major; 599 int drm_dd_minor; 600 }; 601 602 /** DRM_IOCTL_GEM_CLOSE ioctl argument type */ 603 struct drm_gem_close { 604 /** Handle of the object to be closed. */ 605 __u32 handle; 606 __u32 pad; 607 }; 608 609 /** DRM_IOCTL_GEM_FLINK ioctl argument type */ 610 struct drm_gem_flink { 611 /** Handle for the object being named */ 612 __u32 handle; 613 614 /** Returned global name */ 615 __u32 name; 616 }; 617 618 /** DRM_IOCTL_GEM_OPEN ioctl argument type */ 619 struct drm_gem_open { 620 /** Name of object being opened */ 621 __u32 name; 622 623 /** Returned handle for the object */ 624 __u32 handle; 625 626 /** Returned size of the object */ 627 __u64 size; 628 }; 629 630 #define DRM_CAP_DUMB_BUFFER 0x1 631 #define DRM_CAP_VBLANK_HIGH_CRTC 0x2 632 #define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 633 #define DRM_CAP_DUMB_PREFER_SHADOW 0x4 634 #define DRM_CAP_PRIME 0x5 635 #define DRM_PRIME_CAP_IMPORT 0x1 636 #define DRM_PRIME_CAP_EXPORT 0x2 637 #define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 638 #define DRM_CAP_ASYNC_PAGE_FLIP 0x7 639 /* 640 * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight 641 * combination for the hardware cursor. The intention is that a hardware 642 * agnostic userspace can query a cursor plane size to use. 643 * 644 * Note that the cross-driver contract is to merely return a valid size; 645 * drivers are free to attach another meaning on top, eg. i915 returns the 646 * maximum plane size. 647 */ 648 #define DRM_CAP_CURSOR_WIDTH 0x8 649 #define DRM_CAP_CURSOR_HEIGHT 0x9 650 #define DRM_CAP_ADDFB2_MODIFIERS 0x10 651 #define DRM_CAP_PAGE_FLIP_TARGET 0x11 652 #define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12 653 #define DRM_CAP_SYNCOBJ 0x13 654 655 /** DRM_IOCTL_GET_CAP ioctl argument type */ 656 struct drm_get_cap { 657 __u64 capability; 658 __u64 value; 659 }; 660 661 /** 662 * DRM_CLIENT_CAP_STEREO_3D 663 * 664 * if set to 1, the DRM core will expose the stereo 3D capabilities of the 665 * monitor by advertising the supported 3D layouts in the flags of struct 666 * drm_mode_modeinfo. 667 */ 668 #define DRM_CLIENT_CAP_STEREO_3D 1 669 670 /** 671 * DRM_CLIENT_CAP_UNIVERSAL_PLANES 672 * 673 * If set to 1, the DRM core will expose all planes (overlay, primary, and 674 * cursor) to userspace. 675 */ 676 #define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 677 678 /** 679 * DRM_CLIENT_CAP_ATOMIC 680 * 681 * If set to 1, the DRM core will expose atomic properties to userspace 682 */ 683 #define DRM_CLIENT_CAP_ATOMIC 3 684 685 /** 686 * DRM_CLIENT_CAP_ASPECT_RATIO 687 * 688 * If set to 1, the DRM core will provide aspect ratio information in modes. 689 */ 690 #define DRM_CLIENT_CAP_ASPECT_RATIO 4 691 692 /** 693 * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 694 * 695 * If set to 1, the DRM core will expose special connectors to be used for 696 * writing back to memory the scene setup in the commit. Depends on client 697 * also supporting DRM_CLIENT_CAP_ATOMIC 698 */ 699 #define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5 700 701 /* 702 * DRM_CLIENT_CAP_SHARE_PLANES 703 * 704 * If set to 1, the DRM core will expose share planes to userspace. 705 */ 706 #define DRM_CLIENT_CAP_SHARE_PLANES 6 707 708 /** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ 709 struct drm_set_client_cap { 710 __u64 capability; 711 __u64 value; 712 }; 713 714 #define DRM_RDWR O_RDWR 715 #define DRM_CLOEXEC O_CLOEXEC 716 struct drm_prime_handle { 717 __u32 handle; 718 719 /** Flags.. only applicable for handle->fd */ 720 __u32 flags; 721 722 /** Returned dmabuf file descriptor */ 723 __s32 fd; 724 }; 725 726 struct drm_syncobj_create { 727 __u32 handle; 728 #define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0) 729 __u32 flags; 730 }; 731 732 struct drm_syncobj_destroy { 733 __u32 handle; 734 __u32 pad; 735 }; 736 737 #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0) 738 #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0) 739 struct drm_syncobj_handle { 740 __u32 handle; 741 __u32 flags; 742 743 __s32 fd; 744 __u32 pad; 745 }; 746 747 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) 748 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) 749 struct drm_syncobj_wait { 750 __u64 handles; 751 /* absolute timeout */ 752 __s64 timeout_nsec; 753 __u32 count_handles; 754 __u32 flags; 755 __u32 first_signaled; /* only valid when not waiting all */ 756 __u32 pad; 757 }; 758 759 struct drm_syncobj_array { 760 __u64 handles; 761 __u32 count_handles; 762 __u32 pad; 763 }; 764 765 /* Query current scanout sequence number */ 766 struct drm_crtc_get_sequence { 767 __u32 crtc_id; /* requested crtc_id */ 768 __u32 active; /* return: crtc output is active */ 769 __u64 sequence; /* return: most recent vblank sequence */ 770 __s64 sequence_ns; /* return: most recent time of first pixel out */ 771 }; 772 773 /* Queue event to be delivered at specified sequence. Time stamp marks 774 * when the first pixel of the refresh cycle leaves the display engine 775 * for the display 776 */ 777 #define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */ 778 #define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */ 779 780 struct drm_crtc_queue_sequence { 781 __u32 crtc_id; 782 __u32 flags; 783 __u64 sequence; /* on input, target sequence. on output, actual sequence */ 784 __u64 user_data; /* user data passed to event */ 785 }; 786 787 #if defined(__cplusplus) 788 } 789 #endif 790 791 #include "drm_mode.h" 792 793 #if defined(__cplusplus) 794 extern "C" { 795 #endif 796 797 #define DRM_IOCTL_BASE 'd' 798 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 799 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 800 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) 801 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) 802 803 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) 804 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) 805 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) 806 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) 807 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) 808 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) 809 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) 810 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) 811 #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) 812 #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) 813 #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) 814 #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) 815 #define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) 816 #define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap) 817 818 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) 819 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) 820 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) 821 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) 822 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) 823 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) 824 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) 825 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) 826 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) 827 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) 828 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) 829 830 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) 831 832 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) 833 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) 834 835 #define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) 836 #define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) 837 838 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) 839 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) 840 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) 841 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) 842 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) 843 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) 844 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) 845 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) 846 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) 847 #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) 848 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) 849 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) 850 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) 851 852 #define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) 853 #define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) 854 855 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) 856 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) 857 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) 858 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) 859 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) 860 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) 861 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) 862 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) 863 864 #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) 865 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) 866 867 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) 868 869 #define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence) 870 #define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence) 871 872 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) 873 874 #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) 875 #define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) 876 #define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) 877 #define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) 878 #define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) 879 #define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) 880 #define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) 881 #define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) 882 #define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */ 883 #define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */ 884 885 #define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) 886 #define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) 887 #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) 888 #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) 889 #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) 890 #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) 891 #define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) 892 #define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) 893 894 #define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) 895 #define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) 896 #define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) 897 #define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) 898 #define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) 899 #define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) 900 #define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) 901 #define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) 902 #define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) 903 #define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) 904 #define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) 905 #define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) 906 #define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) 907 908 #define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create) 909 #define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy) 910 #define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle) 911 #define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle) 912 #define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait) 913 #define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array) 914 #define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array) 915 916 #define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease) 917 #define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees) 918 #define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) 919 #define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) 920 921 /** 922 * Device specific ioctls should only be in their respective headers 923 * The device specific ioctl range is from 0x40 to 0x9f. 924 * Generic IOCTLS restart at 0xA0. 925 * 926 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and 927 * drmCommandReadWrite(). 928 */ 929 #define DRM_COMMAND_BASE 0x40 930 #define DRM_COMMAND_END 0xA0 931 932 /** 933 * Header for events written back to userspace on the drm fd. The 934 * type defines the type of event, the length specifies the total 935 * length of the event (including the header), and user_data is 936 * typically a 64 bit value passed with the ioctl that triggered the 937 * event. A read on the drm fd will always only return complete 938 * events, that is, if for example the read buffer is 100 bytes, and 939 * there are two 64 byte events pending, only one will be returned. 940 * 941 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and 942 * up are chipset specific. 943 */ 944 struct drm_event { 945 __u32 type; 946 __u32 length; 947 }; 948 949 #define DRM_EVENT_VBLANK 0x01 950 #define DRM_EVENT_FLIP_COMPLETE 0x02 951 #define DRM_EVENT_CRTC_SEQUENCE 0x03 952 953 struct drm_event_vblank { 954 struct drm_event base; 955 __u64 user_data; 956 __u32 tv_sec; 957 __u32 tv_usec; 958 __u32 sequence; 959 __u32 crtc_id; /* 0 on older kernels that do not support this */ 960 }; 961 962 /* Event delivered at sequence. Time stamp marks when the first pixel 963 * of the refresh cycle leaves the display engine for the display 964 */ 965 struct drm_event_crtc_sequence { 966 struct drm_event base; 967 __u64 user_data; 968 __s64 time_ns; 969 __u64 sequence; 970 }; 971 972 /* typedef area */ 973 #ifndef __KERNEL__ 974 typedef struct drm_clip_rect drm_clip_rect_t; 975 typedef struct drm_drawable_info drm_drawable_info_t; 976 typedef struct drm_tex_region drm_tex_region_t; 977 typedef struct drm_hw_lock drm_hw_lock_t; 978 typedef struct drm_version drm_version_t; 979 typedef struct drm_unique drm_unique_t; 980 typedef struct drm_list drm_list_t; 981 typedef struct drm_block drm_block_t; 982 typedef struct drm_control drm_control_t; 983 typedef enum drm_map_type drm_map_type_t; 984 typedef enum drm_map_flags drm_map_flags_t; 985 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; 986 typedef struct drm_map drm_map_t; 987 typedef struct drm_client drm_client_t; 988 typedef enum drm_stat_type drm_stat_type_t; 989 typedef struct drm_stats drm_stats_t; 990 typedef enum drm_lock_flags drm_lock_flags_t; 991 typedef struct drm_lock drm_lock_t; 992 typedef enum drm_dma_flags drm_dma_flags_t; 993 typedef struct drm_buf_desc drm_buf_desc_t; 994 typedef struct drm_buf_info drm_buf_info_t; 995 typedef struct drm_buf_free drm_buf_free_t; 996 typedef struct drm_buf_pub drm_buf_pub_t; 997 typedef struct drm_buf_map drm_buf_map_t; 998 typedef struct drm_dma drm_dma_t; 999 typedef union drm_wait_vblank drm_wait_vblank_t; 1000 typedef struct drm_agp_mode drm_agp_mode_t; 1001 typedef enum drm_ctx_flags drm_ctx_flags_t; 1002 typedef struct drm_ctx drm_ctx_t; 1003 typedef struct drm_ctx_res drm_ctx_res_t; 1004 typedef struct drm_draw drm_draw_t; 1005 typedef struct drm_update_draw drm_update_draw_t; 1006 typedef struct drm_auth drm_auth_t; 1007 typedef struct drm_irq_busid drm_irq_busid_t; 1008 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; 1009 1010 typedef struct drm_agp_buffer drm_agp_buffer_t; 1011 typedef struct drm_agp_binding drm_agp_binding_t; 1012 typedef struct drm_agp_info drm_agp_info_t; 1013 typedef struct drm_scatter_gather drm_scatter_gather_t; 1014 typedef struct drm_set_version drm_set_version_t; 1015 #endif 1016 1017 #if defined(__cplusplus) 1018 } 1019 #endif 1020 1021 #endif 1022